ti_am335x_tscadc.c 9.7 KB

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  1. /*
  2. * TI Touch Screen / ADC MFD driver
  3. *
  4. * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation version 2.
  9. *
  10. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11. * kind, whether express or implied; without even the implied warranty
  12. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/module.h>
  16. #include <linux/slab.h>
  17. #include <linux/err.h>
  18. #include <linux/io.h>
  19. #include <linux/clk.h>
  20. #include <linux/regmap.h>
  21. #include <linux/mfd/core.h>
  22. #include <linux/pm_runtime.h>
  23. #include <linux/of.h>
  24. #include <linux/of_device.h>
  25. #include <linux/sched.h>
  26. #include <linux/mfd/ti_am335x_tscadc.h>
  27. static unsigned int tscadc_readl(struct ti_tscadc_dev *tsadc, unsigned int reg)
  28. {
  29. unsigned int val;
  30. regmap_read(tsadc->regmap_tscadc, reg, &val);
  31. return val;
  32. }
  33. static void tscadc_writel(struct ti_tscadc_dev *tsadc, unsigned int reg,
  34. unsigned int val)
  35. {
  36. regmap_write(tsadc->regmap_tscadc, reg, val);
  37. }
  38. static const struct regmap_config tscadc_regmap_config = {
  39. .name = "ti_tscadc",
  40. .reg_bits = 32,
  41. .reg_stride = 4,
  42. .val_bits = 32,
  43. };
  44. void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val)
  45. {
  46. unsigned long flags;
  47. spin_lock_irqsave(&tsadc->reg_lock, flags);
  48. tsadc->reg_se_cache |= val;
  49. if (tsadc->adc_waiting)
  50. wake_up(&tsadc->reg_se_wait);
  51. else if (!tsadc->adc_in_use)
  52. tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
  53. spin_unlock_irqrestore(&tsadc->reg_lock, flags);
  54. }
  55. EXPORT_SYMBOL_GPL(am335x_tsc_se_set_cache);
  56. static void am335x_tscadc_need_adc(struct ti_tscadc_dev *tsadc)
  57. {
  58. DEFINE_WAIT(wait);
  59. u32 reg;
  60. /*
  61. * disable TSC steps so it does not run while the ADC is using it. If
  62. * write 0 while it is running (it just started or was already running)
  63. * then it completes all steps that were enabled and stops then.
  64. */
  65. tscadc_writel(tsadc, REG_SE, 0);
  66. reg = tscadc_readl(tsadc, REG_ADCFSM);
  67. if (reg & SEQ_STATUS) {
  68. tsadc->adc_waiting = true;
  69. prepare_to_wait(&tsadc->reg_se_wait, &wait,
  70. TASK_UNINTERRUPTIBLE);
  71. spin_unlock_irq(&tsadc->reg_lock);
  72. schedule();
  73. spin_lock_irq(&tsadc->reg_lock);
  74. finish_wait(&tsadc->reg_se_wait, &wait);
  75. reg = tscadc_readl(tsadc, REG_ADCFSM);
  76. WARN_ON(reg & SEQ_STATUS);
  77. tsadc->adc_waiting = false;
  78. }
  79. tsadc->adc_in_use = true;
  80. }
  81. void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val)
  82. {
  83. spin_lock_irq(&tsadc->reg_lock);
  84. tsadc->reg_se_cache |= val;
  85. am335x_tscadc_need_adc(tsadc);
  86. tscadc_writel(tsadc, REG_SE, val);
  87. spin_unlock_irq(&tsadc->reg_lock);
  88. }
  89. EXPORT_SYMBOL_GPL(am335x_tsc_se_set_once);
  90. void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc)
  91. {
  92. unsigned long flags;
  93. spin_lock_irqsave(&tsadc->reg_lock, flags);
  94. tsadc->adc_in_use = false;
  95. tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
  96. spin_unlock_irqrestore(&tsadc->reg_lock, flags);
  97. }
  98. EXPORT_SYMBOL_GPL(am335x_tsc_se_adc_done);
  99. void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val)
  100. {
  101. unsigned long flags;
  102. spin_lock_irqsave(&tsadc->reg_lock, flags);
  103. tsadc->reg_se_cache &= ~val;
  104. tscadc_writel(tsadc, REG_SE, tsadc->reg_se_cache);
  105. spin_unlock_irqrestore(&tsadc->reg_lock, flags);
  106. }
  107. EXPORT_SYMBOL_GPL(am335x_tsc_se_clr);
  108. static void tscadc_idle_config(struct ti_tscadc_dev *config)
  109. {
  110. unsigned int idleconfig;
  111. idleconfig = STEPCONFIG_YNN | STEPCONFIG_INM_ADCREFM |
  112. STEPCONFIG_INP_ADCREFM | STEPCONFIG_YPN;
  113. tscadc_writel(config, REG_IDLECONFIG, idleconfig);
  114. }
  115. static int ti_tscadc_probe(struct platform_device *pdev)
  116. {
  117. struct ti_tscadc_dev *tscadc;
  118. struct resource *res;
  119. struct clk *clk;
  120. struct device_node *node = pdev->dev.of_node;
  121. struct mfd_cell *cell;
  122. struct property *prop;
  123. const __be32 *cur;
  124. u32 val;
  125. int err, ctrl;
  126. int clock_rate;
  127. int tsc_wires = 0, adc_channels = 0, total_channels;
  128. int readouts = 0;
  129. if (!pdev->dev.of_node) {
  130. dev_err(&pdev->dev, "Could not find valid DT data.\n");
  131. return -EINVAL;
  132. }
  133. node = of_get_child_by_name(pdev->dev.of_node, "tsc");
  134. of_property_read_u32(node, "ti,wires", &tsc_wires);
  135. of_property_read_u32(node, "ti,coordiante-readouts", &readouts);
  136. node = of_get_child_by_name(pdev->dev.of_node, "adc");
  137. of_property_for_each_u32(node, "ti,adc-channels", prop, cur, val) {
  138. adc_channels++;
  139. if (val > 7) {
  140. dev_err(&pdev->dev, " PIN numbers are 0..7 (not %d)\n",
  141. val);
  142. return -EINVAL;
  143. }
  144. }
  145. total_channels = tsc_wires + adc_channels;
  146. if (total_channels > 8) {
  147. dev_err(&pdev->dev, "Number of i/p channels more than 8\n");
  148. return -EINVAL;
  149. }
  150. if (total_channels == 0) {
  151. dev_err(&pdev->dev, "Need atleast one channel.\n");
  152. return -EINVAL;
  153. }
  154. if (readouts * 2 + 2 + adc_channels > 16) {
  155. dev_err(&pdev->dev, "Too many step configurations requested\n");
  156. return -EINVAL;
  157. }
  158. /* Allocate memory for device */
  159. tscadc = devm_kzalloc(&pdev->dev,
  160. sizeof(struct ti_tscadc_dev), GFP_KERNEL);
  161. if (!tscadc) {
  162. dev_err(&pdev->dev, "failed to allocate memory.\n");
  163. return -ENOMEM;
  164. }
  165. tscadc->dev = &pdev->dev;
  166. err = platform_get_irq(pdev, 0);
  167. if (err < 0) {
  168. dev_err(&pdev->dev, "no irq ID is specified.\n");
  169. goto ret;
  170. } else
  171. tscadc->irq = err;
  172. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  173. tscadc->tscadc_base = devm_ioremap_resource(&pdev->dev, res);
  174. if (IS_ERR(tscadc->tscadc_base))
  175. return PTR_ERR(tscadc->tscadc_base);
  176. tscadc->regmap_tscadc = devm_regmap_init_mmio(&pdev->dev,
  177. tscadc->tscadc_base, &tscadc_regmap_config);
  178. if (IS_ERR(tscadc->regmap_tscadc)) {
  179. dev_err(&pdev->dev, "regmap init failed\n");
  180. err = PTR_ERR(tscadc->regmap_tscadc);
  181. goto ret;
  182. }
  183. spin_lock_init(&tscadc->reg_lock);
  184. init_waitqueue_head(&tscadc->reg_se_wait);
  185. pm_runtime_enable(&pdev->dev);
  186. pm_runtime_get_sync(&pdev->dev);
  187. /*
  188. * The TSC_ADC_Subsystem has 2 clock domains
  189. * OCP_CLK and ADC_CLK.
  190. * The ADC clock is expected to run at target of 3MHz,
  191. * and expected to capture 12-bit data at a rate of 200 KSPS.
  192. * The TSC_ADC_SS controller design assumes the OCP clock is
  193. * at least 6x faster than the ADC clock.
  194. */
  195. clk = clk_get(&pdev->dev, "adc_tsc_fck");
  196. if (IS_ERR(clk)) {
  197. dev_err(&pdev->dev, "failed to get TSC fck\n");
  198. err = PTR_ERR(clk);
  199. goto err_disable_clk;
  200. }
  201. clock_rate = clk_get_rate(clk);
  202. clk_put(clk);
  203. tscadc->clk_div = clock_rate / ADC_CLK;
  204. /* TSCADC_CLKDIV needs to be configured to the value minus 1 */
  205. tscadc->clk_div--;
  206. tscadc_writel(tscadc, REG_CLKDIV, tscadc->clk_div);
  207. /* Set the control register bits */
  208. ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
  209. tscadc_writel(tscadc, REG_CTRL, ctrl);
  210. /* Set register bits for Idle Config Mode */
  211. if (tsc_wires > 0) {
  212. tscadc->tsc_wires = tsc_wires;
  213. if (tsc_wires == 5)
  214. ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
  215. else
  216. ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
  217. tscadc_idle_config(tscadc);
  218. }
  219. /* Enable the TSC module enable bit */
  220. ctrl |= CNTRLREG_TSCSSENB;
  221. tscadc_writel(tscadc, REG_CTRL, ctrl);
  222. tscadc->used_cells = 0;
  223. tscadc->tsc_cell = -1;
  224. tscadc->adc_cell = -1;
  225. /* TSC Cell */
  226. if (tsc_wires > 0) {
  227. tscadc->tsc_cell = tscadc->used_cells;
  228. cell = &tscadc->cells[tscadc->used_cells++];
  229. cell->name = "TI-am335x-tsc";
  230. cell->of_compatible = "ti,am3359-tsc";
  231. cell->platform_data = &tscadc;
  232. cell->pdata_size = sizeof(tscadc);
  233. }
  234. /* ADC Cell */
  235. if (adc_channels > 0) {
  236. tscadc->adc_cell = tscadc->used_cells;
  237. cell = &tscadc->cells[tscadc->used_cells++];
  238. cell->name = "TI-am335x-adc";
  239. cell->of_compatible = "ti,am3359-adc";
  240. cell->platform_data = &tscadc;
  241. cell->pdata_size = sizeof(tscadc);
  242. }
  243. err = mfd_add_devices(&pdev->dev, pdev->id, tscadc->cells,
  244. tscadc->used_cells, NULL, 0, NULL);
  245. if (err < 0)
  246. goto err_disable_clk;
  247. device_init_wakeup(&pdev->dev, true);
  248. platform_set_drvdata(pdev, tscadc);
  249. return 0;
  250. err_disable_clk:
  251. pm_runtime_put_sync(&pdev->dev);
  252. pm_runtime_disable(&pdev->dev);
  253. ret:
  254. return err;
  255. }
  256. static int ti_tscadc_remove(struct platform_device *pdev)
  257. {
  258. struct ti_tscadc_dev *tscadc = platform_get_drvdata(pdev);
  259. tscadc_writel(tscadc, REG_SE, 0x00);
  260. pm_runtime_put_sync(&pdev->dev);
  261. pm_runtime_disable(&pdev->dev);
  262. mfd_remove_devices(tscadc->dev);
  263. return 0;
  264. }
  265. #ifdef CONFIG_PM
  266. static int tscadc_suspend(struct device *dev)
  267. {
  268. struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
  269. tscadc_writel(tscadc_dev, REG_SE, 0x00);
  270. pm_runtime_put_sync(dev);
  271. return 0;
  272. }
  273. static int tscadc_resume(struct device *dev)
  274. {
  275. struct ti_tscadc_dev *tscadc_dev = dev_get_drvdata(dev);
  276. u32 ctrl;
  277. pm_runtime_get_sync(dev);
  278. /* context restore */
  279. ctrl = CNTRLREG_STEPCONFIGWRT | CNTRLREG_STEPID;
  280. tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
  281. if (tscadc_dev->tsc_cell != -1) {
  282. if (tscadc_dev->tsc_wires == 5)
  283. ctrl |= CNTRLREG_5WIRE | CNTRLREG_TSCENB;
  284. else
  285. ctrl |= CNTRLREG_4WIRE | CNTRLREG_TSCENB;
  286. tscadc_idle_config(tscadc_dev);
  287. }
  288. ctrl |= CNTRLREG_TSCSSENB;
  289. tscadc_writel(tscadc_dev, REG_CTRL, ctrl);
  290. tscadc_writel(tscadc_dev, REG_CLKDIV, tscadc_dev->clk_div);
  291. return 0;
  292. }
  293. static const struct dev_pm_ops tscadc_pm_ops = {
  294. .suspend = tscadc_suspend,
  295. .resume = tscadc_resume,
  296. };
  297. #define TSCADC_PM_OPS (&tscadc_pm_ops)
  298. #else
  299. #define TSCADC_PM_OPS NULL
  300. #endif
  301. static const struct of_device_id ti_tscadc_dt_ids[] = {
  302. { .compatible = "ti,am3359-tscadc", },
  303. { }
  304. };
  305. MODULE_DEVICE_TABLE(of, ti_tscadc_dt_ids);
  306. static struct platform_driver ti_tscadc_driver = {
  307. .driver = {
  308. .name = "ti_am3359-tscadc",
  309. .pm = TSCADC_PM_OPS,
  310. .of_match_table = ti_tscadc_dt_ids,
  311. },
  312. .probe = ti_tscadc_probe,
  313. .remove = ti_tscadc_remove,
  314. };
  315. module_platform_driver(ti_tscadc_driver);
  316. MODULE_DESCRIPTION("TI touchscreen / ADC MFD controller driver");
  317. MODULE_AUTHOR("Rachna Patil <rachna@ti.com>");
  318. MODULE_LICENSE("GPL");