arizona-core.c 26 KB

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  1. /*
  2. * Arizona core driver
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/err.h>
  14. #include <linux/gpio.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/mfd/core.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/of_gpio.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/regmap.h>
  23. #include <linux/regulator/consumer.h>
  24. #include <linux/regulator/machine.h>
  25. #include <linux/slab.h>
  26. #include <linux/mfd/arizona/core.h>
  27. #include <linux/mfd/arizona/registers.h>
  28. #include "arizona.h"
  29. static const char *wm5102_core_supplies[] = {
  30. "AVDD",
  31. "DBVDD1",
  32. };
  33. int arizona_clk32k_enable(struct arizona *arizona)
  34. {
  35. int ret = 0;
  36. mutex_lock(&arizona->clk_lock);
  37. arizona->clk32k_ref++;
  38. if (arizona->clk32k_ref == 1) {
  39. switch (arizona->pdata.clk32k_src) {
  40. case ARIZONA_32KZ_MCLK1:
  41. ret = pm_runtime_get_sync(arizona->dev);
  42. if (ret != 0)
  43. goto out;
  44. break;
  45. }
  46. ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  47. ARIZONA_CLK_32K_ENA,
  48. ARIZONA_CLK_32K_ENA);
  49. }
  50. out:
  51. if (ret != 0)
  52. arizona->clk32k_ref--;
  53. mutex_unlock(&arizona->clk_lock);
  54. return ret;
  55. }
  56. EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
  57. int arizona_clk32k_disable(struct arizona *arizona)
  58. {
  59. int ret = 0;
  60. mutex_lock(&arizona->clk_lock);
  61. BUG_ON(arizona->clk32k_ref <= 0);
  62. arizona->clk32k_ref--;
  63. if (arizona->clk32k_ref == 0) {
  64. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  65. ARIZONA_CLK_32K_ENA, 0);
  66. switch (arizona->pdata.clk32k_src) {
  67. case ARIZONA_32KZ_MCLK1:
  68. pm_runtime_put_sync(arizona->dev);
  69. break;
  70. }
  71. }
  72. mutex_unlock(&arizona->clk_lock);
  73. return ret;
  74. }
  75. EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
  76. static irqreturn_t arizona_clkgen_err(int irq, void *data)
  77. {
  78. struct arizona *arizona = data;
  79. dev_err(arizona->dev, "CLKGEN error\n");
  80. return IRQ_HANDLED;
  81. }
  82. static irqreturn_t arizona_underclocked(int irq, void *data)
  83. {
  84. struct arizona *arizona = data;
  85. unsigned int val;
  86. int ret;
  87. ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
  88. &val);
  89. if (ret != 0) {
  90. dev_err(arizona->dev, "Failed to read underclock status: %d\n",
  91. ret);
  92. return IRQ_NONE;
  93. }
  94. if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
  95. dev_err(arizona->dev, "AIF3 underclocked\n");
  96. if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
  97. dev_err(arizona->dev, "AIF2 underclocked\n");
  98. if (val & ARIZONA_AIF1_UNDERCLOCKED_STS)
  99. dev_err(arizona->dev, "AIF1 underclocked\n");
  100. if (val & ARIZONA_ISRC3_UNDERCLOCKED_STS)
  101. dev_err(arizona->dev, "ISRC3 underclocked\n");
  102. if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
  103. dev_err(arizona->dev, "ISRC2 underclocked\n");
  104. if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
  105. dev_err(arizona->dev, "ISRC1 underclocked\n");
  106. if (val & ARIZONA_FX_UNDERCLOCKED_STS)
  107. dev_err(arizona->dev, "FX underclocked\n");
  108. if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
  109. dev_err(arizona->dev, "ASRC underclocked\n");
  110. if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
  111. dev_err(arizona->dev, "DAC underclocked\n");
  112. if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
  113. dev_err(arizona->dev, "ADC underclocked\n");
  114. if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
  115. dev_err(arizona->dev, "Mixer dropped sample\n");
  116. return IRQ_HANDLED;
  117. }
  118. static irqreturn_t arizona_overclocked(int irq, void *data)
  119. {
  120. struct arizona *arizona = data;
  121. unsigned int val[2];
  122. int ret;
  123. ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
  124. &val[0], 2);
  125. if (ret != 0) {
  126. dev_err(arizona->dev, "Failed to read overclock status: %d\n",
  127. ret);
  128. return IRQ_NONE;
  129. }
  130. if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
  131. dev_err(arizona->dev, "PWM overclocked\n");
  132. if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
  133. dev_err(arizona->dev, "FX core overclocked\n");
  134. if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
  135. dev_err(arizona->dev, "DAC SYS overclocked\n");
  136. if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
  137. dev_err(arizona->dev, "DAC WARP overclocked\n");
  138. if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
  139. dev_err(arizona->dev, "ADC overclocked\n");
  140. if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
  141. dev_err(arizona->dev, "Mixer overclocked\n");
  142. if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
  143. dev_err(arizona->dev, "AIF3 overclocked\n");
  144. if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
  145. dev_err(arizona->dev, "AIF2 overclocked\n");
  146. if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
  147. dev_err(arizona->dev, "AIF1 overclocked\n");
  148. if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
  149. dev_err(arizona->dev, "Pad control overclocked\n");
  150. if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
  151. dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
  152. if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
  153. dev_err(arizona->dev, "Slimbus async overclocked\n");
  154. if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
  155. dev_err(arizona->dev, "Slimbus sync overclocked\n");
  156. if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
  157. dev_err(arizona->dev, "ASRC async system overclocked\n");
  158. if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
  159. dev_err(arizona->dev, "ASRC async WARP overclocked\n");
  160. if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
  161. dev_err(arizona->dev, "ASRC sync system overclocked\n");
  162. if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
  163. dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
  164. if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
  165. dev_err(arizona->dev, "DSP1 overclocked\n");
  166. if (val[1] & ARIZONA_ISRC3_OVERCLOCKED_STS)
  167. dev_err(arizona->dev, "ISRC3 overclocked\n");
  168. if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
  169. dev_err(arizona->dev, "ISRC2 overclocked\n");
  170. if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
  171. dev_err(arizona->dev, "ISRC1 overclocked\n");
  172. return IRQ_HANDLED;
  173. }
  174. static int arizona_poll_reg(struct arizona *arizona,
  175. int timeout, unsigned int reg,
  176. unsigned int mask, unsigned int target)
  177. {
  178. unsigned int val = 0;
  179. int ret, i;
  180. for (i = 0; i < timeout; i++) {
  181. ret = regmap_read(arizona->regmap, reg, &val);
  182. if (ret != 0) {
  183. dev_err(arizona->dev, "Failed to read reg %u: %d\n",
  184. reg, ret);
  185. continue;
  186. }
  187. if ((val & mask) == target)
  188. return 0;
  189. msleep(1);
  190. }
  191. dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val);
  192. return -ETIMEDOUT;
  193. }
  194. static int arizona_wait_for_boot(struct arizona *arizona)
  195. {
  196. int ret;
  197. /*
  198. * We can't use an interrupt as we need to runtime resume to do so,
  199. * we won't race with the interrupt handler as it'll be blocked on
  200. * runtime resume.
  201. */
  202. ret = arizona_poll_reg(arizona, 5, ARIZONA_INTERRUPT_RAW_STATUS_5,
  203. ARIZONA_BOOT_DONE_STS, ARIZONA_BOOT_DONE_STS);
  204. if (!ret)
  205. regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
  206. ARIZONA_BOOT_DONE_STS);
  207. pm_runtime_mark_last_busy(arizona->dev);
  208. return ret;
  209. }
  210. static int arizona_apply_hardware_patch(struct arizona* arizona)
  211. {
  212. unsigned int fll, sysclk;
  213. int ret, err;
  214. /* Cache existing FLL and SYSCLK settings */
  215. ret = regmap_read(arizona->regmap, ARIZONA_FLL1_CONTROL_1, &fll);
  216. if (ret != 0) {
  217. dev_err(arizona->dev, "Failed to cache FLL settings: %d\n",
  218. ret);
  219. return ret;
  220. }
  221. ret = regmap_read(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, &sysclk);
  222. if (ret != 0) {
  223. dev_err(arizona->dev, "Failed to cache SYSCLK settings: %d\n",
  224. ret);
  225. return ret;
  226. }
  227. /* Start up SYSCLK using the FLL in free running mode */
  228. ret = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1,
  229. ARIZONA_FLL1_ENA | ARIZONA_FLL1_FREERUN);
  230. if (ret != 0) {
  231. dev_err(arizona->dev,
  232. "Failed to start FLL in freerunning mode: %d\n",
  233. ret);
  234. return ret;
  235. }
  236. ret = arizona_poll_reg(arizona, 25, ARIZONA_INTERRUPT_RAW_STATUS_5,
  237. ARIZONA_FLL1_CLOCK_OK_STS,
  238. ARIZONA_FLL1_CLOCK_OK_STS);
  239. if (ret != 0) {
  240. ret = -ETIMEDOUT;
  241. goto err_fll;
  242. }
  243. ret = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, 0x0144);
  244. if (ret != 0) {
  245. dev_err(arizona->dev, "Failed to start SYSCLK: %d\n", ret);
  246. goto err_fll;
  247. }
  248. /* Start the write sequencer and wait for it to finish */
  249. ret = regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  250. ARIZONA_WSEQ_ENA | ARIZONA_WSEQ_START | 160);
  251. if (ret != 0) {
  252. dev_err(arizona->dev, "Failed to start write sequencer: %d\n",
  253. ret);
  254. goto err_sysclk;
  255. }
  256. ret = arizona_poll_reg(arizona, 5, ARIZONA_WRITE_SEQUENCER_CTRL_1,
  257. ARIZONA_WSEQ_BUSY, 0);
  258. if (ret != 0) {
  259. regmap_write(arizona->regmap, ARIZONA_WRITE_SEQUENCER_CTRL_0,
  260. ARIZONA_WSEQ_ABORT);
  261. ret = -ETIMEDOUT;
  262. }
  263. err_sysclk:
  264. err = regmap_write(arizona->regmap, ARIZONA_SYSTEM_CLOCK_1, sysclk);
  265. if (err != 0) {
  266. dev_err(arizona->dev,
  267. "Failed to re-apply old SYSCLK settings: %d\n",
  268. err);
  269. }
  270. err_fll:
  271. err = regmap_write(arizona->regmap, ARIZONA_FLL1_CONTROL_1, fll);
  272. if (err != 0) {
  273. dev_err(arizona->dev,
  274. "Failed to re-apply old FLL settings: %d\n",
  275. err);
  276. }
  277. if (ret != 0)
  278. return ret;
  279. else
  280. return err;
  281. }
  282. #ifdef CONFIG_PM
  283. static int arizona_runtime_resume(struct device *dev)
  284. {
  285. struct arizona *arizona = dev_get_drvdata(dev);
  286. int ret;
  287. dev_dbg(arizona->dev, "Leaving AoD mode\n");
  288. ret = regulator_enable(arizona->dcvdd);
  289. if (ret != 0) {
  290. dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret);
  291. return ret;
  292. }
  293. regcache_cache_only(arizona->regmap, false);
  294. switch (arizona->type) {
  295. case WM5102:
  296. if (arizona->external_dcvdd) {
  297. ret = regmap_update_bits(arizona->regmap,
  298. ARIZONA_ISOLATION_CONTROL,
  299. ARIZONA_ISOLATE_DCVDD1, 0);
  300. if (ret != 0) {
  301. dev_err(arizona->dev,
  302. "Failed to connect DCVDD: %d\n", ret);
  303. goto err;
  304. }
  305. }
  306. ret = wm5102_patch(arizona);
  307. if (ret != 0) {
  308. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  309. ret);
  310. goto err;
  311. }
  312. ret = arizona_apply_hardware_patch(arizona);
  313. if (ret != 0) {
  314. dev_err(arizona->dev,
  315. "Failed to apply hardware patch: %d\n",
  316. ret);
  317. goto err;
  318. }
  319. break;
  320. default:
  321. ret = arizona_wait_for_boot(arizona);
  322. if (ret != 0) {
  323. goto err;
  324. }
  325. if (arizona->external_dcvdd) {
  326. ret = regmap_update_bits(arizona->regmap,
  327. ARIZONA_ISOLATION_CONTROL,
  328. ARIZONA_ISOLATE_DCVDD1, 0);
  329. if (ret != 0) {
  330. dev_err(arizona->dev,
  331. "Failed to connect DCVDD: %d\n", ret);
  332. goto err;
  333. }
  334. }
  335. break;
  336. }
  337. ret = regcache_sync(arizona->regmap);
  338. if (ret != 0) {
  339. dev_err(arizona->dev, "Failed to restore register cache\n");
  340. goto err;
  341. }
  342. return 0;
  343. err:
  344. regcache_cache_only(arizona->regmap, true);
  345. regulator_disable(arizona->dcvdd);
  346. return ret;
  347. }
  348. static int arizona_runtime_suspend(struct device *dev)
  349. {
  350. struct arizona *arizona = dev_get_drvdata(dev);
  351. int ret;
  352. dev_dbg(arizona->dev, "Entering AoD mode\n");
  353. if (arizona->external_dcvdd) {
  354. ret = regmap_update_bits(arizona->regmap,
  355. ARIZONA_ISOLATION_CONTROL,
  356. ARIZONA_ISOLATE_DCVDD1,
  357. ARIZONA_ISOLATE_DCVDD1);
  358. if (ret != 0) {
  359. dev_err(arizona->dev, "Failed to isolate DCVDD: %d\n",
  360. ret);
  361. return ret;
  362. }
  363. }
  364. regcache_cache_only(arizona->regmap, true);
  365. regcache_mark_dirty(arizona->regmap);
  366. regulator_disable(arizona->dcvdd);
  367. return 0;
  368. }
  369. #endif
  370. #ifdef CONFIG_PM_SLEEP
  371. static int arizona_suspend(struct device *dev)
  372. {
  373. struct arizona *arizona = dev_get_drvdata(dev);
  374. dev_dbg(arizona->dev, "Suspend, disabling IRQ\n");
  375. disable_irq(arizona->irq);
  376. return 0;
  377. }
  378. static int arizona_suspend_late(struct device *dev)
  379. {
  380. struct arizona *arizona = dev_get_drvdata(dev);
  381. dev_dbg(arizona->dev, "Late suspend, reenabling IRQ\n");
  382. enable_irq(arizona->irq);
  383. return 0;
  384. }
  385. static int arizona_resume_noirq(struct device *dev)
  386. {
  387. struct arizona *arizona = dev_get_drvdata(dev);
  388. dev_dbg(arizona->dev, "Early resume, disabling IRQ\n");
  389. disable_irq(arizona->irq);
  390. return 0;
  391. }
  392. static int arizona_resume(struct device *dev)
  393. {
  394. struct arizona *arizona = dev_get_drvdata(dev);
  395. dev_dbg(arizona->dev, "Late resume, reenabling IRQ\n");
  396. enable_irq(arizona->irq);
  397. return 0;
  398. }
  399. #endif
  400. const struct dev_pm_ops arizona_pm_ops = {
  401. SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
  402. arizona_runtime_resume,
  403. NULL)
  404. SET_SYSTEM_SLEEP_PM_OPS(arizona_suspend, arizona_resume)
  405. #ifdef CONFIG_PM_SLEEP
  406. .suspend_late = arizona_suspend_late,
  407. .resume_noirq = arizona_resume_noirq,
  408. #endif
  409. };
  410. EXPORT_SYMBOL_GPL(arizona_pm_ops);
  411. #ifdef CONFIG_OF
  412. unsigned long arizona_of_get_type(struct device *dev)
  413. {
  414. const struct of_device_id *id = of_match_device(arizona_of_match, dev);
  415. if (id)
  416. return (unsigned long)id->data;
  417. else
  418. return 0;
  419. }
  420. EXPORT_SYMBOL_GPL(arizona_of_get_type);
  421. int arizona_of_get_named_gpio(struct arizona *arizona, const char *prop,
  422. bool mandatory)
  423. {
  424. int gpio;
  425. gpio = of_get_named_gpio(arizona->dev->of_node, prop, 0);
  426. if (gpio < 0) {
  427. if (mandatory)
  428. dev_err(arizona->dev,
  429. "Mandatory DT gpio %s missing/malformed: %d\n",
  430. prop, gpio);
  431. gpio = 0;
  432. }
  433. return gpio;
  434. }
  435. EXPORT_SYMBOL_GPL(arizona_of_get_named_gpio);
  436. static int arizona_of_get_core_pdata(struct arizona *arizona)
  437. {
  438. struct arizona_pdata *pdata = &arizona->pdata;
  439. struct property *prop;
  440. const __be32 *cur;
  441. u32 val;
  442. int ret, i;
  443. int count = 0;
  444. pdata->reset = arizona_of_get_named_gpio(arizona, "wlf,reset", true);
  445. ret = of_property_read_u32_array(arizona->dev->of_node,
  446. "wlf,gpio-defaults",
  447. arizona->pdata.gpio_defaults,
  448. ARRAY_SIZE(arizona->pdata.gpio_defaults));
  449. if (ret >= 0) {
  450. /*
  451. * All values are literal except out of range values
  452. * which are chip default, translate into platform
  453. * data which uses 0 as chip default and out of range
  454. * as zero.
  455. */
  456. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  457. if (arizona->pdata.gpio_defaults[i] > 0xffff)
  458. arizona->pdata.gpio_defaults[i] = 0;
  459. else if (arizona->pdata.gpio_defaults[i] == 0)
  460. arizona->pdata.gpio_defaults[i] = 0x10000;
  461. }
  462. } else {
  463. dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n",
  464. ret);
  465. }
  466. of_property_for_each_u32(arizona->dev->of_node, "wlf,inmode", prop,
  467. cur, val) {
  468. if (count == ARRAY_SIZE(arizona->pdata.inmode))
  469. break;
  470. arizona->pdata.inmode[count] = val;
  471. count++;
  472. }
  473. return 0;
  474. }
  475. const struct of_device_id arizona_of_match[] = {
  476. { .compatible = "wlf,wm5102", .data = (void *)WM5102 },
  477. { .compatible = "wlf,wm5110", .data = (void *)WM5110 },
  478. { .compatible = "wlf,wm8997", .data = (void *)WM8997 },
  479. {},
  480. };
  481. EXPORT_SYMBOL_GPL(arizona_of_match);
  482. #else
  483. static inline int arizona_of_get_core_pdata(struct arizona *arizona)
  484. {
  485. return 0;
  486. }
  487. #endif
  488. static const struct mfd_cell early_devs[] = {
  489. { .name = "arizona-ldo1" },
  490. };
  491. static const char *wm5102_supplies[] = {
  492. "MICVDD",
  493. "DBVDD2",
  494. "DBVDD3",
  495. "CPVDD",
  496. "SPKVDDL",
  497. "SPKVDDR",
  498. };
  499. static const struct mfd_cell wm5102_devs[] = {
  500. { .name = "arizona-micsupp" },
  501. {
  502. .name = "arizona-extcon",
  503. .parent_supplies = wm5102_supplies,
  504. .num_parent_supplies = 1, /* We only need MICVDD */
  505. },
  506. { .name = "arizona-gpio" },
  507. { .name = "arizona-haptics" },
  508. { .name = "arizona-pwm" },
  509. {
  510. .name = "wm5102-codec",
  511. .parent_supplies = wm5102_supplies,
  512. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  513. },
  514. };
  515. static const struct mfd_cell wm5110_devs[] = {
  516. { .name = "arizona-micsupp" },
  517. {
  518. .name = "arizona-extcon",
  519. .parent_supplies = wm5102_supplies,
  520. .num_parent_supplies = 1, /* We only need MICVDD */
  521. },
  522. { .name = "arizona-gpio" },
  523. { .name = "arizona-haptics" },
  524. { .name = "arizona-pwm" },
  525. {
  526. .name = "wm5110-codec",
  527. .parent_supplies = wm5102_supplies,
  528. .num_parent_supplies = ARRAY_SIZE(wm5102_supplies),
  529. },
  530. };
  531. static const char *wm8997_supplies[] = {
  532. "MICVDD",
  533. "DBVDD2",
  534. "CPVDD",
  535. "SPKVDD",
  536. };
  537. static const struct mfd_cell wm8997_devs[] = {
  538. { .name = "arizona-micsupp" },
  539. {
  540. .name = "arizona-extcon",
  541. .parent_supplies = wm8997_supplies,
  542. .num_parent_supplies = 1, /* We only need MICVDD */
  543. },
  544. { .name = "arizona-gpio" },
  545. { .name = "arizona-haptics" },
  546. { .name = "arizona-pwm" },
  547. {
  548. .name = "wm8997-codec",
  549. .parent_supplies = wm8997_supplies,
  550. .num_parent_supplies = ARRAY_SIZE(wm8997_supplies),
  551. },
  552. };
  553. int arizona_dev_init(struct arizona *arizona)
  554. {
  555. struct device *dev = arizona->dev;
  556. const char *type_name;
  557. unsigned int reg, val;
  558. int (*apply_patch)(struct arizona *) = NULL;
  559. int ret, i;
  560. dev_set_drvdata(arizona->dev, arizona);
  561. mutex_init(&arizona->clk_lock);
  562. if (dev_get_platdata(arizona->dev))
  563. memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
  564. sizeof(arizona->pdata));
  565. else
  566. arizona_of_get_core_pdata(arizona);
  567. regcache_cache_only(arizona->regmap, true);
  568. switch (arizona->type) {
  569. case WM5102:
  570. case WM5110:
  571. case WM8997:
  572. for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
  573. arizona->core_supplies[i].supply
  574. = wm5102_core_supplies[i];
  575. arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
  576. break;
  577. default:
  578. dev_err(arizona->dev, "Unknown device type %d\n",
  579. arizona->type);
  580. return -EINVAL;
  581. }
  582. /* Mark DCVDD as external, LDO1 driver will clear if internal */
  583. arizona->external_dcvdd = true;
  584. ret = mfd_add_devices(arizona->dev, -1, early_devs,
  585. ARRAY_SIZE(early_devs), NULL, 0, NULL);
  586. if (ret != 0) {
  587. dev_err(dev, "Failed to add early children: %d\n", ret);
  588. return ret;
  589. }
  590. ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
  591. arizona->core_supplies);
  592. if (ret != 0) {
  593. dev_err(dev, "Failed to request core supplies: %d\n",
  594. ret);
  595. goto err_early;
  596. }
  597. /**
  598. * Don't use devres here because the only device we have to get
  599. * against is the MFD device and DCVDD will likely be supplied by
  600. * one of its children. Meaning that the regulator will be
  601. * destroyed by the time devres calls regulator put.
  602. */
  603. arizona->dcvdd = regulator_get(arizona->dev, "DCVDD");
  604. if (IS_ERR(arizona->dcvdd)) {
  605. ret = PTR_ERR(arizona->dcvdd);
  606. dev_err(dev, "Failed to request DCVDD: %d\n", ret);
  607. goto err_early;
  608. }
  609. if (arizona->pdata.reset) {
  610. /* Start out with /RESET low to put the chip into reset */
  611. ret = gpio_request_one(arizona->pdata.reset,
  612. GPIOF_DIR_OUT | GPIOF_INIT_LOW,
  613. "arizona /RESET");
  614. if (ret != 0) {
  615. dev_err(dev, "Failed to request /RESET: %d\n", ret);
  616. goto err_dcvdd;
  617. }
  618. }
  619. ret = regulator_bulk_enable(arizona->num_core_supplies,
  620. arizona->core_supplies);
  621. if (ret != 0) {
  622. dev_err(dev, "Failed to enable core supplies: %d\n",
  623. ret);
  624. goto err_dcvdd;
  625. }
  626. ret = regulator_enable(arizona->dcvdd);
  627. if (ret != 0) {
  628. dev_err(dev, "Failed to enable DCVDD: %d\n", ret);
  629. goto err_enable;
  630. }
  631. if (arizona->pdata.reset) {
  632. gpio_set_value_cansleep(arizona->pdata.reset, 1);
  633. msleep(1);
  634. }
  635. regcache_cache_only(arizona->regmap, false);
  636. /* Verify that this is a chip we know about */
  637. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  638. if (ret != 0) {
  639. dev_err(dev, "Failed to read ID register: %d\n", ret);
  640. goto err_reset;
  641. }
  642. switch (reg) {
  643. case 0x5102:
  644. case 0x5110:
  645. case 0x8997:
  646. break;
  647. default:
  648. dev_err(arizona->dev, "Unknown device ID: %x\n", reg);
  649. goto err_reset;
  650. }
  651. /* If we have a /RESET GPIO we'll already be reset */
  652. if (!arizona->pdata.reset) {
  653. regcache_mark_dirty(arizona->regmap);
  654. ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
  655. if (ret != 0) {
  656. dev_err(dev, "Failed to reset device: %d\n", ret);
  657. goto err_reset;
  658. }
  659. msleep(1);
  660. ret = regcache_sync(arizona->regmap);
  661. if (ret != 0) {
  662. dev_err(dev, "Failed to sync device: %d\n", ret);
  663. goto err_reset;
  664. }
  665. }
  666. /* Ensure device startup is complete */
  667. switch (arizona->type) {
  668. case WM5102:
  669. ret = regmap_read(arizona->regmap,
  670. ARIZONA_WRITE_SEQUENCER_CTRL_3, &val);
  671. if (ret != 0)
  672. dev_err(dev,
  673. "Failed to check write sequencer state: %d\n",
  674. ret);
  675. else if (val & 0x01)
  676. break;
  677. /* Fall through */
  678. default:
  679. ret = arizona_wait_for_boot(arizona);
  680. if (ret != 0) {
  681. dev_err(arizona->dev,
  682. "Device failed initial boot: %d\n", ret);
  683. goto err_reset;
  684. }
  685. break;
  686. }
  687. /* Read the device ID information & do device specific stuff */
  688. ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
  689. if (ret != 0) {
  690. dev_err(dev, "Failed to read ID register: %d\n", ret);
  691. goto err_reset;
  692. }
  693. ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
  694. &arizona->rev);
  695. if (ret != 0) {
  696. dev_err(dev, "Failed to read revision register: %d\n", ret);
  697. goto err_reset;
  698. }
  699. arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
  700. switch (reg) {
  701. #ifdef CONFIG_MFD_WM5102
  702. case 0x5102:
  703. type_name = "WM5102";
  704. if (arizona->type != WM5102) {
  705. dev_err(arizona->dev, "WM5102 registered as %d\n",
  706. arizona->type);
  707. arizona->type = WM5102;
  708. }
  709. apply_patch = wm5102_patch;
  710. arizona->rev &= 0x7;
  711. break;
  712. #endif
  713. #ifdef CONFIG_MFD_WM5110
  714. case 0x5110:
  715. type_name = "WM5110";
  716. if (arizona->type != WM5110) {
  717. dev_err(arizona->dev, "WM5110 registered as %d\n",
  718. arizona->type);
  719. arizona->type = WM5110;
  720. }
  721. apply_patch = wm5110_patch;
  722. break;
  723. #endif
  724. #ifdef CONFIG_MFD_WM8997
  725. case 0x8997:
  726. type_name = "WM8997";
  727. if (arizona->type != WM8997) {
  728. dev_err(arizona->dev, "WM8997 registered as %d\n",
  729. arizona->type);
  730. arizona->type = WM8997;
  731. }
  732. apply_patch = wm8997_patch;
  733. break;
  734. #endif
  735. default:
  736. dev_err(arizona->dev, "Unknown device ID %x\n", reg);
  737. goto err_reset;
  738. }
  739. dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
  740. if (apply_patch) {
  741. ret = apply_patch(arizona);
  742. if (ret != 0) {
  743. dev_err(arizona->dev, "Failed to apply patch: %d\n",
  744. ret);
  745. goto err_reset;
  746. }
  747. switch (arizona->type) {
  748. case WM5102:
  749. ret = arizona_apply_hardware_patch(arizona);
  750. if (ret != 0) {
  751. dev_err(arizona->dev,
  752. "Failed to apply hardware patch: %d\n",
  753. ret);
  754. goto err_reset;
  755. }
  756. break;
  757. default:
  758. break;
  759. }
  760. }
  761. for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
  762. if (!arizona->pdata.gpio_defaults[i])
  763. continue;
  764. regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
  765. arizona->pdata.gpio_defaults[i]);
  766. }
  767. pm_runtime_set_autosuspend_delay(arizona->dev, 100);
  768. pm_runtime_use_autosuspend(arizona->dev);
  769. pm_runtime_enable(arizona->dev);
  770. /* Chip default */
  771. if (!arizona->pdata.clk32k_src)
  772. arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
  773. switch (arizona->pdata.clk32k_src) {
  774. case ARIZONA_32KZ_MCLK1:
  775. case ARIZONA_32KZ_MCLK2:
  776. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  777. ARIZONA_CLK_32K_SRC_MASK,
  778. arizona->pdata.clk32k_src - 1);
  779. arizona_clk32k_enable(arizona);
  780. break;
  781. case ARIZONA_32KZ_NONE:
  782. regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
  783. ARIZONA_CLK_32K_SRC_MASK, 2);
  784. break;
  785. default:
  786. dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
  787. arizona->pdata.clk32k_src);
  788. ret = -EINVAL;
  789. goto err_reset;
  790. }
  791. for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) {
  792. if (!arizona->pdata.micbias[i].mV &&
  793. !arizona->pdata.micbias[i].bypass)
  794. continue;
  795. /* Apply default for bypass mode */
  796. if (!arizona->pdata.micbias[i].mV)
  797. arizona->pdata.micbias[i].mV = 2800;
  798. val = (arizona->pdata.micbias[i].mV - 1500) / 100;
  799. val <<= ARIZONA_MICB1_LVL_SHIFT;
  800. if (arizona->pdata.micbias[i].ext_cap)
  801. val |= ARIZONA_MICB1_EXT_CAP;
  802. if (arizona->pdata.micbias[i].discharge)
  803. val |= ARIZONA_MICB1_DISCH;
  804. if (arizona->pdata.micbias[i].soft_start)
  805. val |= ARIZONA_MICB1_RATE;
  806. if (arizona->pdata.micbias[i].bypass)
  807. val |= ARIZONA_MICB1_BYPASS;
  808. regmap_update_bits(arizona->regmap,
  809. ARIZONA_MIC_BIAS_CTRL_1 + i,
  810. ARIZONA_MICB1_LVL_MASK |
  811. ARIZONA_MICB1_EXT_CAP |
  812. ARIZONA_MICB1_DISCH |
  813. ARIZONA_MICB1_BYPASS |
  814. ARIZONA_MICB1_RATE, val);
  815. }
  816. for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
  817. /* Default for both is 0 so noop with defaults */
  818. val = arizona->pdata.dmic_ref[i]
  819. << ARIZONA_IN1_DMIC_SUP_SHIFT;
  820. val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
  821. regmap_update_bits(arizona->regmap,
  822. ARIZONA_IN1L_CONTROL + (i * 8),
  823. ARIZONA_IN1_DMIC_SUP_MASK |
  824. ARIZONA_IN1_MODE_MASK, val);
  825. }
  826. for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
  827. /* Default is 0 so noop with defaults */
  828. if (arizona->pdata.out_mono[i])
  829. val = ARIZONA_OUT1_MONO;
  830. else
  831. val = 0;
  832. regmap_update_bits(arizona->regmap,
  833. ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
  834. ARIZONA_OUT1_MONO, val);
  835. }
  836. for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
  837. if (arizona->pdata.spk_mute[i])
  838. regmap_update_bits(arizona->regmap,
  839. ARIZONA_PDM_SPK1_CTRL_1 + (i * 2),
  840. ARIZONA_SPK1_MUTE_ENDIAN_MASK |
  841. ARIZONA_SPK1_MUTE_SEQ1_MASK,
  842. arizona->pdata.spk_mute[i]);
  843. if (arizona->pdata.spk_fmt[i])
  844. regmap_update_bits(arizona->regmap,
  845. ARIZONA_PDM_SPK1_CTRL_2 + (i * 2),
  846. ARIZONA_SPK1_FMT_MASK,
  847. arizona->pdata.spk_fmt[i]);
  848. }
  849. /* Set up for interrupts */
  850. ret = arizona_irq_init(arizona);
  851. if (ret != 0)
  852. goto err_reset;
  853. arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
  854. arizona_clkgen_err, arizona);
  855. arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
  856. arizona_overclocked, arizona);
  857. arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
  858. arizona_underclocked, arizona);
  859. switch (arizona->type) {
  860. case WM5102:
  861. ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
  862. ARRAY_SIZE(wm5102_devs), NULL, 0, NULL);
  863. break;
  864. case WM5110:
  865. ret = mfd_add_devices(arizona->dev, -1, wm5110_devs,
  866. ARRAY_SIZE(wm5110_devs), NULL, 0, NULL);
  867. break;
  868. case WM8997:
  869. ret = mfd_add_devices(arizona->dev, -1, wm8997_devs,
  870. ARRAY_SIZE(wm8997_devs), NULL, 0, NULL);
  871. break;
  872. }
  873. if (ret != 0) {
  874. dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
  875. goto err_irq;
  876. }
  877. #ifdef CONFIG_PM
  878. regulator_disable(arizona->dcvdd);
  879. #endif
  880. return 0;
  881. err_irq:
  882. arizona_irq_exit(arizona);
  883. err_reset:
  884. if (arizona->pdata.reset) {
  885. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  886. gpio_free(arizona->pdata.reset);
  887. }
  888. regulator_disable(arizona->dcvdd);
  889. err_enable:
  890. regulator_bulk_disable(arizona->num_core_supplies,
  891. arizona->core_supplies);
  892. err_dcvdd:
  893. regulator_put(arizona->dcvdd);
  894. err_early:
  895. mfd_remove_devices(dev);
  896. return ret;
  897. }
  898. EXPORT_SYMBOL_GPL(arizona_dev_init);
  899. int arizona_dev_exit(struct arizona *arizona)
  900. {
  901. pm_runtime_disable(arizona->dev);
  902. regulator_disable(arizona->dcvdd);
  903. regulator_put(arizona->dcvdd);
  904. mfd_remove_devices(arizona->dev);
  905. arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
  906. arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
  907. arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
  908. arizona_irq_exit(arizona);
  909. if (arizona->pdata.reset)
  910. gpio_set_value_cansleep(arizona->pdata.reset, 0);
  911. regulator_bulk_disable(arizona->num_core_supplies,
  912. arizona->core_supplies);
  913. return 0;
  914. }
  915. EXPORT_SYMBOL_GPL(arizona_dev_exit);