Kconfig 2.8 KB

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  1. #
  2. # Memory devices
  3. #
  4. menuconfig MEMORY
  5. bool "Memory Controller drivers"
  6. if MEMORY
  7. config ATMEL_SDRAMC
  8. bool "Atmel (Multi-port DDR-)SDRAM Controller"
  9. default y
  10. depends on ARCH_AT91 && OF
  11. help
  12. This driver is for Atmel SDRAM Controller or Atmel Multi-port
  13. DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
  14. Starting with the at91sam9g45, this controller supports SDR, DDR and
  15. LP-DDR memories.
  16. config TI_AEMIF
  17. tristate "Texas Instruments AEMIF driver"
  18. depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
  19. help
  20. This driver is for the AEMIF module available in Texas Instruments
  21. SoCs. AEMIF stands for Asynchronous External Memory Interface and
  22. is intended to provide a glue-less interface to a variety of
  23. asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
  24. of 256M bytes of any of these memories can be accessed at a given
  25. time via four chip selects with 64M byte access per chip select.
  26. config TI_EMIF
  27. tristate "Texas Instruments EMIF driver"
  28. depends on ARCH_OMAP2PLUS
  29. select DDR
  30. help
  31. This driver is for the EMIF module available in Texas Instruments
  32. SoCs. EMIF is an SDRAM controller that, based on its revision,
  33. supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
  34. This driver takes care of only LPDDR2 memories presently. The
  35. functions of the driver includes re-configuring AC timing
  36. parameters and other settings during frequency, voltage and
  37. temperature changes
  38. config OMAP_GPMC
  39. bool
  40. help
  41. This driver is for the General Purpose Memory Controller (GPMC)
  42. present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
  43. interfacing to a variety of asynchronous as well as synchronous
  44. memory drives like NOR, NAND, OneNAND, SRAM.
  45. config MVEBU_DEVBUS
  46. bool "Marvell EBU Device Bus Controller"
  47. default y
  48. depends on PLAT_ORION && OF
  49. help
  50. This driver is for the Device Bus controller available in some
  51. Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
  52. Armada 370 and Armada XP. This controller allows to handle flash
  53. devices such as NOR, NAND, SRAM, and FPGA.
  54. config TEGRA20_MC
  55. bool "Tegra20 Memory Controller(MC) driver"
  56. default y
  57. depends on ARCH_TEGRA_2x_SOC
  58. help
  59. This driver is for the Memory Controller(MC) module available
  60. in Tegra20 SoCs, mainly for a address translation fault
  61. analysis, especially for IOMMU/GART(Graphics Address
  62. Relocation Table) module.
  63. config FSL_CORENET_CF
  64. tristate "Freescale CoreNet Error Reporting"
  65. depends on FSL_SOC_BOOKE
  66. help
  67. Say Y for reporting of errors from the Freescale CoreNet
  68. Coherency Fabric. Errors reported include accesses to
  69. physical addresses that mapped by no local access window
  70. (LAW) or an invalid LAW, as well as bad cache state that
  71. represents a coherency violation.
  72. config FSL_IFC
  73. bool
  74. depends on FSL_SOC
  75. source "drivers/memory/tegra/Kconfig"
  76. endif