atmel-isi.c 27 KB

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  1. /*
  2. * Copyright (c) 2011 Atmel Corporation
  3. * Josh Wu, <josh.wu@atmel.com>
  4. *
  5. * Based on previous work by Lars Haring, <lars.haring@atmel.com>
  6. * and Sedji Gaouaou
  7. * Based on the bttv driver for Bt848 with respective copyright holders
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/completion.h>
  15. #include <linux/delay.h>
  16. #include <linux/fs.h>
  17. #include <linux/init.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/slab.h>
  23. #include <media/atmel-isi.h>
  24. #include <media/soc_camera.h>
  25. #include <media/soc_mediabus.h>
  26. #include <media/v4l2-of.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #define MAX_BUFFER_NUM 32
  29. #define MAX_SUPPORT_WIDTH 2048
  30. #define MAX_SUPPORT_HEIGHT 2048
  31. #define VID_LIMIT_BYTES (16 * 1024 * 1024)
  32. #define MIN_FRAME_RATE 15
  33. #define FRAME_INTERVAL_MILLI_SEC (1000 / MIN_FRAME_RATE)
  34. #define ISI_DEFAULT_MCLK_FREQ 25000000
  35. /* Frame buffer descriptor */
  36. struct fbd {
  37. /* Physical address of the frame buffer */
  38. u32 fb_address;
  39. /* DMA Control Register(only in HISI2) */
  40. u32 dma_ctrl;
  41. /* Physical address of the next fbd */
  42. u32 next_fbd_address;
  43. };
  44. static void set_dma_ctrl(struct fbd *fb_desc, u32 ctrl)
  45. {
  46. fb_desc->dma_ctrl = ctrl;
  47. }
  48. struct isi_dma_desc {
  49. struct list_head list;
  50. struct fbd *p_fbd;
  51. dma_addr_t fbd_phys;
  52. };
  53. /* Frame buffer data */
  54. struct frame_buffer {
  55. struct vb2_buffer vb;
  56. struct isi_dma_desc *p_dma_desc;
  57. struct list_head list;
  58. };
  59. struct atmel_isi {
  60. /* Protects the access of variables shared with the ISR */
  61. spinlock_t lock;
  62. void __iomem *regs;
  63. int sequence;
  64. struct vb2_alloc_ctx *alloc_ctx;
  65. /* Allocate descriptors for dma buffer use */
  66. struct fbd *p_fb_descriptors;
  67. dma_addr_t fb_descriptors_phys;
  68. struct list_head dma_desc_head;
  69. struct isi_dma_desc dma_desc[MAX_BUFFER_NUM];
  70. struct completion complete;
  71. /* ISI peripherial clock */
  72. struct clk *pclk;
  73. /* ISI_MCK, feed to camera sensor to generate pixel clock */
  74. struct clk *mck;
  75. unsigned int irq;
  76. struct isi_platform_data pdata;
  77. u16 width_flags; /* max 12 bits */
  78. struct list_head video_buffer_list;
  79. struct frame_buffer *active;
  80. struct soc_camera_host soc_host;
  81. };
  82. static void isi_writel(struct atmel_isi *isi, u32 reg, u32 val)
  83. {
  84. writel(val, isi->regs + reg);
  85. }
  86. static u32 isi_readl(struct atmel_isi *isi, u32 reg)
  87. {
  88. return readl(isi->regs + reg);
  89. }
  90. static int configure_geometry(struct atmel_isi *isi, u32 width,
  91. u32 height, u32 code)
  92. {
  93. u32 cfg2, cr;
  94. switch (code) {
  95. /* YUV, including grey */
  96. case MEDIA_BUS_FMT_Y8_1X8:
  97. cr = ISI_CFG2_GRAYSCALE;
  98. break;
  99. case MEDIA_BUS_FMT_VYUY8_2X8:
  100. cr = ISI_CFG2_YCC_SWAP_MODE_3;
  101. break;
  102. case MEDIA_BUS_FMT_UYVY8_2X8:
  103. cr = ISI_CFG2_YCC_SWAP_MODE_2;
  104. break;
  105. case MEDIA_BUS_FMT_YVYU8_2X8:
  106. cr = ISI_CFG2_YCC_SWAP_MODE_1;
  107. break;
  108. case MEDIA_BUS_FMT_YUYV8_2X8:
  109. cr = ISI_CFG2_YCC_SWAP_DEFAULT;
  110. break;
  111. /* RGB, TODO */
  112. default:
  113. return -EINVAL;
  114. }
  115. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  116. cfg2 = isi_readl(isi, ISI_CFG2);
  117. /* Set YCC swap mode */
  118. cfg2 &= ~ISI_CFG2_YCC_SWAP_MODE_MASK;
  119. cfg2 |= cr;
  120. /* Set width */
  121. cfg2 &= ~(ISI_CFG2_IM_HSIZE_MASK);
  122. cfg2 |= ((width - 1) << ISI_CFG2_IM_HSIZE_OFFSET) &
  123. ISI_CFG2_IM_HSIZE_MASK;
  124. /* Set height */
  125. cfg2 &= ~(ISI_CFG2_IM_VSIZE_MASK);
  126. cfg2 |= ((height - 1) << ISI_CFG2_IM_VSIZE_OFFSET)
  127. & ISI_CFG2_IM_VSIZE_MASK;
  128. isi_writel(isi, ISI_CFG2, cfg2);
  129. return 0;
  130. }
  131. static irqreturn_t atmel_isi_handle_streaming(struct atmel_isi *isi)
  132. {
  133. if (isi->active) {
  134. struct vb2_buffer *vb = &isi->active->vb;
  135. struct frame_buffer *buf = isi->active;
  136. list_del_init(&buf->list);
  137. v4l2_get_timestamp(&vb->v4l2_buf.timestamp);
  138. vb->v4l2_buf.sequence = isi->sequence++;
  139. vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
  140. }
  141. if (list_empty(&isi->video_buffer_list)) {
  142. isi->active = NULL;
  143. } else {
  144. /* start next dma frame. */
  145. isi->active = list_entry(isi->video_buffer_list.next,
  146. struct frame_buffer, list);
  147. isi_writel(isi, ISI_DMA_C_DSCR,
  148. (u32)isi->active->p_dma_desc->fbd_phys);
  149. isi_writel(isi, ISI_DMA_C_CTRL,
  150. ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  151. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  152. }
  153. return IRQ_HANDLED;
  154. }
  155. /* ISI interrupt service routine */
  156. static irqreturn_t isi_interrupt(int irq, void *dev_id)
  157. {
  158. struct atmel_isi *isi = dev_id;
  159. u32 status, mask, pending;
  160. irqreturn_t ret = IRQ_NONE;
  161. spin_lock(&isi->lock);
  162. status = isi_readl(isi, ISI_STATUS);
  163. mask = isi_readl(isi, ISI_INTMASK);
  164. pending = status & mask;
  165. if (pending & ISI_CTRL_SRST) {
  166. complete(&isi->complete);
  167. isi_writel(isi, ISI_INTDIS, ISI_CTRL_SRST);
  168. ret = IRQ_HANDLED;
  169. } else if (pending & ISI_CTRL_DIS) {
  170. complete(&isi->complete);
  171. isi_writel(isi, ISI_INTDIS, ISI_CTRL_DIS);
  172. ret = IRQ_HANDLED;
  173. } else {
  174. if (likely(pending & ISI_SR_CXFR_DONE))
  175. ret = atmel_isi_handle_streaming(isi);
  176. }
  177. spin_unlock(&isi->lock);
  178. return ret;
  179. }
  180. #define WAIT_ISI_RESET 1
  181. #define WAIT_ISI_DISABLE 0
  182. static int atmel_isi_wait_status(struct atmel_isi *isi, int wait_reset)
  183. {
  184. unsigned long timeout;
  185. /*
  186. * The reset or disable will only succeed if we have a
  187. * pixel clock from the camera.
  188. */
  189. init_completion(&isi->complete);
  190. if (wait_reset) {
  191. isi_writel(isi, ISI_INTEN, ISI_CTRL_SRST);
  192. isi_writel(isi, ISI_CTRL, ISI_CTRL_SRST);
  193. } else {
  194. isi_writel(isi, ISI_INTEN, ISI_CTRL_DIS);
  195. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  196. }
  197. timeout = wait_for_completion_timeout(&isi->complete,
  198. msecs_to_jiffies(100));
  199. if (timeout == 0)
  200. return -ETIMEDOUT;
  201. return 0;
  202. }
  203. /* ------------------------------------------------------------------
  204. Videobuf operations
  205. ------------------------------------------------------------------*/
  206. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
  207. unsigned int *nbuffers, unsigned int *nplanes,
  208. unsigned int sizes[], void *alloc_ctxs[])
  209. {
  210. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  211. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  212. struct atmel_isi *isi = ici->priv;
  213. unsigned long size;
  214. size = icd->sizeimage;
  215. if (!*nbuffers || *nbuffers > MAX_BUFFER_NUM)
  216. *nbuffers = MAX_BUFFER_NUM;
  217. if (size * *nbuffers > VID_LIMIT_BYTES)
  218. *nbuffers = VID_LIMIT_BYTES / size;
  219. *nplanes = 1;
  220. sizes[0] = size;
  221. alloc_ctxs[0] = isi->alloc_ctx;
  222. isi->sequence = 0;
  223. isi->active = NULL;
  224. dev_dbg(icd->parent, "%s, count=%d, size=%ld\n", __func__,
  225. *nbuffers, size);
  226. return 0;
  227. }
  228. static int buffer_init(struct vb2_buffer *vb)
  229. {
  230. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  231. buf->p_dma_desc = NULL;
  232. INIT_LIST_HEAD(&buf->list);
  233. return 0;
  234. }
  235. static int buffer_prepare(struct vb2_buffer *vb)
  236. {
  237. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  238. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  239. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  240. struct atmel_isi *isi = ici->priv;
  241. unsigned long size;
  242. struct isi_dma_desc *desc;
  243. size = icd->sizeimage;
  244. if (vb2_plane_size(vb, 0) < size) {
  245. dev_err(icd->parent, "%s data will not fit into plane (%lu < %lu)\n",
  246. __func__, vb2_plane_size(vb, 0), size);
  247. return -EINVAL;
  248. }
  249. vb2_set_plane_payload(&buf->vb, 0, size);
  250. if (!buf->p_dma_desc) {
  251. if (list_empty(&isi->dma_desc_head)) {
  252. dev_err(icd->parent, "Not enough dma descriptors.\n");
  253. return -EINVAL;
  254. } else {
  255. /* Get an available descriptor */
  256. desc = list_entry(isi->dma_desc_head.next,
  257. struct isi_dma_desc, list);
  258. /* Delete the descriptor since now it is used */
  259. list_del_init(&desc->list);
  260. /* Initialize the dma descriptor */
  261. desc->p_fbd->fb_address =
  262. vb2_dma_contig_plane_dma_addr(vb, 0);
  263. desc->p_fbd->next_fbd_address = 0;
  264. set_dma_ctrl(desc->p_fbd, ISI_DMA_CTRL_WB);
  265. buf->p_dma_desc = desc;
  266. }
  267. }
  268. return 0;
  269. }
  270. static void buffer_cleanup(struct vb2_buffer *vb)
  271. {
  272. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  273. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  274. struct atmel_isi *isi = ici->priv;
  275. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  276. /* This descriptor is available now and we add to head list */
  277. if (buf->p_dma_desc)
  278. list_add(&buf->p_dma_desc->list, &isi->dma_desc_head);
  279. }
  280. static void start_dma(struct atmel_isi *isi, struct frame_buffer *buffer)
  281. {
  282. u32 ctrl, cfg1;
  283. cfg1 = isi_readl(isi, ISI_CFG1);
  284. /* Enable irq: cxfr for the codec path, pxfr for the preview path */
  285. isi_writel(isi, ISI_INTEN,
  286. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  287. /* Check if already in a frame */
  288. if (isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) {
  289. dev_err(isi->soc_host.icd->parent, "Already in frame handling.\n");
  290. return;
  291. }
  292. isi_writel(isi, ISI_DMA_C_DSCR, (u32)buffer->p_dma_desc->fbd_phys);
  293. isi_writel(isi, ISI_DMA_C_CTRL, ISI_DMA_CTRL_FETCH | ISI_DMA_CTRL_DONE);
  294. isi_writel(isi, ISI_DMA_CHER, ISI_DMA_CHSR_C_CH);
  295. cfg1 &= ~ISI_CFG1_FRATE_DIV_MASK;
  296. /* Enable linked list */
  297. cfg1 |= isi->pdata.frate | ISI_CFG1_DISCR;
  298. /* Enable codec path and ISI */
  299. ctrl = ISI_CTRL_CDC | ISI_CTRL_EN;
  300. isi_writel(isi, ISI_CTRL, ctrl);
  301. isi_writel(isi, ISI_CFG1, cfg1);
  302. }
  303. static void buffer_queue(struct vb2_buffer *vb)
  304. {
  305. struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
  306. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  307. struct atmel_isi *isi = ici->priv;
  308. struct frame_buffer *buf = container_of(vb, struct frame_buffer, vb);
  309. unsigned long flags = 0;
  310. spin_lock_irqsave(&isi->lock, flags);
  311. list_add_tail(&buf->list, &isi->video_buffer_list);
  312. if (isi->active == NULL) {
  313. isi->active = buf;
  314. if (vb2_is_streaming(vb->vb2_queue))
  315. start_dma(isi, buf);
  316. }
  317. spin_unlock_irqrestore(&isi->lock, flags);
  318. }
  319. static int start_streaming(struct vb2_queue *vq, unsigned int count)
  320. {
  321. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  322. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  323. struct atmel_isi *isi = ici->priv;
  324. int ret;
  325. /* Reset ISI */
  326. ret = atmel_isi_wait_status(isi, WAIT_ISI_RESET);
  327. if (ret < 0) {
  328. dev_err(icd->parent, "Reset ISI timed out\n");
  329. return ret;
  330. }
  331. /* Disable all interrupts */
  332. isi_writel(isi, ISI_INTDIS, (u32)~0UL);
  333. spin_lock_irq(&isi->lock);
  334. /* Clear any pending interrupt */
  335. isi_readl(isi, ISI_STATUS);
  336. if (count)
  337. start_dma(isi, isi->active);
  338. spin_unlock_irq(&isi->lock);
  339. return 0;
  340. }
  341. /* abort streaming and wait for last buffer */
  342. static void stop_streaming(struct vb2_queue *vq)
  343. {
  344. struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
  345. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  346. struct atmel_isi *isi = ici->priv;
  347. struct frame_buffer *buf, *node;
  348. int ret = 0;
  349. unsigned long timeout;
  350. spin_lock_irq(&isi->lock);
  351. isi->active = NULL;
  352. /* Release all active buffers */
  353. list_for_each_entry_safe(buf, node, &isi->video_buffer_list, list) {
  354. list_del_init(&buf->list);
  355. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  356. }
  357. spin_unlock_irq(&isi->lock);
  358. timeout = jiffies + FRAME_INTERVAL_MILLI_SEC * HZ;
  359. /* Wait until the end of the current frame. */
  360. while ((isi_readl(isi, ISI_STATUS) & ISI_CTRL_CDC) &&
  361. time_before(jiffies, timeout))
  362. msleep(1);
  363. if (time_after(jiffies, timeout)) {
  364. dev_err(icd->parent,
  365. "Timeout waiting for finishing codec request\n");
  366. return;
  367. }
  368. /* Disable interrupts */
  369. isi_writel(isi, ISI_INTDIS,
  370. ISI_SR_CXFR_DONE | ISI_SR_PXFR_DONE);
  371. /* Disable ISI and wait for it is done */
  372. ret = atmel_isi_wait_status(isi, WAIT_ISI_DISABLE);
  373. if (ret < 0)
  374. dev_err(icd->parent, "Disable ISI timed out\n");
  375. }
  376. static struct vb2_ops isi_video_qops = {
  377. .queue_setup = queue_setup,
  378. .buf_init = buffer_init,
  379. .buf_prepare = buffer_prepare,
  380. .buf_cleanup = buffer_cleanup,
  381. .buf_queue = buffer_queue,
  382. .start_streaming = start_streaming,
  383. .stop_streaming = stop_streaming,
  384. .wait_prepare = soc_camera_unlock,
  385. .wait_finish = soc_camera_lock,
  386. };
  387. /* ------------------------------------------------------------------
  388. SOC camera operations for the device
  389. ------------------------------------------------------------------*/
  390. static int isi_camera_init_videobuf(struct vb2_queue *q,
  391. struct soc_camera_device *icd)
  392. {
  393. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
  394. q->io_modes = VB2_MMAP;
  395. q->drv_priv = icd;
  396. q->buf_struct_size = sizeof(struct frame_buffer);
  397. q->ops = &isi_video_qops;
  398. q->mem_ops = &vb2_dma_contig_memops;
  399. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  400. return vb2_queue_init(q);
  401. }
  402. static int isi_camera_set_fmt(struct soc_camera_device *icd,
  403. struct v4l2_format *f)
  404. {
  405. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  406. struct atmel_isi *isi = ici->priv;
  407. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  408. const struct soc_camera_format_xlate *xlate;
  409. struct v4l2_pix_format *pix = &f->fmt.pix;
  410. struct v4l2_mbus_framefmt mf;
  411. int ret;
  412. xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
  413. if (!xlate) {
  414. dev_warn(icd->parent, "Format %x not found\n",
  415. pix->pixelformat);
  416. return -EINVAL;
  417. }
  418. dev_dbg(icd->parent, "Plan to set format %dx%d\n",
  419. pix->width, pix->height);
  420. mf.width = pix->width;
  421. mf.height = pix->height;
  422. mf.field = pix->field;
  423. mf.colorspace = pix->colorspace;
  424. mf.code = xlate->code;
  425. ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
  426. if (ret < 0)
  427. return ret;
  428. if (mf.code != xlate->code)
  429. return -EINVAL;
  430. ret = configure_geometry(isi, pix->width, pix->height, xlate->code);
  431. if (ret < 0)
  432. return ret;
  433. pix->width = mf.width;
  434. pix->height = mf.height;
  435. pix->field = mf.field;
  436. pix->colorspace = mf.colorspace;
  437. icd->current_fmt = xlate;
  438. dev_dbg(icd->parent, "Finally set format %dx%d\n",
  439. pix->width, pix->height);
  440. return ret;
  441. }
  442. static int isi_camera_try_fmt(struct soc_camera_device *icd,
  443. struct v4l2_format *f)
  444. {
  445. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  446. const struct soc_camera_format_xlate *xlate;
  447. struct v4l2_pix_format *pix = &f->fmt.pix;
  448. struct v4l2_mbus_framefmt mf;
  449. u32 pixfmt = pix->pixelformat;
  450. int ret;
  451. xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
  452. if (pixfmt && !xlate) {
  453. dev_warn(icd->parent, "Format %x not found\n", pixfmt);
  454. return -EINVAL;
  455. }
  456. /* limit to Atmel ISI hardware capabilities */
  457. if (pix->height > MAX_SUPPORT_HEIGHT)
  458. pix->height = MAX_SUPPORT_HEIGHT;
  459. if (pix->width > MAX_SUPPORT_WIDTH)
  460. pix->width = MAX_SUPPORT_WIDTH;
  461. /* limit to sensor capabilities */
  462. mf.width = pix->width;
  463. mf.height = pix->height;
  464. mf.field = pix->field;
  465. mf.colorspace = pix->colorspace;
  466. mf.code = xlate->code;
  467. ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
  468. if (ret < 0)
  469. return ret;
  470. pix->width = mf.width;
  471. pix->height = mf.height;
  472. pix->colorspace = mf.colorspace;
  473. switch (mf.field) {
  474. case V4L2_FIELD_ANY:
  475. pix->field = V4L2_FIELD_NONE;
  476. break;
  477. case V4L2_FIELD_NONE:
  478. break;
  479. default:
  480. dev_err(icd->parent, "Field type %d unsupported.\n",
  481. mf.field);
  482. ret = -EINVAL;
  483. }
  484. return ret;
  485. }
  486. static const struct soc_mbus_pixelfmt isi_camera_formats[] = {
  487. {
  488. .fourcc = V4L2_PIX_FMT_YUYV,
  489. .name = "Packed YUV422 16 bit",
  490. .bits_per_sample = 8,
  491. .packing = SOC_MBUS_PACKING_2X8_PADHI,
  492. .order = SOC_MBUS_ORDER_LE,
  493. .layout = SOC_MBUS_LAYOUT_PACKED,
  494. },
  495. };
  496. /* This will be corrected as we get more formats */
  497. static bool isi_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
  498. {
  499. return fmt->packing == SOC_MBUS_PACKING_NONE ||
  500. (fmt->bits_per_sample == 8 &&
  501. fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
  502. (fmt->bits_per_sample > 8 &&
  503. fmt->packing == SOC_MBUS_PACKING_EXTEND16);
  504. }
  505. #define ISI_BUS_PARAM (V4L2_MBUS_MASTER | \
  506. V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
  507. V4L2_MBUS_HSYNC_ACTIVE_LOW | \
  508. V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
  509. V4L2_MBUS_VSYNC_ACTIVE_LOW | \
  510. V4L2_MBUS_PCLK_SAMPLE_RISING | \
  511. V4L2_MBUS_PCLK_SAMPLE_FALLING | \
  512. V4L2_MBUS_DATA_ACTIVE_HIGH)
  513. static int isi_camera_try_bus_param(struct soc_camera_device *icd,
  514. unsigned char buswidth)
  515. {
  516. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  517. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  518. struct atmel_isi *isi = ici->priv;
  519. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  520. unsigned long common_flags;
  521. int ret;
  522. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  523. if (!ret) {
  524. common_flags = soc_mbus_config_compatible(&cfg,
  525. ISI_BUS_PARAM);
  526. if (!common_flags) {
  527. dev_warn(icd->parent,
  528. "Flags incompatible: camera 0x%x, host 0x%x\n",
  529. cfg.flags, ISI_BUS_PARAM);
  530. return -EINVAL;
  531. }
  532. } else if (ret != -ENOIOCTLCMD) {
  533. return ret;
  534. }
  535. if ((1 << (buswidth - 1)) & isi->width_flags)
  536. return 0;
  537. return -EINVAL;
  538. }
  539. static int isi_camera_get_formats(struct soc_camera_device *icd,
  540. unsigned int idx,
  541. struct soc_camera_format_xlate *xlate)
  542. {
  543. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  544. int formats = 0, ret;
  545. /* sensor format */
  546. u32 code;
  547. /* soc camera host format */
  548. const struct soc_mbus_pixelfmt *fmt;
  549. ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
  550. if (ret < 0)
  551. /* No more formats */
  552. return 0;
  553. fmt = soc_mbus_get_fmtdesc(code);
  554. if (!fmt) {
  555. dev_err(icd->parent,
  556. "Invalid format code #%u: %d\n", idx, code);
  557. return 0;
  558. }
  559. /* This also checks support for the requested bits-per-sample */
  560. ret = isi_camera_try_bus_param(icd, fmt->bits_per_sample);
  561. if (ret < 0) {
  562. dev_err(icd->parent,
  563. "Fail to try the bus parameters.\n");
  564. return 0;
  565. }
  566. switch (code) {
  567. case MEDIA_BUS_FMT_UYVY8_2X8:
  568. case MEDIA_BUS_FMT_VYUY8_2X8:
  569. case MEDIA_BUS_FMT_YUYV8_2X8:
  570. case MEDIA_BUS_FMT_YVYU8_2X8:
  571. formats++;
  572. if (xlate) {
  573. xlate->host_fmt = &isi_camera_formats[0];
  574. xlate->code = code;
  575. xlate++;
  576. dev_dbg(icd->parent, "Providing format %s using code %d\n",
  577. isi_camera_formats[0].name, code);
  578. }
  579. break;
  580. default:
  581. if (!isi_camera_packing_supported(fmt))
  582. return 0;
  583. if (xlate)
  584. dev_dbg(icd->parent,
  585. "Providing format %s in pass-through mode\n",
  586. fmt->name);
  587. }
  588. /* Generic pass-through */
  589. formats++;
  590. if (xlate) {
  591. xlate->host_fmt = fmt;
  592. xlate->code = code;
  593. xlate++;
  594. }
  595. return formats;
  596. }
  597. static int isi_camera_add_device(struct soc_camera_device *icd)
  598. {
  599. dev_dbg(icd->parent, "Atmel ISI Camera driver attached to camera %d\n",
  600. icd->devnum);
  601. return 0;
  602. }
  603. static void isi_camera_remove_device(struct soc_camera_device *icd)
  604. {
  605. dev_dbg(icd->parent, "Atmel ISI Camera driver detached from camera %d\n",
  606. icd->devnum);
  607. }
  608. /* Called with .host_lock held */
  609. static int isi_camera_clock_start(struct soc_camera_host *ici)
  610. {
  611. struct atmel_isi *isi = ici->priv;
  612. int ret;
  613. ret = clk_prepare_enable(isi->pclk);
  614. if (ret)
  615. return ret;
  616. if (!IS_ERR(isi->mck)) {
  617. ret = clk_prepare_enable(isi->mck);
  618. if (ret) {
  619. clk_disable_unprepare(isi->pclk);
  620. return ret;
  621. }
  622. }
  623. return 0;
  624. }
  625. /* Called with .host_lock held */
  626. static void isi_camera_clock_stop(struct soc_camera_host *ici)
  627. {
  628. struct atmel_isi *isi = ici->priv;
  629. if (!IS_ERR(isi->mck))
  630. clk_disable_unprepare(isi->mck);
  631. clk_disable_unprepare(isi->pclk);
  632. }
  633. static unsigned int isi_camera_poll(struct file *file, poll_table *pt)
  634. {
  635. struct soc_camera_device *icd = file->private_data;
  636. return vb2_poll(&icd->vb2_vidq, file, pt);
  637. }
  638. static int isi_camera_querycap(struct soc_camera_host *ici,
  639. struct v4l2_capability *cap)
  640. {
  641. strcpy(cap->driver, "atmel-isi");
  642. strcpy(cap->card, "Atmel Image Sensor Interface");
  643. cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
  644. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  645. return 0;
  646. }
  647. static int isi_camera_set_bus_param(struct soc_camera_device *icd)
  648. {
  649. struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
  650. struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
  651. struct atmel_isi *isi = ici->priv;
  652. struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
  653. unsigned long common_flags;
  654. int ret;
  655. u32 cfg1 = 0;
  656. ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
  657. if (!ret) {
  658. common_flags = soc_mbus_config_compatible(&cfg,
  659. ISI_BUS_PARAM);
  660. if (!common_flags) {
  661. dev_warn(icd->parent,
  662. "Flags incompatible: camera 0x%x, host 0x%x\n",
  663. cfg.flags, ISI_BUS_PARAM);
  664. return -EINVAL;
  665. }
  666. } else if (ret != -ENOIOCTLCMD) {
  667. return ret;
  668. } else {
  669. common_flags = ISI_BUS_PARAM;
  670. }
  671. dev_dbg(icd->parent, "Flags cam: 0x%x host: 0x%x common: 0x%lx\n",
  672. cfg.flags, ISI_BUS_PARAM, common_flags);
  673. /* Make choises, based on platform preferences */
  674. if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
  675. (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
  676. if (isi->pdata.hsync_act_low)
  677. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
  678. else
  679. common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
  680. }
  681. if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
  682. (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
  683. if (isi->pdata.vsync_act_low)
  684. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
  685. else
  686. common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
  687. }
  688. if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
  689. (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
  690. if (isi->pdata.pclk_act_falling)
  691. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
  692. else
  693. common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
  694. }
  695. cfg.flags = common_flags;
  696. ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
  697. if (ret < 0 && ret != -ENOIOCTLCMD) {
  698. dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
  699. common_flags, ret);
  700. return ret;
  701. }
  702. /* set bus param for ISI */
  703. if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
  704. cfg1 |= ISI_CFG1_HSYNC_POL_ACTIVE_LOW;
  705. if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
  706. cfg1 |= ISI_CFG1_VSYNC_POL_ACTIVE_LOW;
  707. if (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
  708. cfg1 |= ISI_CFG1_PIXCLK_POL_ACTIVE_FALLING;
  709. if (isi->pdata.has_emb_sync)
  710. cfg1 |= ISI_CFG1_EMB_SYNC;
  711. if (isi->pdata.full_mode)
  712. cfg1 |= ISI_CFG1_FULL_MODE;
  713. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  714. isi_writel(isi, ISI_CFG1, cfg1);
  715. return 0;
  716. }
  717. static struct soc_camera_host_ops isi_soc_camera_host_ops = {
  718. .owner = THIS_MODULE,
  719. .add = isi_camera_add_device,
  720. .remove = isi_camera_remove_device,
  721. .clock_start = isi_camera_clock_start,
  722. .clock_stop = isi_camera_clock_stop,
  723. .set_fmt = isi_camera_set_fmt,
  724. .try_fmt = isi_camera_try_fmt,
  725. .get_formats = isi_camera_get_formats,
  726. .init_videobuf2 = isi_camera_init_videobuf,
  727. .poll = isi_camera_poll,
  728. .querycap = isi_camera_querycap,
  729. .set_bus_param = isi_camera_set_bus_param,
  730. };
  731. /* -----------------------------------------------------------------------*/
  732. static int atmel_isi_remove(struct platform_device *pdev)
  733. {
  734. struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
  735. struct atmel_isi *isi = container_of(soc_host,
  736. struct atmel_isi, soc_host);
  737. soc_camera_host_unregister(soc_host);
  738. vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
  739. dma_free_coherent(&pdev->dev,
  740. sizeof(struct fbd) * MAX_BUFFER_NUM,
  741. isi->p_fb_descriptors,
  742. isi->fb_descriptors_phys);
  743. return 0;
  744. }
  745. static int atmel_isi_probe_dt(struct atmel_isi *isi,
  746. struct platform_device *pdev)
  747. {
  748. struct device_node *np= pdev->dev.of_node;
  749. struct v4l2_of_endpoint ep;
  750. int err;
  751. /* Default settings for ISI */
  752. isi->pdata.full_mode = 1;
  753. isi->pdata.mck_hz = ISI_DEFAULT_MCLK_FREQ;
  754. isi->pdata.frate = ISI_CFG1_FRATE_CAPTURE_ALL;
  755. np = of_graph_get_next_endpoint(np, NULL);
  756. if (!np) {
  757. dev_err(&pdev->dev, "Could not find the endpoint\n");
  758. return -EINVAL;
  759. }
  760. err = v4l2_of_parse_endpoint(np, &ep);
  761. if (err) {
  762. dev_err(&pdev->dev, "Could not parse the endpoint\n");
  763. goto err_probe_dt;
  764. }
  765. switch (ep.bus.parallel.bus_width) {
  766. case 8:
  767. isi->pdata.data_width_flags = ISI_DATAWIDTH_8;
  768. break;
  769. case 10:
  770. isi->pdata.data_width_flags =
  771. ISI_DATAWIDTH_8 | ISI_DATAWIDTH_10;
  772. break;
  773. default:
  774. dev_err(&pdev->dev, "Unsupported bus width: %d\n",
  775. ep.bus.parallel.bus_width);
  776. err = -EINVAL;
  777. goto err_probe_dt;
  778. }
  779. err_probe_dt:
  780. of_node_put(np);
  781. return err;
  782. }
  783. static int atmel_isi_probe(struct platform_device *pdev)
  784. {
  785. unsigned int irq;
  786. struct atmel_isi *isi;
  787. struct resource *regs;
  788. int ret, i;
  789. struct device *dev = &pdev->dev;
  790. struct soc_camera_host *soc_host;
  791. struct isi_platform_data *pdata;
  792. pdata = dev->platform_data;
  793. if ((!pdata || !pdata->data_width_flags) && !pdev->dev.of_node) {
  794. dev_err(&pdev->dev,
  795. "No config available for Atmel ISI\n");
  796. return -EINVAL;
  797. }
  798. isi = devm_kzalloc(&pdev->dev, sizeof(struct atmel_isi), GFP_KERNEL);
  799. if (!isi) {
  800. dev_err(&pdev->dev, "Can't allocate interface!\n");
  801. return -ENOMEM;
  802. }
  803. isi->pclk = devm_clk_get(&pdev->dev, "isi_clk");
  804. if (IS_ERR(isi->pclk))
  805. return PTR_ERR(isi->pclk);
  806. if (pdata) {
  807. memcpy(&isi->pdata, pdata, sizeof(isi->pdata));
  808. } else {
  809. ret = atmel_isi_probe_dt(isi, pdev);
  810. if (ret)
  811. return ret;
  812. }
  813. isi->active = NULL;
  814. spin_lock_init(&isi->lock);
  815. INIT_LIST_HEAD(&isi->video_buffer_list);
  816. INIT_LIST_HEAD(&isi->dma_desc_head);
  817. /* ISI_MCK is the sensor master clock. It should be handled by the
  818. * sensor driver directly, as the ISI has no use for that clock. Make
  819. * the clock optional here while platforms transition to the correct
  820. * model.
  821. */
  822. isi->mck = devm_clk_get(dev, "isi_mck");
  823. if (!IS_ERR(isi->mck)) {
  824. /* Set ISI_MCK's frequency, it should be faster than pixel
  825. * clock.
  826. */
  827. ret = clk_set_rate(isi->mck, isi->pdata.mck_hz);
  828. if (ret < 0)
  829. return ret;
  830. }
  831. isi->p_fb_descriptors = dma_alloc_coherent(&pdev->dev,
  832. sizeof(struct fbd) * MAX_BUFFER_NUM,
  833. &isi->fb_descriptors_phys,
  834. GFP_KERNEL);
  835. if (!isi->p_fb_descriptors) {
  836. dev_err(&pdev->dev, "Can't allocate descriptors!\n");
  837. return -ENOMEM;
  838. }
  839. for (i = 0; i < MAX_BUFFER_NUM; i++) {
  840. isi->dma_desc[i].p_fbd = isi->p_fb_descriptors + i;
  841. isi->dma_desc[i].fbd_phys = isi->fb_descriptors_phys +
  842. i * sizeof(struct fbd);
  843. list_add(&isi->dma_desc[i].list, &isi->dma_desc_head);
  844. }
  845. isi->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  846. if (IS_ERR(isi->alloc_ctx)) {
  847. ret = PTR_ERR(isi->alloc_ctx);
  848. goto err_alloc_ctx;
  849. }
  850. regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  851. isi->regs = devm_ioremap_resource(&pdev->dev, regs);
  852. if (IS_ERR(isi->regs)) {
  853. ret = PTR_ERR(isi->regs);
  854. goto err_ioremap;
  855. }
  856. if (isi->pdata.data_width_flags & ISI_DATAWIDTH_8)
  857. isi->width_flags = 1 << 7;
  858. if (isi->pdata.data_width_flags & ISI_DATAWIDTH_10)
  859. isi->width_flags |= 1 << 9;
  860. isi_writel(isi, ISI_CTRL, ISI_CTRL_DIS);
  861. irq = platform_get_irq(pdev, 0);
  862. if (IS_ERR_VALUE(irq)) {
  863. ret = irq;
  864. goto err_req_irq;
  865. }
  866. ret = devm_request_irq(&pdev->dev, irq, isi_interrupt, 0, "isi", isi);
  867. if (ret) {
  868. dev_err(&pdev->dev, "Unable to request irq %d\n", irq);
  869. goto err_req_irq;
  870. }
  871. isi->irq = irq;
  872. soc_host = &isi->soc_host;
  873. soc_host->drv_name = "isi-camera";
  874. soc_host->ops = &isi_soc_camera_host_ops;
  875. soc_host->priv = isi;
  876. soc_host->v4l2_dev.dev = &pdev->dev;
  877. soc_host->nr = pdev->id;
  878. if (isi->pdata.asd_sizes) {
  879. soc_host->asd = isi->pdata.asd;
  880. soc_host->asd_sizes = isi->pdata.asd_sizes;
  881. }
  882. ret = soc_camera_host_register(soc_host);
  883. if (ret) {
  884. dev_err(&pdev->dev, "Unable to register soc camera host\n");
  885. goto err_register_soc_camera_host;
  886. }
  887. return 0;
  888. err_register_soc_camera_host:
  889. err_req_irq:
  890. err_ioremap:
  891. vb2_dma_contig_cleanup_ctx(isi->alloc_ctx);
  892. err_alloc_ctx:
  893. dma_free_coherent(&pdev->dev,
  894. sizeof(struct fbd) * MAX_BUFFER_NUM,
  895. isi->p_fb_descriptors,
  896. isi->fb_descriptors_phys);
  897. return ret;
  898. }
  899. static const struct of_device_id atmel_isi_of_match[] = {
  900. { .compatible = "atmel,at91sam9g45-isi" },
  901. { }
  902. };
  903. MODULE_DEVICE_TABLE(of, atmel_isi_of_match);
  904. static struct platform_driver atmel_isi_driver = {
  905. .remove = atmel_isi_remove,
  906. .driver = {
  907. .name = "atmel_isi",
  908. .of_match_table = of_match_ptr(atmel_isi_of_match),
  909. },
  910. };
  911. module_platform_driver_probe(atmel_isi_driver, atmel_isi_probe);
  912. MODULE_AUTHOR("Josh Wu <josh.wu@atmel.com>");
  913. MODULE_DESCRIPTION("The V4L2 driver for Atmel Linux");
  914. MODULE_LICENSE("GPL");
  915. MODULE_SUPPORTED_DEVICE("video");