coda-bit.c 54 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/reset.h>
  19. #include <linux/slab.h>
  20. #include <linux/videodev2.h>
  21. #include <media/v4l2-common.h>
  22. #include <media/v4l2-ctrls.h>
  23. #include <media/v4l2-fh.h>
  24. #include <media/v4l2-mem2mem.h>
  25. #include <media/videobuf2-core.h>
  26. #include <media/videobuf2-dma-contig.h>
  27. #include <media/videobuf2-vmalloc.h>
  28. #include "coda.h"
  29. #define CODA7_PS_BUF_SIZE 0x28000
  30. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  31. #define CODA_DEFAULT_GAMMA 4096
  32. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  33. static inline int coda_is_initialized(struct coda_dev *dev)
  34. {
  35. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  36. }
  37. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  38. {
  39. return coda_read(dev, CODA_REG_BIT_BUSY);
  40. }
  41. static int coda_wait_timeout(struct coda_dev *dev)
  42. {
  43. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  44. while (coda_isbusy(dev)) {
  45. if (time_after(jiffies, timeout))
  46. return -ETIMEDOUT;
  47. }
  48. return 0;
  49. }
  50. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  51. {
  52. struct coda_dev *dev = ctx->dev;
  53. if (dev->devtype->product == CODA_960 ||
  54. dev->devtype->product == CODA_7541) {
  55. /* Restore context related registers to CODA */
  56. coda_write(dev, ctx->bit_stream_param,
  57. CODA_REG_BIT_BIT_STREAM_PARAM);
  58. coda_write(dev, ctx->frm_dis_flg,
  59. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  60. coda_write(dev, ctx->frame_mem_ctrl,
  61. CODA_REG_BIT_FRAME_MEM_CTRL);
  62. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  63. }
  64. if (dev->devtype->product == CODA_960) {
  65. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  66. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  67. }
  68. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  69. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  70. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  71. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  72. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  73. }
  74. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  75. {
  76. struct coda_dev *dev = ctx->dev;
  77. coda_command_async(ctx, cmd);
  78. return coda_wait_timeout(dev);
  79. }
  80. int coda_hw_reset(struct coda_ctx *ctx)
  81. {
  82. struct coda_dev *dev = ctx->dev;
  83. unsigned long timeout;
  84. unsigned int idx;
  85. int ret;
  86. if (!dev->rstc)
  87. return -ENOENT;
  88. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  89. if (dev->devtype->product == CODA_960) {
  90. timeout = jiffies + msecs_to_jiffies(100);
  91. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  92. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  93. if (time_after(jiffies, timeout))
  94. return -ETIME;
  95. cpu_relax();
  96. }
  97. }
  98. ret = reset_control_reset(dev->rstc);
  99. if (ret < 0)
  100. return ret;
  101. if (dev->devtype->product == CODA_960)
  102. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  103. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  104. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  105. ret = coda_wait_timeout(dev);
  106. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  107. return ret;
  108. }
  109. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  110. {
  111. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  112. struct coda_dev *dev = ctx->dev;
  113. u32 rd_ptr;
  114. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  115. kfifo->out = (kfifo->in & ~kfifo->mask) |
  116. (rd_ptr - ctx->bitstream.paddr);
  117. if (kfifo->out > kfifo->in)
  118. kfifo->out -= kfifo->mask + 1;
  119. }
  120. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  121. {
  122. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  123. struct coda_dev *dev = ctx->dev;
  124. u32 rd_ptr, wr_ptr;
  125. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  126. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  127. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  128. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  129. }
  130. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  131. {
  132. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  133. struct coda_dev *dev = ctx->dev;
  134. u32 wr_ptr;
  135. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  136. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  137. }
  138. static int coda_bitstream_queue(struct coda_ctx *ctx,
  139. struct vb2_buffer *src_buf)
  140. {
  141. u32 src_size = vb2_get_plane_payload(src_buf, 0);
  142. u32 n;
  143. n = kfifo_in(&ctx->bitstream_fifo, vb2_plane_vaddr(src_buf, 0),
  144. src_size);
  145. if (n < src_size)
  146. return -ENOSPC;
  147. dma_sync_single_for_device(&ctx->dev->plat_dev->dev,
  148. ctx->bitstream.paddr, ctx->bitstream.size,
  149. DMA_TO_DEVICE);
  150. src_buf->v4l2_buf.sequence = ctx->qsequence++;
  151. return 0;
  152. }
  153. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  154. struct vb2_buffer *src_buf)
  155. {
  156. int ret;
  157. if (coda_get_bitstream_payload(ctx) +
  158. vb2_get_plane_payload(src_buf, 0) + 512 >= ctx->bitstream.size)
  159. return false;
  160. if (vb2_plane_vaddr(src_buf, 0) == NULL) {
  161. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  162. return true;
  163. }
  164. ret = coda_bitstream_queue(ctx, src_buf);
  165. if (ret < 0) {
  166. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  167. return false;
  168. }
  169. /* Sync read pointer to device */
  170. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  171. coda_kfifo_sync_to_device_write(ctx);
  172. ctx->hold = false;
  173. return true;
  174. }
  175. void coda_fill_bitstream(struct coda_ctx *ctx)
  176. {
  177. struct vb2_buffer *src_buf;
  178. struct coda_buffer_meta *meta;
  179. u32 start;
  180. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  181. /*
  182. * Only queue a single JPEG into the bitstream buffer, except
  183. * to increase payload over 512 bytes or if in hold state.
  184. */
  185. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  186. (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
  187. break;
  188. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  189. /* Drop frames that do not start/end with a SOI/EOI markers */
  190. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  191. !coda_jpeg_check_buffer(ctx, src_buf)) {
  192. v4l2_err(&ctx->dev->v4l2_dev,
  193. "dropping invalid JPEG frame\n");
  194. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  195. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR);
  196. continue;
  197. }
  198. /* Buffer start position */
  199. start = ctx->bitstream_fifo.kfifo.in &
  200. ctx->bitstream_fifo.kfifo.mask;
  201. if (coda_bitstream_try_queue(ctx, src_buf)) {
  202. /*
  203. * Source buffer is queued in the bitstream ringbuffer;
  204. * queue the timestamp and mark source buffer as done
  205. */
  206. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  207. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  208. if (meta) {
  209. meta->sequence = src_buf->v4l2_buf.sequence;
  210. meta->timecode = src_buf->v4l2_buf.timecode;
  211. meta->timestamp = src_buf->v4l2_buf.timestamp;
  212. meta->start = start;
  213. meta->end = ctx->bitstream_fifo.kfifo.in &
  214. ctx->bitstream_fifo.kfifo.mask;
  215. list_add_tail(&meta->list,
  216. &ctx->buffer_meta_list);
  217. }
  218. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  219. } else {
  220. break;
  221. }
  222. }
  223. }
  224. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  225. {
  226. struct coda_dev *dev = ctx->dev;
  227. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  228. /* If this context is currently running, update the hardware flag */
  229. if ((dev->devtype->product == CODA_960) &&
  230. coda_isbusy(dev) &&
  231. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  232. coda_write(dev, ctx->bit_stream_param,
  233. CODA_REG_BIT_BIT_STREAM_PARAM);
  234. }
  235. }
  236. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  237. {
  238. struct coda_dev *dev = ctx->dev;
  239. u32 *p = ctx->parabuf.vaddr;
  240. if (dev->devtype->product == CODA_DX6)
  241. p[index] = value;
  242. else
  243. p[index ^ 1] = value;
  244. }
  245. static void coda_free_framebuffers(struct coda_ctx *ctx)
  246. {
  247. int i;
  248. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  249. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  250. }
  251. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  252. struct coda_q_data *q_data, u32 fourcc)
  253. {
  254. struct coda_dev *dev = ctx->dev;
  255. int width, height;
  256. dma_addr_t paddr;
  257. int ysize;
  258. int ret;
  259. int i;
  260. if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  261. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
  262. width = round_up(q_data->width, 16);
  263. height = round_up(q_data->height, 16);
  264. } else {
  265. width = round_up(q_data->width, 8);
  266. height = q_data->height;
  267. }
  268. ysize = width * height;
  269. /* Allocate frame buffers */
  270. for (i = 0; i < ctx->num_internal_frames; i++) {
  271. size_t size;
  272. char *name;
  273. size = ysize + ysize / 2;
  274. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  275. dev->devtype->product != CODA_DX6)
  276. size += ysize / 4;
  277. name = kasprintf(GFP_KERNEL, "fb%d", i);
  278. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  279. size, name);
  280. kfree(name);
  281. if (ret < 0) {
  282. coda_free_framebuffers(ctx);
  283. return ret;
  284. }
  285. }
  286. /* Register frame buffers in the parameter buffer */
  287. for (i = 0; i < ctx->num_internal_frames; i++) {
  288. paddr = ctx->internal_frames[i].paddr;
  289. /* Start addresses of Y, Cb, Cr planes */
  290. coda_parabuf_write(ctx, i * 3 + 0, paddr);
  291. coda_parabuf_write(ctx, i * 3 + 1, paddr + ysize);
  292. coda_parabuf_write(ctx, i * 3 + 2, paddr + ysize + ysize / 4);
  293. /* mvcol buffer for h.264 */
  294. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  295. dev->devtype->product != CODA_DX6)
  296. coda_parabuf_write(ctx, 96 + i,
  297. ctx->internal_frames[i].paddr +
  298. ysize + ysize/4 + ysize/4);
  299. }
  300. /* mvcol buffer for mpeg4 */
  301. if ((dev->devtype->product != CODA_DX6) &&
  302. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  303. coda_parabuf_write(ctx, 97, ctx->internal_frames[i].paddr +
  304. ysize + ysize/4 + ysize/4);
  305. return 0;
  306. }
  307. static void coda_free_context_buffers(struct coda_ctx *ctx)
  308. {
  309. struct coda_dev *dev = ctx->dev;
  310. coda_free_aux_buf(dev, &ctx->slicebuf);
  311. coda_free_aux_buf(dev, &ctx->psbuf);
  312. if (dev->devtype->product != CODA_DX6)
  313. coda_free_aux_buf(dev, &ctx->workbuf);
  314. }
  315. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  316. struct coda_q_data *q_data)
  317. {
  318. struct coda_dev *dev = ctx->dev;
  319. size_t size;
  320. int ret;
  321. if (dev->devtype->product == CODA_DX6)
  322. return 0;
  323. if (ctx->psbuf.vaddr) {
  324. v4l2_err(&dev->v4l2_dev, "psmembuf still allocated\n");
  325. return -EBUSY;
  326. }
  327. if (ctx->slicebuf.vaddr) {
  328. v4l2_err(&dev->v4l2_dev, "slicebuf still allocated\n");
  329. return -EBUSY;
  330. }
  331. if (ctx->workbuf.vaddr) {
  332. v4l2_err(&dev->v4l2_dev, "context buffer still allocated\n");
  333. ret = -EBUSY;
  334. return -ENOMEM;
  335. }
  336. if (q_data->fourcc == V4L2_PIX_FMT_H264) {
  337. /* worst case slice size */
  338. size = (DIV_ROUND_UP(q_data->width, 16) *
  339. DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
  340. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  341. "slicebuf");
  342. if (ret < 0) {
  343. v4l2_err(&dev->v4l2_dev,
  344. "failed to allocate %d byte slice buffer",
  345. ctx->slicebuf.size);
  346. return ret;
  347. }
  348. }
  349. if (dev->devtype->product == CODA_7541) {
  350. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  351. CODA7_PS_BUF_SIZE, "psbuf");
  352. if (ret < 0) {
  353. v4l2_err(&dev->v4l2_dev,
  354. "failed to allocate psmem buffer");
  355. goto err;
  356. }
  357. }
  358. size = dev->devtype->workbuf_size;
  359. if (dev->devtype->product == CODA_960 &&
  360. q_data->fourcc == V4L2_PIX_FMT_H264)
  361. size += CODA9_PS_SAVE_SIZE;
  362. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size, "workbuf");
  363. if (ret < 0) {
  364. v4l2_err(&dev->v4l2_dev,
  365. "failed to allocate %d byte context buffer",
  366. ctx->workbuf.size);
  367. goto err;
  368. }
  369. return 0;
  370. err:
  371. coda_free_context_buffers(ctx);
  372. return ret;
  373. }
  374. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
  375. int header_code, u8 *header, int *size)
  376. {
  377. struct coda_dev *dev = ctx->dev;
  378. size_t bufsize;
  379. int ret;
  380. int i;
  381. if (dev->devtype->product == CODA_960)
  382. memset(vb2_plane_vaddr(buf, 0), 0, 64);
  383. coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0),
  384. CODA_CMD_ENC_HEADER_BB_START);
  385. bufsize = vb2_plane_size(buf, 0);
  386. if (dev->devtype->product == CODA_960)
  387. bufsize /= 1024;
  388. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  389. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  390. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  391. if (ret < 0) {
  392. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  393. return ret;
  394. }
  395. if (dev->devtype->product == CODA_960) {
  396. for (i = 63; i > 0; i--)
  397. if (((char *)vb2_plane_vaddr(buf, 0))[i] != 0)
  398. break;
  399. *size = i + 1;
  400. } else {
  401. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  402. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  403. }
  404. memcpy(header, vb2_plane_vaddr(buf, 0), *size);
  405. return 0;
  406. }
  407. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  408. {
  409. phys_addr_t ret;
  410. size = round_up(size, 1024);
  411. if (size > iram->remaining)
  412. return 0;
  413. iram->remaining -= size;
  414. ret = iram->next_paddr;
  415. iram->next_paddr += size;
  416. return ret;
  417. }
  418. static void coda_setup_iram(struct coda_ctx *ctx)
  419. {
  420. struct coda_iram_info *iram_info = &ctx->iram_info;
  421. struct coda_dev *dev = ctx->dev;
  422. int w64, w128;
  423. int mb_width;
  424. int dbk_bits;
  425. int bit_bits;
  426. int ip_bits;
  427. memset(iram_info, 0, sizeof(*iram_info));
  428. iram_info->next_paddr = dev->iram.paddr;
  429. iram_info->remaining = dev->iram.size;
  430. if (!dev->iram.vaddr)
  431. return;
  432. switch (dev->devtype->product) {
  433. case CODA_7541:
  434. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  435. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  436. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  437. break;
  438. case CODA_960:
  439. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  440. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  441. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  442. break;
  443. default: /* CODA_DX6 */
  444. return;
  445. }
  446. if (ctx->inst_type == CODA_INST_ENCODER) {
  447. struct coda_q_data *q_data_src;
  448. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  449. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  450. w128 = mb_width * 128;
  451. w64 = mb_width * 64;
  452. /* Prioritize in case IRAM is too small for everything */
  453. if (dev->devtype->product == CODA_7541) {
  454. iram_info->search_ram_size = round_up(mb_width * 16 *
  455. 36 + 2048, 1024);
  456. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  457. iram_info->search_ram_size);
  458. if (!iram_info->search_ram_paddr) {
  459. pr_err("IRAM is smaller than the search ram size\n");
  460. goto out;
  461. }
  462. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
  463. CODA7_USE_ME_ENABLE;
  464. }
  465. /* Only H.264BP and H.263P3 are considered */
  466. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  467. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  468. if (!iram_info->buf_dbk_c_use)
  469. goto out;
  470. iram_info->axi_sram_use |= dbk_bits;
  471. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  472. if (!iram_info->buf_bit_use)
  473. goto out;
  474. iram_info->axi_sram_use |= bit_bits;
  475. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  476. if (!iram_info->buf_ip_ac_dc_use)
  477. goto out;
  478. iram_info->axi_sram_use |= ip_bits;
  479. /* OVL and BTP disabled for encoder */
  480. } else if (ctx->inst_type == CODA_INST_DECODER) {
  481. struct coda_q_data *q_data_dst;
  482. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  483. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  484. w128 = mb_width * 128;
  485. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  486. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  487. if (!iram_info->buf_dbk_c_use)
  488. goto out;
  489. iram_info->axi_sram_use |= dbk_bits;
  490. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  491. if (!iram_info->buf_bit_use)
  492. goto out;
  493. iram_info->axi_sram_use |= bit_bits;
  494. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  495. if (!iram_info->buf_ip_ac_dc_use)
  496. goto out;
  497. iram_info->axi_sram_use |= ip_bits;
  498. /* OVL and BTP unused as there is no VC1 support yet */
  499. }
  500. out:
  501. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  502. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  503. "IRAM smaller than needed\n");
  504. if (dev->devtype->product == CODA_7541) {
  505. /* TODO - Enabling these causes picture errors on CODA7541 */
  506. if (ctx->inst_type == CODA_INST_DECODER) {
  507. /* fw 1.4.50 */
  508. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  509. CODA7_USE_IP_ENABLE);
  510. } else {
  511. /* fw 13.4.29 */
  512. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  513. CODA7_USE_HOST_DBK_ENABLE |
  514. CODA7_USE_IP_ENABLE |
  515. CODA7_USE_DBK_ENABLE);
  516. }
  517. }
  518. }
  519. static u32 coda_supported_firmwares[] = {
  520. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  521. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  522. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  523. };
  524. static bool coda_firmware_supported(u32 vernum)
  525. {
  526. int i;
  527. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  528. if (vernum == coda_supported_firmwares[i])
  529. return true;
  530. return false;
  531. }
  532. int coda_check_firmware(struct coda_dev *dev)
  533. {
  534. u16 product, major, minor, release;
  535. u32 data;
  536. int ret;
  537. ret = clk_prepare_enable(dev->clk_per);
  538. if (ret)
  539. goto err_clk_per;
  540. ret = clk_prepare_enable(dev->clk_ahb);
  541. if (ret)
  542. goto err_clk_ahb;
  543. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  544. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  545. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  546. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  547. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  548. if (coda_wait_timeout(dev)) {
  549. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  550. ret = -EIO;
  551. goto err_run_cmd;
  552. }
  553. if (dev->devtype->product == CODA_960) {
  554. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  555. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  556. data);
  557. }
  558. /* Check we are compatible with the loaded firmware */
  559. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  560. product = CODA_FIRMWARE_PRODUCT(data);
  561. major = CODA_FIRMWARE_MAJOR(data);
  562. minor = CODA_FIRMWARE_MINOR(data);
  563. release = CODA_FIRMWARE_RELEASE(data);
  564. clk_disable_unprepare(dev->clk_per);
  565. clk_disable_unprepare(dev->clk_ahb);
  566. if (product != dev->devtype->product) {
  567. v4l2_err(&dev->v4l2_dev,
  568. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  569. coda_product_name(dev->devtype->product),
  570. coda_product_name(product), major, minor, release);
  571. return -EINVAL;
  572. }
  573. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  574. coda_product_name(product));
  575. if (coda_firmware_supported(data)) {
  576. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  577. major, minor, release);
  578. } else {
  579. v4l2_warn(&dev->v4l2_dev,
  580. "Unsupported firmware version: %u.%u.%u\n",
  581. major, minor, release);
  582. }
  583. return 0;
  584. err_run_cmd:
  585. clk_disable_unprepare(dev->clk_ahb);
  586. err_clk_ahb:
  587. clk_disable_unprepare(dev->clk_per);
  588. err_clk_per:
  589. return ret;
  590. }
  591. /*
  592. * Encoder context operations
  593. */
  594. static int coda_start_encoding(struct coda_ctx *ctx)
  595. {
  596. struct coda_dev *dev = ctx->dev;
  597. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  598. struct coda_q_data *q_data_src, *q_data_dst;
  599. u32 bitstream_buf, bitstream_size;
  600. struct vb2_buffer *buf;
  601. int gamma, ret, value;
  602. u32 dst_fourcc;
  603. u32 stride;
  604. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  605. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  606. dst_fourcc = q_data_dst->fourcc;
  607. /* Allocate per-instance buffers */
  608. ret = coda_alloc_context_buffers(ctx, q_data_src);
  609. if (ret < 0)
  610. return ret;
  611. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  612. bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
  613. bitstream_size = q_data_dst->sizeimage;
  614. if (!coda_is_initialized(dev)) {
  615. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  616. return -EFAULT;
  617. }
  618. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  619. if (!ctx->params.jpeg_qmat_tab[0])
  620. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  621. if (!ctx->params.jpeg_qmat_tab[1])
  622. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  623. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  624. }
  625. mutex_lock(&dev->coda_mutex);
  626. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  627. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  628. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  629. switch (dev->devtype->product) {
  630. case CODA_DX6:
  631. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  632. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  633. break;
  634. case CODA_960:
  635. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  636. /* fallthrough */
  637. case CODA_7541:
  638. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  639. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  640. break;
  641. }
  642. ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
  643. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  644. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  645. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  646. if (dev->devtype->product == CODA_DX6) {
  647. /* Configure the coda */
  648. coda_write(dev, dev->iram.paddr,
  649. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  650. }
  651. /* Could set rotation here if needed */
  652. value = 0;
  653. switch (dev->devtype->product) {
  654. case CODA_DX6:
  655. value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
  656. << CODADX6_PICWIDTH_OFFSET;
  657. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
  658. << CODA_PICHEIGHT_OFFSET;
  659. break;
  660. case CODA_7541:
  661. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  662. value = (round_up(q_data_src->width, 16) &
  663. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  664. value |= (round_up(q_data_src->height, 16) &
  665. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  666. break;
  667. }
  668. /* fallthrough */
  669. case CODA_960:
  670. value = (q_data_src->width & CODA7_PICWIDTH_MASK)
  671. << CODA7_PICWIDTH_OFFSET;
  672. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
  673. << CODA_PICHEIGHT_OFFSET;
  674. }
  675. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  676. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  677. ctx->params.framerate = 0;
  678. coda_write(dev, ctx->params.framerate,
  679. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  680. ctx->params.codec_mode = ctx->codec->mode;
  681. switch (dst_fourcc) {
  682. case V4L2_PIX_FMT_MPEG4:
  683. if (dev->devtype->product == CODA_960)
  684. coda_write(dev, CODA9_STD_MPEG4,
  685. CODA_CMD_ENC_SEQ_COD_STD);
  686. else
  687. coda_write(dev, CODA_STD_MPEG4,
  688. CODA_CMD_ENC_SEQ_COD_STD);
  689. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  690. break;
  691. case V4L2_PIX_FMT_H264:
  692. if (dev->devtype->product == CODA_960)
  693. coda_write(dev, CODA9_STD_H264,
  694. CODA_CMD_ENC_SEQ_COD_STD);
  695. else
  696. coda_write(dev, CODA_STD_H264,
  697. CODA_CMD_ENC_SEQ_COD_STD);
  698. if (ctx->params.h264_deblk_enabled) {
  699. value = ((ctx->params.h264_deblk_alpha &
  700. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  701. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  702. ((ctx->params.h264_deblk_beta &
  703. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  704. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  705. } else {
  706. value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
  707. }
  708. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  709. break;
  710. case V4L2_PIX_FMT_JPEG:
  711. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  712. coda_write(dev, ctx->params.jpeg_restart_interval,
  713. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  714. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  715. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  716. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  717. coda_jpeg_write_tables(ctx);
  718. break;
  719. default:
  720. v4l2_err(v4l2_dev,
  721. "dst format (0x%08x) invalid.\n", dst_fourcc);
  722. ret = -EINVAL;
  723. goto out;
  724. }
  725. /*
  726. * slice mode and GOP size registers are used for thumb size/offset
  727. * in JPEG mode
  728. */
  729. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  730. switch (ctx->params.slice_mode) {
  731. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  732. value = 0;
  733. break;
  734. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  735. value = (ctx->params.slice_max_mb &
  736. CODA_SLICING_SIZE_MASK)
  737. << CODA_SLICING_SIZE_OFFSET;
  738. value |= (1 & CODA_SLICING_UNIT_MASK)
  739. << CODA_SLICING_UNIT_OFFSET;
  740. value |= 1 & CODA_SLICING_MODE_MASK;
  741. break;
  742. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  743. value = (ctx->params.slice_max_bits &
  744. CODA_SLICING_SIZE_MASK)
  745. << CODA_SLICING_SIZE_OFFSET;
  746. value |= (0 & CODA_SLICING_UNIT_MASK)
  747. << CODA_SLICING_UNIT_OFFSET;
  748. value |= 1 & CODA_SLICING_MODE_MASK;
  749. break;
  750. }
  751. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  752. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  753. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  754. }
  755. if (ctx->params.bitrate) {
  756. /* Rate control enabled */
  757. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  758. << CODA_RATECONTROL_BITRATE_OFFSET;
  759. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  760. if (dev->devtype->product == CODA_960)
  761. value |= BIT(31); /* disable autoskip */
  762. } else {
  763. value = 0;
  764. }
  765. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  766. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  767. coda_write(dev, ctx->params.intra_refresh,
  768. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  769. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  770. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  771. value = 0;
  772. if (dev->devtype->product == CODA_960)
  773. gamma = CODA9_DEFAULT_GAMMA;
  774. else
  775. gamma = CODA_DEFAULT_GAMMA;
  776. if (gamma > 0) {
  777. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  778. CODA_CMD_ENC_SEQ_RC_GAMMA);
  779. }
  780. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  781. coda_write(dev,
  782. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  783. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  784. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  785. }
  786. if (dev->devtype->product == CODA_960) {
  787. if (ctx->params.h264_max_qp)
  788. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  789. if (CODA_DEFAULT_GAMMA > 0)
  790. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  791. } else {
  792. if (CODA_DEFAULT_GAMMA > 0) {
  793. if (dev->devtype->product == CODA_DX6)
  794. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  795. else
  796. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  797. }
  798. if (ctx->params.h264_min_qp)
  799. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  800. if (ctx->params.h264_max_qp)
  801. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  802. }
  803. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  804. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  805. coda_setup_iram(ctx);
  806. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  807. switch (dev->devtype->product) {
  808. case CODA_DX6:
  809. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  810. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  811. break;
  812. case CODA_7541:
  813. coda_write(dev, ctx->iram_info.search_ram_paddr,
  814. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  815. coda_write(dev, ctx->iram_info.search_ram_size,
  816. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  817. break;
  818. case CODA_960:
  819. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  820. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  821. }
  822. }
  823. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  824. if (ret < 0) {
  825. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  826. goto out;
  827. }
  828. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  829. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  830. ret = -EFAULT;
  831. goto out;
  832. }
  833. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  834. if (dev->devtype->product == CODA_960)
  835. ctx->num_internal_frames = 4;
  836. else
  837. ctx->num_internal_frames = 2;
  838. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  839. if (ret < 0) {
  840. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  841. goto out;
  842. }
  843. stride = q_data_src->bytesperline;
  844. } else {
  845. ctx->num_internal_frames = 0;
  846. stride = 0;
  847. }
  848. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  849. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  850. if (dev->devtype->product == CODA_7541) {
  851. coda_write(dev, q_data_src->bytesperline,
  852. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  853. }
  854. if (dev->devtype->product != CODA_DX6) {
  855. coda_write(dev, ctx->iram_info.buf_bit_use,
  856. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  857. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  858. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  859. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  860. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  861. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  862. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  863. coda_write(dev, ctx->iram_info.buf_ovl_use,
  864. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  865. if (dev->devtype->product == CODA_960) {
  866. coda_write(dev, ctx->iram_info.buf_btp_use,
  867. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  868. /* FIXME */
  869. coda_write(dev, ctx->internal_frames[2].paddr,
  870. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  871. coda_write(dev, ctx->internal_frames[3].paddr,
  872. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  873. }
  874. }
  875. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  876. if (ret < 0) {
  877. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  878. goto out;
  879. }
  880. /* Save stream headers */
  881. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  882. switch (dst_fourcc) {
  883. case V4L2_PIX_FMT_H264:
  884. /*
  885. * Get SPS in the first frame and copy it to an
  886. * intermediate buffer.
  887. */
  888. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  889. &ctx->vpu_header[0][0],
  890. &ctx->vpu_header_size[0]);
  891. if (ret < 0)
  892. goto out;
  893. /*
  894. * Get PPS in the first frame and copy it to an
  895. * intermediate buffer.
  896. */
  897. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  898. &ctx->vpu_header[1][0],
  899. &ctx->vpu_header_size[1]);
  900. if (ret < 0)
  901. goto out;
  902. /*
  903. * Length of H.264 headers is variable and thus it might not be
  904. * aligned for the coda to append the encoded frame. In that is
  905. * the case a filler NAL must be added to header 2.
  906. */
  907. ctx->vpu_header_size[2] = coda_h264_padding(
  908. (ctx->vpu_header_size[0] +
  909. ctx->vpu_header_size[1]),
  910. ctx->vpu_header[2]);
  911. break;
  912. case V4L2_PIX_FMT_MPEG4:
  913. /*
  914. * Get VOS in the first frame and copy it to an
  915. * intermediate buffer
  916. */
  917. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  918. &ctx->vpu_header[0][0],
  919. &ctx->vpu_header_size[0]);
  920. if (ret < 0)
  921. goto out;
  922. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  923. &ctx->vpu_header[1][0],
  924. &ctx->vpu_header_size[1]);
  925. if (ret < 0)
  926. goto out;
  927. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  928. &ctx->vpu_header[2][0],
  929. &ctx->vpu_header_size[2]);
  930. if (ret < 0)
  931. goto out;
  932. break;
  933. default:
  934. /* No more formats need to save headers at the moment */
  935. break;
  936. }
  937. out:
  938. mutex_unlock(&dev->coda_mutex);
  939. return ret;
  940. }
  941. static int coda_prepare_encode(struct coda_ctx *ctx)
  942. {
  943. struct coda_q_data *q_data_src, *q_data_dst;
  944. struct vb2_buffer *src_buf, *dst_buf;
  945. struct coda_dev *dev = ctx->dev;
  946. int force_ipicture;
  947. int quant_param = 0;
  948. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  949. u32 rot_mode = 0;
  950. u32 dst_fourcc;
  951. u32 reg;
  952. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  953. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  954. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  955. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  956. dst_fourcc = q_data_dst->fourcc;
  957. src_buf->v4l2_buf.sequence = ctx->osequence;
  958. dst_buf->v4l2_buf.sequence = ctx->osequence;
  959. ctx->osequence++;
  960. /*
  961. * Workaround coda firmware BUG that only marks the first
  962. * frame as IDR. This is a problem for some decoders that can't
  963. * recover when a frame is lost.
  964. */
  965. if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
  966. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  967. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  968. } else {
  969. src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  970. src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  971. }
  972. if (dev->devtype->product == CODA_960)
  973. coda_set_gdi_regs(ctx);
  974. /*
  975. * Copy headers at the beginning of the first frame for H.264 only.
  976. * In MPEG4 they are already copied by the coda.
  977. */
  978. if (src_buf->v4l2_buf.sequence == 0) {
  979. pic_stream_buffer_addr =
  980. vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
  981. ctx->vpu_header_size[0] +
  982. ctx->vpu_header_size[1] +
  983. ctx->vpu_header_size[2];
  984. pic_stream_buffer_size = q_data_dst->sizeimage -
  985. ctx->vpu_header_size[0] -
  986. ctx->vpu_header_size[1] -
  987. ctx->vpu_header_size[2];
  988. memcpy(vb2_plane_vaddr(dst_buf, 0),
  989. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  990. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
  991. &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
  992. memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
  993. ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
  994. ctx->vpu_header_size[2]);
  995. } else {
  996. pic_stream_buffer_addr =
  997. vb2_dma_contig_plane_dma_addr(dst_buf, 0);
  998. pic_stream_buffer_size = q_data_dst->sizeimage;
  999. }
  1000. if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
  1001. force_ipicture = 1;
  1002. switch (dst_fourcc) {
  1003. case V4L2_PIX_FMT_H264:
  1004. quant_param = ctx->params.h264_intra_qp;
  1005. break;
  1006. case V4L2_PIX_FMT_MPEG4:
  1007. quant_param = ctx->params.mpeg4_intra_qp;
  1008. break;
  1009. case V4L2_PIX_FMT_JPEG:
  1010. quant_param = 30;
  1011. break;
  1012. default:
  1013. v4l2_warn(&ctx->dev->v4l2_dev,
  1014. "cannot set intra qp, fmt not supported\n");
  1015. break;
  1016. }
  1017. } else {
  1018. force_ipicture = 0;
  1019. switch (dst_fourcc) {
  1020. case V4L2_PIX_FMT_H264:
  1021. quant_param = ctx->params.h264_inter_qp;
  1022. break;
  1023. case V4L2_PIX_FMT_MPEG4:
  1024. quant_param = ctx->params.mpeg4_inter_qp;
  1025. break;
  1026. default:
  1027. v4l2_warn(&ctx->dev->v4l2_dev,
  1028. "cannot set inter qp, fmt not supported\n");
  1029. break;
  1030. }
  1031. }
  1032. /* submit */
  1033. if (ctx->params.rot_mode)
  1034. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1035. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1036. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1037. if (dev->devtype->product == CODA_960) {
  1038. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1039. coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1040. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1041. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1042. } else {
  1043. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1044. }
  1045. coda_write_base(ctx, q_data_src, src_buf, reg);
  1046. coda_write(dev, force_ipicture << 1 & 0x2,
  1047. CODA_CMD_ENC_PIC_OPTION);
  1048. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1049. coda_write(dev, pic_stream_buffer_size / 1024,
  1050. CODA_CMD_ENC_PIC_BB_SIZE);
  1051. if (!ctx->streamon_out) {
  1052. /* After streamoff on the output side, set stream end flag */
  1053. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1054. coda_write(dev, ctx->bit_stream_param,
  1055. CODA_REG_BIT_BIT_STREAM_PARAM);
  1056. }
  1057. if (dev->devtype->product != CODA_DX6)
  1058. coda_write(dev, ctx->iram_info.axi_sram_use,
  1059. CODA7_REG_BIT_AXI_SRAM_USE);
  1060. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1061. return 0;
  1062. }
  1063. static void coda_finish_encode(struct coda_ctx *ctx)
  1064. {
  1065. struct vb2_buffer *src_buf, *dst_buf;
  1066. struct coda_dev *dev = ctx->dev;
  1067. u32 wr_ptr, start_ptr;
  1068. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1069. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1070. /* Get results from the coda */
  1071. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1072. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1073. /* Calculate bytesused field */
  1074. if (dst_buf->v4l2_buf.sequence == 0) {
  1075. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr +
  1076. ctx->vpu_header_size[0] +
  1077. ctx->vpu_header_size[1] +
  1078. ctx->vpu_header_size[2]);
  1079. } else {
  1080. vb2_set_plane_payload(dst_buf, 0, wr_ptr - start_ptr);
  1081. }
  1082. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1083. wr_ptr - start_ptr);
  1084. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1085. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1086. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1087. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
  1088. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
  1089. } else {
  1090. dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
  1091. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1092. }
  1093. dst_buf->v4l2_buf.timestamp = src_buf->v4l2_buf.timestamp;
  1094. dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1095. dst_buf->v4l2_buf.flags |=
  1096. src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1097. dst_buf->v4l2_buf.timecode = src_buf->v4l2_buf.timecode;
  1098. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1099. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1100. v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
  1101. ctx->gopcounter--;
  1102. if (ctx->gopcounter < 0)
  1103. ctx->gopcounter = ctx->params.gop_size - 1;
  1104. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1105. "job finished: encoding frame (%d) (%s)\n",
  1106. dst_buf->v4l2_buf.sequence,
  1107. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1108. "KEYFRAME" : "PFRAME");
  1109. }
  1110. static void coda_seq_end_work(struct work_struct *work)
  1111. {
  1112. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1113. struct coda_dev *dev = ctx->dev;
  1114. mutex_lock(&ctx->buffer_mutex);
  1115. mutex_lock(&dev->coda_mutex);
  1116. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1117. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1118. __func__);
  1119. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1120. v4l2_err(&dev->v4l2_dev,
  1121. "CODA_COMMAND_SEQ_END failed\n");
  1122. }
  1123. kfifo_init(&ctx->bitstream_fifo,
  1124. ctx->bitstream.vaddr, ctx->bitstream.size);
  1125. coda_free_framebuffers(ctx);
  1126. coda_free_context_buffers(ctx);
  1127. mutex_unlock(&dev->coda_mutex);
  1128. mutex_unlock(&ctx->buffer_mutex);
  1129. }
  1130. static void coda_bit_release(struct coda_ctx *ctx)
  1131. {
  1132. coda_free_framebuffers(ctx);
  1133. coda_free_context_buffers(ctx);
  1134. }
  1135. const struct coda_context_ops coda_bit_encode_ops = {
  1136. .queue_init = coda_encoder_queue_init,
  1137. .start_streaming = coda_start_encoding,
  1138. .prepare_run = coda_prepare_encode,
  1139. .finish_run = coda_finish_encode,
  1140. .seq_end_work = coda_seq_end_work,
  1141. .release = coda_bit_release,
  1142. };
  1143. /*
  1144. * Decoder context operations
  1145. */
  1146. static int __coda_start_decoding(struct coda_ctx *ctx)
  1147. {
  1148. struct coda_q_data *q_data_src, *q_data_dst;
  1149. u32 bitstream_buf, bitstream_size;
  1150. struct coda_dev *dev = ctx->dev;
  1151. int width, height;
  1152. u32 src_fourcc, dst_fourcc;
  1153. u32 val;
  1154. int ret;
  1155. /* Start decoding */
  1156. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1157. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1158. bitstream_buf = ctx->bitstream.paddr;
  1159. bitstream_size = ctx->bitstream.size;
  1160. src_fourcc = q_data_src->fourcc;
  1161. dst_fourcc = q_data_dst->fourcc;
  1162. /* Allocate per-instance buffers */
  1163. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1164. if (ret < 0)
  1165. return ret;
  1166. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1167. /* Update coda bitstream read and write pointers from kfifo */
  1168. coda_kfifo_sync_to_device_full(ctx);
  1169. ctx->frame_mem_ctrl &= ~CODA_FRAME_CHROMA_INTERLEAVE;
  1170. if (dst_fourcc == V4L2_PIX_FMT_NV12)
  1171. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1172. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1173. ctx->display_idx = -1;
  1174. ctx->frm_dis_flg = 0;
  1175. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1176. coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
  1177. CODA_REG_BIT_BIT_STREAM_PARAM);
  1178. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1179. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1180. val = 0;
  1181. if ((dev->devtype->product == CODA_7541) ||
  1182. (dev->devtype->product == CODA_960))
  1183. val |= CODA_REORDER_ENABLE;
  1184. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1185. val |= CODA_NO_INT_ENABLE;
  1186. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1187. ctx->params.codec_mode = ctx->codec->mode;
  1188. if (dev->devtype->product == CODA_960 &&
  1189. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1190. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1191. else
  1192. ctx->params.codec_mode_aux = 0;
  1193. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1194. if (dev->devtype->product == CODA_7541) {
  1195. coda_write(dev, ctx->psbuf.paddr,
  1196. CODA_CMD_DEC_SEQ_PS_BB_START);
  1197. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1198. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1199. }
  1200. if (dev->devtype->product == CODA_960) {
  1201. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1202. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1203. }
  1204. }
  1205. if (dev->devtype->product != CODA_960)
  1206. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1207. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  1208. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1209. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1210. return -ETIMEDOUT;
  1211. }
  1212. /* Update kfifo out pointer from coda bitstream read pointer */
  1213. coda_kfifo_sync_from_device(ctx);
  1214. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1215. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1216. v4l2_err(&dev->v4l2_dev,
  1217. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1218. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1219. return -EAGAIN;
  1220. }
  1221. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1222. if (dev->devtype->product == CODA_DX6) {
  1223. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1224. height = val & CODADX6_PICHEIGHT_MASK;
  1225. } else {
  1226. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1227. height = val & CODA7_PICHEIGHT_MASK;
  1228. }
  1229. if (width > q_data_dst->width || height > q_data_dst->height) {
  1230. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1231. width, height, q_data_dst->width, q_data_dst->height);
  1232. return -EINVAL;
  1233. }
  1234. width = round_up(width, 16);
  1235. height = round_up(height, 16);
  1236. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1237. __func__, ctx->idx, width, height);
  1238. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1239. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1240. v4l2_err(&dev->v4l2_dev,
  1241. "not enough framebuffers to decode (%d < %d)\n",
  1242. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1243. return -EINVAL;
  1244. }
  1245. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1246. u32 left_right;
  1247. u32 top_bottom;
  1248. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1249. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1250. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1251. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1252. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1253. (left_right & 0x3ff);
  1254. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1255. (top_bottom & 0x3ff);
  1256. }
  1257. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1258. if (ret < 0) {
  1259. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1260. return ret;
  1261. }
  1262. /* Tell the decoder how many frame buffers we allocated. */
  1263. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1264. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1265. if (dev->devtype->product != CODA_DX6) {
  1266. /* Set secondary AXI IRAM */
  1267. coda_setup_iram(ctx);
  1268. coda_write(dev, ctx->iram_info.buf_bit_use,
  1269. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1270. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1271. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1272. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1273. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1274. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1275. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1276. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1277. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1278. if (dev->devtype->product == CODA_960)
  1279. coda_write(dev, ctx->iram_info.buf_btp_use,
  1280. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1281. }
  1282. if (dev->devtype->product == CODA_960) {
  1283. int cbb_size, crb_size;
  1284. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1285. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  1286. coda_write(dev, 0x20262024, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  1287. if (dst_fourcc == V4L2_PIX_FMT_NV12) {
  1288. cbb_size = 0;
  1289. crb_size = 16;
  1290. } else {
  1291. cbb_size = 8;
  1292. crb_size = 8;
  1293. }
  1294. coda_write(dev, 2 << CODA9_CACHE_PAGEMERGE_OFFSET |
  1295. 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  1296. cbb_size << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET |
  1297. crb_size << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET,
  1298. CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  1299. }
  1300. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1301. coda_write(dev, ctx->slicebuf.paddr,
  1302. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1303. coda_write(dev, ctx->slicebuf.size / 1024,
  1304. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1305. }
  1306. if (dev->devtype->product == CODA_7541) {
  1307. int max_mb_x = 1920 / 16;
  1308. int max_mb_y = 1088 / 16;
  1309. int max_mb_num = max_mb_x * max_mb_y;
  1310. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1311. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1312. } else if (dev->devtype->product == CODA_960) {
  1313. int max_mb_x = 1920 / 16;
  1314. int max_mb_y = 1088 / 16;
  1315. int max_mb_num = max_mb_x * max_mb_y;
  1316. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1317. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1318. }
  1319. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1320. v4l2_err(&ctx->dev->v4l2_dev,
  1321. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1322. return -ETIMEDOUT;
  1323. }
  1324. return 0;
  1325. }
  1326. static int coda_start_decoding(struct coda_ctx *ctx)
  1327. {
  1328. struct coda_dev *dev = ctx->dev;
  1329. int ret;
  1330. mutex_lock(&dev->coda_mutex);
  1331. ret = __coda_start_decoding(ctx);
  1332. mutex_unlock(&dev->coda_mutex);
  1333. return ret;
  1334. }
  1335. static int coda_prepare_decode(struct coda_ctx *ctx)
  1336. {
  1337. struct vb2_buffer *dst_buf;
  1338. struct coda_dev *dev = ctx->dev;
  1339. struct coda_q_data *q_data_dst;
  1340. u32 reg_addr, reg_stride;
  1341. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1342. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1343. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1344. mutex_lock(&ctx->bitstream_mutex);
  1345. coda_fill_bitstream(ctx);
  1346. mutex_unlock(&ctx->bitstream_mutex);
  1347. if (coda_get_bitstream_payload(ctx) < 512 &&
  1348. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1349. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1350. "bitstream payload: %d, skipping\n",
  1351. coda_get_bitstream_payload(ctx));
  1352. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1353. return -EAGAIN;
  1354. }
  1355. /* Run coda_start_decoding (again) if not yet initialized */
  1356. if (!ctx->initialized) {
  1357. int ret = __coda_start_decoding(ctx);
  1358. if (ret < 0) {
  1359. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1360. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1361. return -EAGAIN;
  1362. } else {
  1363. ctx->initialized = 1;
  1364. }
  1365. }
  1366. if (dev->devtype->product == CODA_960)
  1367. coda_set_gdi_regs(ctx);
  1368. if (dev->devtype->product == CODA_960) {
  1369. /*
  1370. * The CODA960 seems to have an internal list of buffers with
  1371. * 64 entries that includes the registered frame buffers as
  1372. * well as the rotator buffer output.
  1373. * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
  1374. */
  1375. coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->v4l2_buf.index,
  1376. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1377. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1378. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1379. } else {
  1380. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1381. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1382. }
  1383. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1384. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1385. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  1386. CODA_CMD_DEC_PIC_ROT_MODE);
  1387. switch (dev->devtype->product) {
  1388. case CODA_DX6:
  1389. /* TBD */
  1390. case CODA_7541:
  1391. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1392. break;
  1393. case CODA_960:
  1394. /* 'hardcode to use interrupt disable mode'? */
  1395. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1396. break;
  1397. }
  1398. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1399. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1400. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1401. if (dev->devtype->product != CODA_DX6)
  1402. coda_write(dev, ctx->iram_info.axi_sram_use,
  1403. CODA7_REG_BIT_AXI_SRAM_USE);
  1404. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1405. struct coda_buffer_meta *meta;
  1406. /* If this is the last buffer in the bitstream, add padding */
  1407. meta = list_first_entry(&ctx->buffer_meta_list,
  1408. struct coda_buffer_meta, list);
  1409. if (meta->end == (ctx->bitstream_fifo.kfifo.in &
  1410. ctx->bitstream_fifo.kfifo.mask)) {
  1411. static unsigned char buf[512];
  1412. unsigned int pad;
  1413. /* Pad to multiple of 256 and then add 256 more */
  1414. pad = ((0 - meta->end) & 0xff) + 256;
  1415. memset(buf, 0xff, sizeof(buf));
  1416. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1417. }
  1418. }
  1419. coda_kfifo_sync_to_device_full(ctx);
  1420. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1421. return 0;
  1422. }
  1423. static void coda_finish_decode(struct coda_ctx *ctx)
  1424. {
  1425. struct coda_dev *dev = ctx->dev;
  1426. struct coda_q_data *q_data_src;
  1427. struct coda_q_data *q_data_dst;
  1428. struct vb2_buffer *dst_buf;
  1429. struct coda_buffer_meta *meta;
  1430. unsigned long payload;
  1431. int width, height;
  1432. int decoded_idx;
  1433. int display_idx;
  1434. u32 src_fourcc;
  1435. int success;
  1436. u32 err_mb;
  1437. u32 val;
  1438. /* Update kfifo out pointer from coda bitstream read pointer */
  1439. coda_kfifo_sync_from_device(ctx);
  1440. /*
  1441. * in stream-end mode, the read pointer can overshoot the write pointer
  1442. * by up to 512 bytes
  1443. */
  1444. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1445. if (coda_get_bitstream_payload(ctx) >= CODA_MAX_FRAME_SIZE - 512)
  1446. kfifo_init(&ctx->bitstream_fifo,
  1447. ctx->bitstream.vaddr, ctx->bitstream.size);
  1448. }
  1449. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1450. src_fourcc = q_data_src->fourcc;
  1451. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1452. if (val != 1)
  1453. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1454. success = val & 0x1;
  1455. if (!success)
  1456. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1457. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1458. if (val & (1 << 3))
  1459. v4l2_err(&dev->v4l2_dev,
  1460. "insufficient PS buffer space (%d bytes)\n",
  1461. ctx->psbuf.size);
  1462. if (val & (1 << 2))
  1463. v4l2_err(&dev->v4l2_dev,
  1464. "insufficient slice buffer space (%d bytes)\n",
  1465. ctx->slicebuf.size);
  1466. }
  1467. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1468. width = (val >> 16) & 0xffff;
  1469. height = val & 0xffff;
  1470. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1471. /* frame crop information */
  1472. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1473. u32 left_right;
  1474. u32 top_bottom;
  1475. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1476. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1477. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1478. /* Keep current crop information */
  1479. } else {
  1480. struct v4l2_rect *rect = &q_data_dst->rect;
  1481. rect->left = left_right >> 16 & 0xffff;
  1482. rect->top = top_bottom >> 16 & 0xffff;
  1483. rect->width = width - rect->left -
  1484. (left_right & 0xffff);
  1485. rect->height = height - rect->top -
  1486. (top_bottom & 0xffff);
  1487. }
  1488. } else {
  1489. /* no cropping */
  1490. }
  1491. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1492. if (err_mb > 0)
  1493. v4l2_err(&dev->v4l2_dev,
  1494. "errors in %d macroblocks\n", err_mb);
  1495. if (dev->devtype->product == CODA_7541) {
  1496. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1497. if (val == 0) {
  1498. /* not enough bitstream data */
  1499. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1500. "prescan failed: %d\n", val);
  1501. ctx->hold = true;
  1502. return;
  1503. }
  1504. }
  1505. ctx->frm_dis_flg = coda_read(dev,
  1506. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1507. /*
  1508. * The previous display frame was copied out by the rotator,
  1509. * now it can be overwritten again
  1510. */
  1511. if (ctx->display_idx >= 0 &&
  1512. ctx->display_idx < ctx->num_internal_frames) {
  1513. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1514. coda_write(dev, ctx->frm_dis_flg,
  1515. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1516. }
  1517. /*
  1518. * The index of the last decoded frame, not necessarily in
  1519. * display order, and the index of the next display frame.
  1520. * The latter could have been decoded in a previous run.
  1521. */
  1522. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1523. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1524. if (decoded_idx == -1) {
  1525. /* no frame was decoded, but we might have a display frame */
  1526. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1527. ctx->sequence_offset++;
  1528. else if (ctx->display_idx < 0)
  1529. ctx->hold = true;
  1530. } else if (decoded_idx == -2) {
  1531. /* no frame was decoded, we still return remaining buffers */
  1532. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1533. v4l2_err(&dev->v4l2_dev,
  1534. "decoded frame index out of range: %d\n", decoded_idx);
  1535. } else {
  1536. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
  1537. val -= ctx->sequence_offset;
  1538. mutex_lock(&ctx->bitstream_mutex);
  1539. if (!list_empty(&ctx->buffer_meta_list)) {
  1540. meta = list_first_entry(&ctx->buffer_meta_list,
  1541. struct coda_buffer_meta, list);
  1542. list_del(&meta->list);
  1543. if (val != (meta->sequence & 0xffff)) {
  1544. v4l2_err(&dev->v4l2_dev,
  1545. "sequence number mismatch (%d(%d) != %d)\n",
  1546. val, ctx->sequence_offset,
  1547. meta->sequence);
  1548. }
  1549. ctx->frame_metas[decoded_idx] = *meta;
  1550. kfree(meta);
  1551. } else {
  1552. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1553. memset(&ctx->frame_metas[decoded_idx], 0,
  1554. sizeof(struct coda_buffer_meta));
  1555. ctx->frame_metas[decoded_idx].sequence = val;
  1556. }
  1557. mutex_unlock(&ctx->bitstream_mutex);
  1558. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1559. if (val == 0)
  1560. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1561. else if (val == 1)
  1562. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1563. else
  1564. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1565. ctx->frame_errors[decoded_idx] = err_mb;
  1566. }
  1567. if (display_idx == -1) {
  1568. /*
  1569. * no more frames to be decoded, but there could still
  1570. * be rotator output to dequeue
  1571. */
  1572. ctx->hold = true;
  1573. } else if (display_idx == -3) {
  1574. /* possibly prescan failure */
  1575. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1576. v4l2_err(&dev->v4l2_dev,
  1577. "presentation frame index out of range: %d\n",
  1578. display_idx);
  1579. }
  1580. /* If a frame was copied out, return it */
  1581. if (ctx->display_idx >= 0 &&
  1582. ctx->display_idx < ctx->num_internal_frames) {
  1583. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1584. dst_buf->v4l2_buf.sequence = ctx->osequence++;
  1585. dst_buf->v4l2_buf.flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1586. V4L2_BUF_FLAG_PFRAME |
  1587. V4L2_BUF_FLAG_BFRAME);
  1588. dst_buf->v4l2_buf.flags |= ctx->frame_types[ctx->display_idx];
  1589. meta = &ctx->frame_metas[ctx->display_idx];
  1590. dst_buf->v4l2_buf.timecode = meta->timecode;
  1591. dst_buf->v4l2_buf.timestamp = meta->timestamp;
  1592. switch (q_data_dst->fourcc) {
  1593. case V4L2_PIX_FMT_YUV420:
  1594. case V4L2_PIX_FMT_YVU420:
  1595. case V4L2_PIX_FMT_NV12:
  1596. default:
  1597. payload = width * height * 3 / 2;
  1598. break;
  1599. case V4L2_PIX_FMT_YUV422P:
  1600. payload = width * height * 2;
  1601. break;
  1602. }
  1603. vb2_set_plane_payload(dst_buf, 0, payload);
  1604. v4l2_m2m_buf_done(dst_buf, ctx->frame_errors[display_idx] ?
  1605. VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  1606. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1607. "job finished: decoding frame (%d) (%s)\n",
  1608. dst_buf->v4l2_buf.sequence,
  1609. (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1610. "KEYFRAME" : "PFRAME");
  1611. } else {
  1612. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1613. "job finished: no frame decoded\n");
  1614. }
  1615. /* The rotator will copy the current display frame next time */
  1616. ctx->display_idx = display_idx;
  1617. }
  1618. const struct coda_context_ops coda_bit_decode_ops = {
  1619. .queue_init = coda_decoder_queue_init,
  1620. .start_streaming = coda_start_decoding,
  1621. .prepare_run = coda_prepare_decode,
  1622. .finish_run = coda_finish_decode,
  1623. .seq_end_work = coda_seq_end_work,
  1624. .release = coda_bit_release,
  1625. };
  1626. irqreturn_t coda_irq_handler(int irq, void *data)
  1627. {
  1628. struct coda_dev *dev = data;
  1629. struct coda_ctx *ctx;
  1630. /* read status register to attend the IRQ */
  1631. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1632. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1633. CODA_REG_BIT_INT_CLEAR);
  1634. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1635. if (ctx == NULL) {
  1636. v4l2_err(&dev->v4l2_dev,
  1637. "Instance released before the end of transaction\n");
  1638. mutex_unlock(&dev->coda_mutex);
  1639. return IRQ_HANDLED;
  1640. }
  1641. if (ctx->aborting) {
  1642. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1643. "task has been aborted\n");
  1644. }
  1645. if (coda_isbusy(ctx->dev)) {
  1646. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1647. "coda is still busy!!!!\n");
  1648. return IRQ_NONE;
  1649. }
  1650. complete(&ctx->completion);
  1651. return IRQ_HANDLED;
  1652. }