s5c73m3-core.c 42 KB

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  1. /*
  2. * Samsung LSI S5C73M3 8M pixel camera driver
  3. *
  4. * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. * Andrzej Hajda <a.hajda@samsung.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/clk.h>
  18. #include <linux/delay.h>
  19. #include <linux/firmware.h>
  20. #include <linux/gpio.h>
  21. #include <linux/i2c.h>
  22. #include <linux/init.h>
  23. #include <linux/media.h>
  24. #include <linux/module.h>
  25. #include <linux/of_gpio.h>
  26. #include <linux/regulator/consumer.h>
  27. #include <linux/sizes.h>
  28. #include <linux/slab.h>
  29. #include <linux/spi/spi.h>
  30. #include <linux/videodev2.h>
  31. #include <media/media-entity.h>
  32. #include <media/v4l2-ctrls.h>
  33. #include <media/v4l2-device.h>
  34. #include <media/v4l2-subdev.h>
  35. #include <media/v4l2-mediabus.h>
  36. #include <media/s5c73m3.h>
  37. #include <media/v4l2-of.h>
  38. #include "s5c73m3.h"
  39. int s5c73m3_dbg;
  40. module_param_named(debug, s5c73m3_dbg, int, 0644);
  41. static int boot_from_rom = 1;
  42. module_param(boot_from_rom, int, 0644);
  43. static int update_fw;
  44. module_param(update_fw, int, 0644);
  45. #define S5C73M3_EMBEDDED_DATA_MAXLEN SZ_4K
  46. #define S5C73M3_MIPI_DATA_LANES 4
  47. #define S5C73M3_CLK_NAME "cis_extclk"
  48. static const char * const s5c73m3_supply_names[S5C73M3_MAX_SUPPLIES] = {
  49. "vdd-int", /* Digital Core supply (1.2V), CAM_ISP_CORE_1.2V */
  50. "vdda", /* Analog Core supply (1.2V), CAM_SENSOR_CORE_1.2V */
  51. "vdd-reg", /* Regulator input supply (2.8V), CAM_SENSOR_A2.8V */
  52. "vddio-host", /* Digital Host I/O power supply (1.8V...2.8V),
  53. CAM_ISP_SENSOR_1.8V */
  54. "vddio-cis", /* Digital CIS I/O power (1.2V...1.8V),
  55. CAM_ISP_MIPI_1.2V */
  56. "vdd-af", /* Lens, CAM_AF_2.8V */
  57. };
  58. static const struct s5c73m3_frame_size s5c73m3_isp_resolutions[] = {
  59. { 320, 240, COMM_CHG_MODE_YUV_320_240 },
  60. { 352, 288, COMM_CHG_MODE_YUV_352_288 },
  61. { 640, 480, COMM_CHG_MODE_YUV_640_480 },
  62. { 880, 720, COMM_CHG_MODE_YUV_880_720 },
  63. { 960, 720, COMM_CHG_MODE_YUV_960_720 },
  64. { 1008, 672, COMM_CHG_MODE_YUV_1008_672 },
  65. { 1184, 666, COMM_CHG_MODE_YUV_1184_666 },
  66. { 1280, 720, COMM_CHG_MODE_YUV_1280_720 },
  67. { 1536, 864, COMM_CHG_MODE_YUV_1536_864 },
  68. { 1600, 1200, COMM_CHG_MODE_YUV_1600_1200 },
  69. { 1632, 1224, COMM_CHG_MODE_YUV_1632_1224 },
  70. { 1920, 1080, COMM_CHG_MODE_YUV_1920_1080 },
  71. { 1920, 1440, COMM_CHG_MODE_YUV_1920_1440 },
  72. { 2304, 1296, COMM_CHG_MODE_YUV_2304_1296 },
  73. { 3264, 2448, COMM_CHG_MODE_YUV_3264_2448 },
  74. };
  75. static const struct s5c73m3_frame_size s5c73m3_jpeg_resolutions[] = {
  76. { 640, 480, COMM_CHG_MODE_JPEG_640_480 },
  77. { 800, 450, COMM_CHG_MODE_JPEG_800_450 },
  78. { 800, 600, COMM_CHG_MODE_JPEG_800_600 },
  79. { 1024, 768, COMM_CHG_MODE_JPEG_1024_768 },
  80. { 1280, 720, COMM_CHG_MODE_JPEG_1280_720 },
  81. { 1280, 960, COMM_CHG_MODE_JPEG_1280_960 },
  82. { 1600, 900, COMM_CHG_MODE_JPEG_1600_900 },
  83. { 1600, 1200, COMM_CHG_MODE_JPEG_1600_1200 },
  84. { 2048, 1152, COMM_CHG_MODE_JPEG_2048_1152 },
  85. { 2048, 1536, COMM_CHG_MODE_JPEG_2048_1536 },
  86. { 2560, 1440, COMM_CHG_MODE_JPEG_2560_1440 },
  87. { 2560, 1920, COMM_CHG_MODE_JPEG_2560_1920 },
  88. { 3264, 1836, COMM_CHG_MODE_JPEG_3264_1836 },
  89. { 3264, 2176, COMM_CHG_MODE_JPEG_3264_2176 },
  90. { 3264, 2448, COMM_CHG_MODE_JPEG_3264_2448 },
  91. };
  92. static const struct s5c73m3_frame_size * const s5c73m3_resolutions[] = {
  93. [RES_ISP] = s5c73m3_isp_resolutions,
  94. [RES_JPEG] = s5c73m3_jpeg_resolutions
  95. };
  96. static const int s5c73m3_resolutions_len[] = {
  97. [RES_ISP] = ARRAY_SIZE(s5c73m3_isp_resolutions),
  98. [RES_JPEG] = ARRAY_SIZE(s5c73m3_jpeg_resolutions)
  99. };
  100. static const struct s5c73m3_interval s5c73m3_intervals[] = {
  101. { COMM_FRAME_RATE_FIXED_7FPS, {142857, 1000000}, {3264, 2448} },
  102. { COMM_FRAME_RATE_FIXED_15FPS, {66667, 1000000}, {3264, 2448} },
  103. { COMM_FRAME_RATE_FIXED_20FPS, {50000, 1000000}, {2304, 1296} },
  104. { COMM_FRAME_RATE_FIXED_30FPS, {33333, 1000000}, {2304, 1296} },
  105. };
  106. #define S5C73M3_DEFAULT_FRAME_INTERVAL 3 /* 30 fps */
  107. static void s5c73m3_fill_mbus_fmt(struct v4l2_mbus_framefmt *mf,
  108. const struct s5c73m3_frame_size *fs,
  109. u32 code)
  110. {
  111. mf->width = fs->width;
  112. mf->height = fs->height;
  113. mf->code = code;
  114. mf->colorspace = V4L2_COLORSPACE_JPEG;
  115. mf->field = V4L2_FIELD_NONE;
  116. }
  117. static int s5c73m3_i2c_write(struct i2c_client *client, u16 addr, u16 data)
  118. {
  119. u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff };
  120. int ret = i2c_master_send(client, buf, sizeof(buf));
  121. v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n",
  122. __func__, addr, data);
  123. if (ret == 4)
  124. return 0;
  125. return ret < 0 ? ret : -EREMOTEIO;
  126. }
  127. static int s5c73m3_i2c_read(struct i2c_client *client, u16 addr, u16 *data)
  128. {
  129. int ret;
  130. u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff };
  131. struct i2c_msg msg[2] = {
  132. {
  133. .addr = client->addr,
  134. .flags = 0,
  135. .len = sizeof(wbuf),
  136. .buf = wbuf
  137. }, {
  138. .addr = client->addr,
  139. .flags = I2C_M_RD,
  140. .len = sizeof(rbuf),
  141. .buf = rbuf
  142. }
  143. };
  144. /*
  145. * Issue repeated START after writing 2 address bytes and
  146. * just one STOP only after reading the data bytes.
  147. */
  148. ret = i2c_transfer(client->adapter, msg, 2);
  149. if (ret == 2) {
  150. *data = be16_to_cpup((u16 *)rbuf);
  151. v4l2_dbg(4, s5c73m3_dbg, client,
  152. "%s: addr: 0x%04x, data: 0x%04x\n",
  153. __func__, addr, *data);
  154. return 0;
  155. }
  156. v4l2_err(client, "I2C read failed: addr: %04x, (%d)\n", addr, ret);
  157. return ret >= 0 ? -EREMOTEIO : ret;
  158. }
  159. int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data)
  160. {
  161. struct i2c_client *client = state->i2c_client;
  162. int ret;
  163. if ((addr ^ state->i2c_write_address) & 0xffff0000) {
  164. ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRH, addr >> 16);
  165. if (ret < 0) {
  166. state->i2c_write_address = 0;
  167. return ret;
  168. }
  169. }
  170. if ((addr ^ state->i2c_write_address) & 0xffff) {
  171. ret = s5c73m3_i2c_write(client, REG_CMDWR_ADDRL, addr & 0xffff);
  172. if (ret < 0) {
  173. state->i2c_write_address = 0;
  174. return ret;
  175. }
  176. }
  177. state->i2c_write_address = addr;
  178. ret = s5c73m3_i2c_write(client, REG_CMDBUF_ADDR, data);
  179. if (ret < 0)
  180. return ret;
  181. state->i2c_write_address += 2;
  182. return ret;
  183. }
  184. int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data)
  185. {
  186. struct i2c_client *client = state->i2c_client;
  187. int ret;
  188. if ((addr ^ state->i2c_read_address) & 0xffff0000) {
  189. ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRH, addr >> 16);
  190. if (ret < 0) {
  191. state->i2c_read_address = 0;
  192. return ret;
  193. }
  194. }
  195. if ((addr ^ state->i2c_read_address) & 0xffff) {
  196. ret = s5c73m3_i2c_write(client, REG_CMDRD_ADDRL, addr & 0xffff);
  197. if (ret < 0) {
  198. state->i2c_read_address = 0;
  199. return ret;
  200. }
  201. }
  202. state->i2c_read_address = addr;
  203. ret = s5c73m3_i2c_read(client, REG_CMDBUF_ADDR, data);
  204. if (ret < 0)
  205. return ret;
  206. state->i2c_read_address += 2;
  207. return ret;
  208. }
  209. static int s5c73m3_check_status(struct s5c73m3 *state, unsigned int value)
  210. {
  211. unsigned long start = jiffies;
  212. unsigned long end = start + msecs_to_jiffies(2000);
  213. int ret = 0;
  214. u16 status;
  215. int count = 0;
  216. while (time_is_after_jiffies(end)) {
  217. ret = s5c73m3_read(state, REG_STATUS, &status);
  218. if (ret < 0 || status == value)
  219. break;
  220. usleep_range(500, 1000);
  221. ++count;
  222. }
  223. if (count > 0)
  224. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  225. "status check took %dms\n",
  226. jiffies_to_msecs(jiffies - start));
  227. if (ret == 0 && status != value) {
  228. u16 i2c_status = 0;
  229. u16 i2c_seq_status = 0;
  230. s5c73m3_read(state, REG_I2C_STATUS, &i2c_status);
  231. s5c73m3_read(state, REG_I2C_SEQ_STATUS, &i2c_seq_status);
  232. v4l2_err(&state->sensor_sd,
  233. "wrong status %#x, expected: %#x, i2c_status: %#x/%#x\n",
  234. status, value, i2c_status, i2c_seq_status);
  235. return -ETIMEDOUT;
  236. }
  237. return ret;
  238. }
  239. int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data)
  240. {
  241. int ret;
  242. ret = s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
  243. if (ret < 0)
  244. return ret;
  245. ret = s5c73m3_write(state, 0x00095000, command);
  246. if (ret < 0)
  247. return ret;
  248. ret = s5c73m3_write(state, 0x00095002, data);
  249. if (ret < 0)
  250. return ret;
  251. return s5c73m3_write(state, REG_STATUS, 0x0001);
  252. }
  253. static int s5c73m3_isp_comm_result(struct s5c73m3 *state, u16 command,
  254. u16 *data)
  255. {
  256. return s5c73m3_read(state, COMM_RESULT_OFFSET + command, data);
  257. }
  258. static int s5c73m3_set_af_softlanding(struct s5c73m3 *state)
  259. {
  260. unsigned long start = jiffies;
  261. u16 af_softlanding;
  262. int count = 0;
  263. int ret;
  264. const char *msg;
  265. ret = s5c73m3_isp_command(state, COMM_AF_SOFTLANDING,
  266. COMM_AF_SOFTLANDING_ON);
  267. if (ret < 0) {
  268. v4l2_info(&state->sensor_sd, "AF soft-landing failed\n");
  269. return ret;
  270. }
  271. for (;;) {
  272. ret = s5c73m3_isp_comm_result(state, COMM_AF_SOFTLANDING,
  273. &af_softlanding);
  274. if (ret < 0) {
  275. msg = "failed";
  276. break;
  277. }
  278. if (af_softlanding == COMM_AF_SOFTLANDING_RES_COMPLETE) {
  279. msg = "succeeded";
  280. break;
  281. }
  282. if (++count > 100) {
  283. ret = -ETIME;
  284. msg = "timed out";
  285. break;
  286. }
  287. msleep(25);
  288. }
  289. v4l2_info(&state->sensor_sd, "AF soft-landing %s after %dms\n",
  290. msg, jiffies_to_msecs(jiffies - start));
  291. return ret;
  292. }
  293. static int s5c73m3_load_fw(struct v4l2_subdev *sd)
  294. {
  295. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  296. struct i2c_client *client = state->i2c_client;
  297. const struct firmware *fw;
  298. int ret;
  299. char fw_name[20];
  300. snprintf(fw_name, sizeof(fw_name), "SlimISP_%.2s.bin",
  301. state->fw_file_version);
  302. ret = request_firmware(&fw, fw_name, &client->dev);
  303. if (ret < 0) {
  304. v4l2_err(sd, "Firmware request failed (%s)\n", fw_name);
  305. return -EINVAL;
  306. }
  307. v4l2_info(sd, "Loading firmware (%s, %zu B)\n", fw_name, fw->size);
  308. ret = s5c73m3_spi_write(state, fw->data, fw->size, 64);
  309. if (ret >= 0)
  310. state->isp_ready = 1;
  311. else
  312. v4l2_err(sd, "SPI write failed\n");
  313. release_firmware(fw);
  314. return ret;
  315. }
  316. static int s5c73m3_set_frame_size(struct s5c73m3 *state)
  317. {
  318. const struct s5c73m3_frame_size *prev_size =
  319. state->sensor_pix_size[RES_ISP];
  320. const struct s5c73m3_frame_size *cap_size =
  321. state->sensor_pix_size[RES_JPEG];
  322. unsigned int chg_mode;
  323. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  324. "Preview size: %dx%d, reg_val: 0x%x\n",
  325. prev_size->width, prev_size->height, prev_size->reg_val);
  326. chg_mode = prev_size->reg_val | COMM_CHG_MODE_NEW;
  327. if (state->mbus_code == S5C73M3_JPEG_FMT) {
  328. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  329. "Capture size: %dx%d, reg_val: 0x%x\n",
  330. cap_size->width, cap_size->height, cap_size->reg_val);
  331. chg_mode |= cap_size->reg_val;
  332. }
  333. return s5c73m3_isp_command(state, COMM_CHG_MODE, chg_mode);
  334. }
  335. static int s5c73m3_set_frame_rate(struct s5c73m3 *state)
  336. {
  337. int ret;
  338. if (state->ctrls.stabilization->val)
  339. return 0;
  340. if (WARN_ON(state->fiv == NULL))
  341. return -EINVAL;
  342. ret = s5c73m3_isp_command(state, COMM_FRAME_RATE, state->fiv->fps_reg);
  343. if (!ret)
  344. state->apply_fiv = 0;
  345. return ret;
  346. }
  347. static int __s5c73m3_s_stream(struct s5c73m3 *state, struct v4l2_subdev *sd,
  348. int on)
  349. {
  350. u16 mode;
  351. int ret;
  352. if (on && state->apply_fmt) {
  353. if (state->mbus_code == S5C73M3_JPEG_FMT)
  354. mode = COMM_IMG_OUTPUT_INTERLEAVED;
  355. else
  356. mode = COMM_IMG_OUTPUT_YUV;
  357. ret = s5c73m3_isp_command(state, COMM_IMG_OUTPUT, mode);
  358. if (!ret)
  359. ret = s5c73m3_set_frame_size(state);
  360. if (ret)
  361. return ret;
  362. state->apply_fmt = 0;
  363. }
  364. ret = s5c73m3_isp_command(state, COMM_SENSOR_STREAMING, !!on);
  365. if (ret)
  366. return ret;
  367. state->streaming = !!on;
  368. if (!on)
  369. return ret;
  370. if (state->apply_fiv) {
  371. ret = s5c73m3_set_frame_rate(state);
  372. if (ret < 0)
  373. v4l2_err(sd, "Error setting frame rate(%d)\n", ret);
  374. }
  375. return s5c73m3_check_status(state, REG_STATUS_ISP_COMMAND_COMPLETED);
  376. }
  377. static int s5c73m3_oif_s_stream(struct v4l2_subdev *sd, int on)
  378. {
  379. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  380. int ret;
  381. mutex_lock(&state->lock);
  382. ret = __s5c73m3_s_stream(state, sd, on);
  383. mutex_unlock(&state->lock);
  384. return ret;
  385. }
  386. static int s5c73m3_system_status_wait(struct s5c73m3 *state, u32 value,
  387. unsigned int delay, unsigned int steps)
  388. {
  389. u16 reg = 0;
  390. while (steps-- > 0) {
  391. int ret = s5c73m3_read(state, 0x30100010, &reg);
  392. if (ret < 0)
  393. return ret;
  394. if (reg == value)
  395. return 0;
  396. usleep_range(delay, delay + 25);
  397. }
  398. return -ETIMEDOUT;
  399. }
  400. static int s5c73m3_read_fw_version(struct s5c73m3 *state)
  401. {
  402. struct v4l2_subdev *sd = &state->sensor_sd;
  403. int i, ret;
  404. u16 data[2];
  405. int offset;
  406. offset = state->isp_ready ? 0x60 : 0;
  407. for (i = 0; i < S5C73M3_SENSOR_FW_LEN / 2; i++) {
  408. ret = s5c73m3_read(state, offset + i * 2, data);
  409. if (ret < 0)
  410. return ret;
  411. state->sensor_fw[i * 2] = (char)(*data & 0xff);
  412. state->sensor_fw[i * 2 + 1] = (char)(*data >> 8);
  413. }
  414. state->sensor_fw[S5C73M3_SENSOR_FW_LEN] = '\0';
  415. for (i = 0; i < S5C73M3_SENSOR_TYPE_LEN / 2; i++) {
  416. ret = s5c73m3_read(state, offset + 6 + i * 2, data);
  417. if (ret < 0)
  418. return ret;
  419. state->sensor_type[i * 2] = (char)(*data & 0xff);
  420. state->sensor_type[i * 2 + 1] = (char)(*data >> 8);
  421. }
  422. state->sensor_type[S5C73M3_SENSOR_TYPE_LEN] = '\0';
  423. ret = s5c73m3_read(state, offset + 0x14, data);
  424. if (ret >= 0) {
  425. ret = s5c73m3_read(state, offset + 0x16, data + 1);
  426. if (ret >= 0)
  427. state->fw_size = data[0] + (data[1] << 16);
  428. }
  429. v4l2_info(sd, "Sensor type: %s, FW version: %s\n",
  430. state->sensor_type, state->sensor_fw);
  431. return ret;
  432. }
  433. static int s5c73m3_fw_update_from(struct s5c73m3 *state)
  434. {
  435. struct v4l2_subdev *sd = &state->sensor_sd;
  436. u16 status = COMM_FW_UPDATE_NOT_READY;
  437. int ret;
  438. int count = 0;
  439. v4l2_warn(sd, "Updating F-ROM firmware.\n");
  440. do {
  441. if (status == COMM_FW_UPDATE_NOT_READY) {
  442. ret = s5c73m3_isp_command(state, COMM_FW_UPDATE, 0);
  443. if (ret < 0)
  444. return ret;
  445. }
  446. ret = s5c73m3_read(state, 0x00095906, &status);
  447. if (ret < 0)
  448. return ret;
  449. switch (status) {
  450. case COMM_FW_UPDATE_FAIL:
  451. v4l2_warn(sd, "Updating F-ROM firmware failed.\n");
  452. return -EIO;
  453. case COMM_FW_UPDATE_SUCCESS:
  454. v4l2_warn(sd, "Updating F-ROM firmware finished.\n");
  455. return 0;
  456. }
  457. ++count;
  458. msleep(20);
  459. } while (count < 500);
  460. v4l2_warn(sd, "Updating F-ROM firmware timed-out.\n");
  461. return -ETIMEDOUT;
  462. }
  463. static int s5c73m3_spi_boot(struct s5c73m3 *state, bool load_fw)
  464. {
  465. struct v4l2_subdev *sd = &state->sensor_sd;
  466. int ret;
  467. /* Run ARM MCU */
  468. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  469. if (ret < 0)
  470. return ret;
  471. usleep_range(400, 500);
  472. /* Check booting status */
  473. ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
  474. if (ret < 0) {
  475. v4l2_err(sd, "booting failed: %d\n", ret);
  476. return ret;
  477. }
  478. /* P,M,S and Boot Mode */
  479. ret = s5c73m3_write(state, 0x30100014, 0x2146);
  480. if (ret < 0)
  481. return ret;
  482. ret = s5c73m3_write(state, 0x30100010, 0x210c);
  483. if (ret < 0)
  484. return ret;
  485. usleep_range(200, 250);
  486. /* Check SPI status */
  487. ret = s5c73m3_system_status_wait(state, 0x210d, 100, 300);
  488. if (ret < 0)
  489. v4l2_err(sd, "SPI not ready: %d\n", ret);
  490. /* Firmware download over SPI */
  491. if (load_fw)
  492. s5c73m3_load_fw(sd);
  493. /* MCU reset */
  494. ret = s5c73m3_write(state, 0x30000004, 0xfffd);
  495. if (ret < 0)
  496. return ret;
  497. /* Remap */
  498. ret = s5c73m3_write(state, 0x301000a4, 0x0183);
  499. if (ret < 0)
  500. return ret;
  501. /* MCU restart */
  502. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  503. if (ret < 0 || !load_fw)
  504. return ret;
  505. ret = s5c73m3_read_fw_version(state);
  506. if (ret < 0)
  507. return ret;
  508. if (load_fw && update_fw) {
  509. ret = s5c73m3_fw_update_from(state);
  510. update_fw = 0;
  511. }
  512. return ret;
  513. }
  514. static int s5c73m3_set_timing_register_for_vdd(struct s5c73m3 *state)
  515. {
  516. static const u32 regs[][2] = {
  517. { 0x30100018, 0x0618 },
  518. { 0x3010001c, 0x10c1 },
  519. { 0x30100020, 0x249e }
  520. };
  521. int ret;
  522. int i;
  523. for (i = 0; i < ARRAY_SIZE(regs); i++) {
  524. ret = s5c73m3_write(state, regs[i][0], regs[i][1]);
  525. if (ret < 0)
  526. return ret;
  527. }
  528. return 0;
  529. }
  530. static void s5c73m3_set_fw_file_version(struct s5c73m3 *state)
  531. {
  532. switch (state->sensor_fw[0]) {
  533. case 'G':
  534. case 'O':
  535. state->fw_file_version[0] = 'G';
  536. break;
  537. case 'S':
  538. case 'Z':
  539. state->fw_file_version[0] = 'Z';
  540. break;
  541. }
  542. switch (state->sensor_fw[1]) {
  543. case 'C'...'F':
  544. state->fw_file_version[1] = state->sensor_fw[1];
  545. break;
  546. }
  547. }
  548. static int s5c73m3_get_fw_version(struct s5c73m3 *state)
  549. {
  550. struct v4l2_subdev *sd = &state->sensor_sd;
  551. int ret;
  552. /* Run ARM MCU */
  553. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  554. if (ret < 0)
  555. return ret;
  556. usleep_range(400, 500);
  557. /* Check booting status */
  558. ret = s5c73m3_system_status_wait(state, 0x0c, 100, 3);
  559. if (ret < 0) {
  560. v4l2_err(sd, "%s: booting failed: %d\n", __func__, ret);
  561. return ret;
  562. }
  563. /* Change I/O Driver Current in order to read from F-ROM */
  564. ret = s5c73m3_write(state, 0x30100120, 0x0820);
  565. ret = s5c73m3_write(state, 0x30100124, 0x0820);
  566. /* Offset Setting */
  567. ret = s5c73m3_write(state, 0x00010418, 0x0008);
  568. /* P,M,S and Boot Mode */
  569. ret = s5c73m3_write(state, 0x30100014, 0x2146);
  570. if (ret < 0)
  571. return ret;
  572. ret = s5c73m3_write(state, 0x30100010, 0x230c);
  573. if (ret < 0)
  574. return ret;
  575. usleep_range(200, 250);
  576. /* Check SPI status */
  577. ret = s5c73m3_system_status_wait(state, 0x230e, 100, 300);
  578. if (ret < 0)
  579. v4l2_err(sd, "SPI not ready: %d\n", ret);
  580. /* ARM reset */
  581. ret = s5c73m3_write(state, 0x30000004, 0xfffd);
  582. if (ret < 0)
  583. return ret;
  584. /* Remap */
  585. ret = s5c73m3_write(state, 0x301000a4, 0x0183);
  586. if (ret < 0)
  587. return ret;
  588. s5c73m3_set_timing_register_for_vdd(state);
  589. ret = s5c73m3_read_fw_version(state);
  590. s5c73m3_set_fw_file_version(state);
  591. return ret;
  592. }
  593. static int s5c73m3_rom_boot(struct s5c73m3 *state, bool load_fw)
  594. {
  595. static const u32 boot_regs[][2] = {
  596. { 0x3100010c, 0x0044 },
  597. { 0x31000108, 0x000d },
  598. { 0x31000304, 0x0001 },
  599. { 0x00010000, 0x5800 },
  600. { 0x00010002, 0x0002 },
  601. { 0x31000000, 0x0001 },
  602. { 0x30100014, 0x1b85 },
  603. { 0x30100010, 0x230c }
  604. };
  605. struct v4l2_subdev *sd = &state->sensor_sd;
  606. int i, ret;
  607. /* Run ARM MCU */
  608. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  609. if (ret < 0)
  610. return ret;
  611. usleep_range(400, 450);
  612. /* Check booting status */
  613. ret = s5c73m3_system_status_wait(state, 0x0c, 100, 4);
  614. if (ret < 0) {
  615. v4l2_err(sd, "Booting failed: %d\n", ret);
  616. return ret;
  617. }
  618. for (i = 0; i < ARRAY_SIZE(boot_regs); i++) {
  619. ret = s5c73m3_write(state, boot_regs[i][0], boot_regs[i][1]);
  620. if (ret < 0)
  621. return ret;
  622. }
  623. msleep(200);
  624. /* Check the binary read status */
  625. ret = s5c73m3_system_status_wait(state, 0x230e, 1000, 150);
  626. if (ret < 0) {
  627. v4l2_err(sd, "Binary read failed: %d\n", ret);
  628. return ret;
  629. }
  630. /* ARM reset */
  631. ret = s5c73m3_write(state, 0x30000004, 0xfffd);
  632. if (ret < 0)
  633. return ret;
  634. /* Remap */
  635. ret = s5c73m3_write(state, 0x301000a4, 0x0183);
  636. if (ret < 0)
  637. return ret;
  638. /* MCU re-start */
  639. ret = s5c73m3_write(state, 0x30000004, 0xffff);
  640. if (ret < 0)
  641. return ret;
  642. state->isp_ready = 1;
  643. return s5c73m3_read_fw_version(state);
  644. }
  645. static int s5c73m3_isp_init(struct s5c73m3 *state)
  646. {
  647. int ret;
  648. state->i2c_read_address = 0;
  649. state->i2c_write_address = 0;
  650. ret = s5c73m3_i2c_write(state->i2c_client, AHB_MSB_ADDR_PTR, 0x3310);
  651. if (ret < 0)
  652. return ret;
  653. if (boot_from_rom)
  654. return s5c73m3_rom_boot(state, true);
  655. else
  656. return s5c73m3_spi_boot(state, true);
  657. }
  658. static const struct s5c73m3_frame_size *s5c73m3_find_frame_size(
  659. struct v4l2_mbus_framefmt *fmt,
  660. enum s5c73m3_resolution_types idx)
  661. {
  662. const struct s5c73m3_frame_size *fs;
  663. const struct s5c73m3_frame_size *best_fs;
  664. int best_dist = INT_MAX;
  665. int i;
  666. fs = s5c73m3_resolutions[idx];
  667. best_fs = NULL;
  668. for (i = 0; i < s5c73m3_resolutions_len[idx]; ++i) {
  669. int dist = abs(fs->width - fmt->width) +
  670. abs(fs->height - fmt->height);
  671. if (dist < best_dist) {
  672. best_dist = dist;
  673. best_fs = fs;
  674. }
  675. ++fs;
  676. }
  677. return best_fs;
  678. }
  679. static void s5c73m3_oif_try_format(struct s5c73m3 *state,
  680. struct v4l2_subdev_fh *fh,
  681. struct v4l2_subdev_format *fmt,
  682. const struct s5c73m3_frame_size **fs)
  683. {
  684. u32 code;
  685. switch (fmt->pad) {
  686. case OIF_ISP_PAD:
  687. *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
  688. code = S5C73M3_ISP_FMT;
  689. break;
  690. case OIF_JPEG_PAD:
  691. *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
  692. code = S5C73M3_JPEG_FMT;
  693. break;
  694. case OIF_SOURCE_PAD:
  695. default:
  696. if (fmt->format.code == S5C73M3_JPEG_FMT)
  697. code = S5C73M3_JPEG_FMT;
  698. else
  699. code = S5C73M3_ISP_FMT;
  700. if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
  701. *fs = state->oif_pix_size[RES_ISP];
  702. else
  703. *fs = s5c73m3_find_frame_size(
  704. v4l2_subdev_get_try_format(fh,
  705. OIF_ISP_PAD),
  706. RES_ISP);
  707. break;
  708. }
  709. s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
  710. }
  711. static void s5c73m3_try_format(struct s5c73m3 *state,
  712. struct v4l2_subdev_fh *fh,
  713. struct v4l2_subdev_format *fmt,
  714. const struct s5c73m3_frame_size **fs)
  715. {
  716. u32 code;
  717. if (fmt->pad == S5C73M3_ISP_PAD) {
  718. *fs = s5c73m3_find_frame_size(&fmt->format, RES_ISP);
  719. code = S5C73M3_ISP_FMT;
  720. } else {
  721. *fs = s5c73m3_find_frame_size(&fmt->format, RES_JPEG);
  722. code = S5C73M3_JPEG_FMT;
  723. }
  724. s5c73m3_fill_mbus_fmt(&fmt->format, *fs, code);
  725. }
  726. static int s5c73m3_oif_g_frame_interval(struct v4l2_subdev *sd,
  727. struct v4l2_subdev_frame_interval *fi)
  728. {
  729. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  730. if (fi->pad != OIF_SOURCE_PAD)
  731. return -EINVAL;
  732. mutex_lock(&state->lock);
  733. fi->interval = state->fiv->interval;
  734. mutex_unlock(&state->lock);
  735. return 0;
  736. }
  737. static int __s5c73m3_set_frame_interval(struct s5c73m3 *state,
  738. struct v4l2_subdev_frame_interval *fi)
  739. {
  740. const struct s5c73m3_frame_size *prev_size =
  741. state->sensor_pix_size[RES_ISP];
  742. const struct s5c73m3_interval *fiv = &s5c73m3_intervals[0];
  743. unsigned int ret, min_err = UINT_MAX;
  744. unsigned int i, fr_time;
  745. if (fi->interval.denominator == 0)
  746. return -EINVAL;
  747. fr_time = fi->interval.numerator * 1000 / fi->interval.denominator;
  748. for (i = 0; i < ARRAY_SIZE(s5c73m3_intervals); i++) {
  749. const struct s5c73m3_interval *iv = &s5c73m3_intervals[i];
  750. if (prev_size->width > iv->size.width ||
  751. prev_size->height > iv->size.height)
  752. continue;
  753. ret = abs(iv->interval.numerator / 1000 - fr_time);
  754. if (ret < min_err) {
  755. fiv = iv;
  756. min_err = ret;
  757. }
  758. }
  759. state->fiv = fiv;
  760. v4l2_dbg(1, s5c73m3_dbg, &state->sensor_sd,
  761. "Changed frame interval to %u us\n", fiv->interval.numerator);
  762. return 0;
  763. }
  764. static int s5c73m3_oif_s_frame_interval(struct v4l2_subdev *sd,
  765. struct v4l2_subdev_frame_interval *fi)
  766. {
  767. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  768. int ret;
  769. if (fi->pad != OIF_SOURCE_PAD)
  770. return -EINVAL;
  771. v4l2_dbg(1, s5c73m3_dbg, sd, "Setting %d/%d frame interval\n",
  772. fi->interval.numerator, fi->interval.denominator);
  773. mutex_lock(&state->lock);
  774. ret = __s5c73m3_set_frame_interval(state, fi);
  775. if (!ret) {
  776. if (state->streaming)
  777. ret = s5c73m3_set_frame_rate(state);
  778. else
  779. state->apply_fiv = 1;
  780. }
  781. mutex_unlock(&state->lock);
  782. return ret;
  783. }
  784. static int s5c73m3_oif_enum_frame_interval(struct v4l2_subdev *sd,
  785. struct v4l2_subdev_fh *fh,
  786. struct v4l2_subdev_frame_interval_enum *fie)
  787. {
  788. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  789. const struct s5c73m3_interval *fi;
  790. int ret = 0;
  791. if (fie->pad != OIF_SOURCE_PAD)
  792. return -EINVAL;
  793. if (fie->index >= ARRAY_SIZE(s5c73m3_intervals))
  794. return -EINVAL;
  795. mutex_lock(&state->lock);
  796. fi = &s5c73m3_intervals[fie->index];
  797. if (fie->width > fi->size.width || fie->height > fi->size.height)
  798. ret = -EINVAL;
  799. else
  800. fie->interval = fi->interval;
  801. mutex_unlock(&state->lock);
  802. return ret;
  803. }
  804. static int s5c73m3_oif_get_pad_code(int pad, int index)
  805. {
  806. if (pad == OIF_SOURCE_PAD) {
  807. if (index > 1)
  808. return -EINVAL;
  809. return (index == 0) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
  810. }
  811. if (index > 0)
  812. return -EINVAL;
  813. return (pad == OIF_ISP_PAD) ? S5C73M3_ISP_FMT : S5C73M3_JPEG_FMT;
  814. }
  815. static int s5c73m3_get_fmt(struct v4l2_subdev *sd,
  816. struct v4l2_subdev_fh *fh,
  817. struct v4l2_subdev_format *fmt)
  818. {
  819. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  820. const struct s5c73m3_frame_size *fs;
  821. u32 code;
  822. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  823. fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
  824. return 0;
  825. }
  826. mutex_lock(&state->lock);
  827. switch (fmt->pad) {
  828. case S5C73M3_ISP_PAD:
  829. code = S5C73M3_ISP_FMT;
  830. fs = state->sensor_pix_size[RES_ISP];
  831. break;
  832. case S5C73M3_JPEG_PAD:
  833. code = S5C73M3_JPEG_FMT;
  834. fs = state->sensor_pix_size[RES_JPEG];
  835. break;
  836. default:
  837. mutex_unlock(&state->lock);
  838. return -EINVAL;
  839. }
  840. s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
  841. mutex_unlock(&state->lock);
  842. return 0;
  843. }
  844. static int s5c73m3_oif_get_fmt(struct v4l2_subdev *sd,
  845. struct v4l2_subdev_fh *fh,
  846. struct v4l2_subdev_format *fmt)
  847. {
  848. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  849. const struct s5c73m3_frame_size *fs;
  850. u32 code;
  851. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  852. fmt->format = *v4l2_subdev_get_try_format(fh, fmt->pad);
  853. return 0;
  854. }
  855. mutex_lock(&state->lock);
  856. switch (fmt->pad) {
  857. case OIF_ISP_PAD:
  858. code = S5C73M3_ISP_FMT;
  859. fs = state->oif_pix_size[RES_ISP];
  860. break;
  861. case OIF_JPEG_PAD:
  862. code = S5C73M3_JPEG_FMT;
  863. fs = state->oif_pix_size[RES_JPEG];
  864. break;
  865. case OIF_SOURCE_PAD:
  866. code = state->mbus_code;
  867. fs = state->oif_pix_size[RES_ISP];
  868. break;
  869. default:
  870. mutex_unlock(&state->lock);
  871. return -EINVAL;
  872. }
  873. s5c73m3_fill_mbus_fmt(&fmt->format, fs, code);
  874. mutex_unlock(&state->lock);
  875. return 0;
  876. }
  877. static int s5c73m3_set_fmt(struct v4l2_subdev *sd,
  878. struct v4l2_subdev_fh *fh,
  879. struct v4l2_subdev_format *fmt)
  880. {
  881. const struct s5c73m3_frame_size *frame_size = NULL;
  882. struct s5c73m3 *state = sensor_sd_to_s5c73m3(sd);
  883. struct v4l2_mbus_framefmt *mf;
  884. int ret = 0;
  885. mutex_lock(&state->lock);
  886. s5c73m3_try_format(state, fh, fmt, &frame_size);
  887. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  888. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  889. *mf = fmt->format;
  890. } else {
  891. switch (fmt->pad) {
  892. case S5C73M3_ISP_PAD:
  893. state->sensor_pix_size[RES_ISP] = frame_size;
  894. break;
  895. case S5C73M3_JPEG_PAD:
  896. state->sensor_pix_size[RES_JPEG] = frame_size;
  897. break;
  898. default:
  899. ret = -EBUSY;
  900. }
  901. if (state->streaming)
  902. ret = -EBUSY;
  903. else
  904. state->apply_fmt = 1;
  905. }
  906. mutex_unlock(&state->lock);
  907. return ret;
  908. }
  909. static int s5c73m3_oif_set_fmt(struct v4l2_subdev *sd,
  910. struct v4l2_subdev_fh *fh,
  911. struct v4l2_subdev_format *fmt)
  912. {
  913. const struct s5c73m3_frame_size *frame_size = NULL;
  914. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  915. struct v4l2_mbus_framefmt *mf;
  916. int ret = 0;
  917. mutex_lock(&state->lock);
  918. s5c73m3_oif_try_format(state, fh, fmt, &frame_size);
  919. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  920. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  921. *mf = fmt->format;
  922. if (fmt->pad == OIF_ISP_PAD) {
  923. mf = v4l2_subdev_get_try_format(fh, OIF_SOURCE_PAD);
  924. mf->width = fmt->format.width;
  925. mf->height = fmt->format.height;
  926. }
  927. } else {
  928. switch (fmt->pad) {
  929. case OIF_ISP_PAD:
  930. state->oif_pix_size[RES_ISP] = frame_size;
  931. break;
  932. case OIF_JPEG_PAD:
  933. state->oif_pix_size[RES_JPEG] = frame_size;
  934. break;
  935. case OIF_SOURCE_PAD:
  936. state->mbus_code = fmt->format.code;
  937. break;
  938. default:
  939. ret = -EBUSY;
  940. }
  941. if (state->streaming)
  942. ret = -EBUSY;
  943. else
  944. state->apply_fmt = 1;
  945. }
  946. mutex_unlock(&state->lock);
  947. return ret;
  948. }
  949. static int s5c73m3_oif_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
  950. struct v4l2_mbus_frame_desc *fd)
  951. {
  952. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  953. int i;
  954. if (pad != OIF_SOURCE_PAD || fd == NULL)
  955. return -EINVAL;
  956. mutex_lock(&state->lock);
  957. fd->num_entries = 2;
  958. for (i = 0; i < fd->num_entries; i++)
  959. fd->entry[i] = state->frame_desc.entry[i];
  960. mutex_unlock(&state->lock);
  961. return 0;
  962. }
  963. static int s5c73m3_oif_set_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
  964. struct v4l2_mbus_frame_desc *fd)
  965. {
  966. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  967. struct v4l2_mbus_frame_desc *frame_desc = &state->frame_desc;
  968. int i;
  969. if (pad != OIF_SOURCE_PAD || fd == NULL)
  970. return -EINVAL;
  971. fd->entry[0].length = 10 * SZ_1M;
  972. fd->entry[1].length = max_t(u32, fd->entry[1].length,
  973. S5C73M3_EMBEDDED_DATA_MAXLEN);
  974. fd->num_entries = 2;
  975. mutex_lock(&state->lock);
  976. for (i = 0; i < fd->num_entries; i++)
  977. frame_desc->entry[i] = fd->entry[i];
  978. mutex_unlock(&state->lock);
  979. return 0;
  980. }
  981. static int s5c73m3_enum_mbus_code(struct v4l2_subdev *sd,
  982. struct v4l2_subdev_fh *fh,
  983. struct v4l2_subdev_mbus_code_enum *code)
  984. {
  985. static const int codes[] = {
  986. [S5C73M3_ISP_PAD] = S5C73M3_ISP_FMT,
  987. [S5C73M3_JPEG_PAD] = S5C73M3_JPEG_FMT};
  988. if (code->index > 0 || code->pad >= S5C73M3_NUM_PADS)
  989. return -EINVAL;
  990. code->code = codes[code->pad];
  991. return 0;
  992. }
  993. static int s5c73m3_oif_enum_mbus_code(struct v4l2_subdev *sd,
  994. struct v4l2_subdev_fh *fh,
  995. struct v4l2_subdev_mbus_code_enum *code)
  996. {
  997. int ret;
  998. ret = s5c73m3_oif_get_pad_code(code->pad, code->index);
  999. if (ret < 0)
  1000. return ret;
  1001. code->code = ret;
  1002. return 0;
  1003. }
  1004. static int s5c73m3_enum_frame_size(struct v4l2_subdev *sd,
  1005. struct v4l2_subdev_fh *fh,
  1006. struct v4l2_subdev_frame_size_enum *fse)
  1007. {
  1008. int idx;
  1009. if (fse->pad == S5C73M3_ISP_PAD) {
  1010. if (fse->code != S5C73M3_ISP_FMT)
  1011. return -EINVAL;
  1012. idx = RES_ISP;
  1013. } else{
  1014. if (fse->code != S5C73M3_JPEG_FMT)
  1015. return -EINVAL;
  1016. idx = RES_JPEG;
  1017. }
  1018. if (fse->index >= s5c73m3_resolutions_len[idx])
  1019. return -EINVAL;
  1020. fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
  1021. fse->max_width = fse->min_width;
  1022. fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
  1023. fse->min_height = fse->max_height;
  1024. return 0;
  1025. }
  1026. static int s5c73m3_oif_enum_frame_size(struct v4l2_subdev *sd,
  1027. struct v4l2_subdev_fh *fh,
  1028. struct v4l2_subdev_frame_size_enum *fse)
  1029. {
  1030. int idx;
  1031. if (fse->pad == OIF_SOURCE_PAD) {
  1032. if (fse->index > 0)
  1033. return -EINVAL;
  1034. switch (fse->code) {
  1035. case S5C73M3_JPEG_FMT:
  1036. case S5C73M3_ISP_FMT: {
  1037. struct v4l2_mbus_framefmt *mf =
  1038. v4l2_subdev_get_try_format(fh, OIF_ISP_PAD);
  1039. fse->max_width = fse->min_width = mf->width;
  1040. fse->max_height = fse->min_height = mf->height;
  1041. return 0;
  1042. }
  1043. default:
  1044. return -EINVAL;
  1045. }
  1046. }
  1047. if (fse->code != s5c73m3_oif_get_pad_code(fse->pad, 0))
  1048. return -EINVAL;
  1049. if (fse->pad == OIF_JPEG_PAD)
  1050. idx = RES_JPEG;
  1051. else
  1052. idx = RES_ISP;
  1053. if (fse->index >= s5c73m3_resolutions_len[idx])
  1054. return -EINVAL;
  1055. fse->min_width = s5c73m3_resolutions[idx][fse->index].width;
  1056. fse->max_width = fse->min_width;
  1057. fse->max_height = s5c73m3_resolutions[idx][fse->index].height;
  1058. fse->min_height = fse->max_height;
  1059. return 0;
  1060. }
  1061. static int s5c73m3_oif_log_status(struct v4l2_subdev *sd)
  1062. {
  1063. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1064. v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
  1065. v4l2_info(sd, "power: %d, apply_fmt: %d\n", state->power,
  1066. state->apply_fmt);
  1067. return 0;
  1068. }
  1069. static int s5c73m3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1070. {
  1071. struct v4l2_mbus_framefmt *mf;
  1072. mf = v4l2_subdev_get_try_format(fh, S5C73M3_ISP_PAD);
  1073. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
  1074. S5C73M3_ISP_FMT);
  1075. mf = v4l2_subdev_get_try_format(fh, S5C73M3_JPEG_PAD);
  1076. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
  1077. S5C73M3_JPEG_FMT);
  1078. return 0;
  1079. }
  1080. static int s5c73m3_oif_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
  1081. {
  1082. struct v4l2_mbus_framefmt *mf;
  1083. mf = v4l2_subdev_get_try_format(fh, OIF_ISP_PAD);
  1084. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
  1085. S5C73M3_ISP_FMT);
  1086. mf = v4l2_subdev_get_try_format(fh, OIF_JPEG_PAD);
  1087. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_jpeg_resolutions[1],
  1088. S5C73M3_JPEG_FMT);
  1089. mf = v4l2_subdev_get_try_format(fh, OIF_SOURCE_PAD);
  1090. s5c73m3_fill_mbus_fmt(mf, &s5c73m3_isp_resolutions[1],
  1091. S5C73M3_ISP_FMT);
  1092. return 0;
  1093. }
  1094. static int s5c73m3_gpio_set_value(struct s5c73m3 *priv, int id, u32 val)
  1095. {
  1096. if (!gpio_is_valid(priv->gpio[id].gpio))
  1097. return 0;
  1098. gpio_set_value(priv->gpio[id].gpio, !!val);
  1099. return 1;
  1100. }
  1101. static int s5c73m3_gpio_assert(struct s5c73m3 *priv, int id)
  1102. {
  1103. return s5c73m3_gpio_set_value(priv, id, priv->gpio[id].level);
  1104. }
  1105. static int s5c73m3_gpio_deassert(struct s5c73m3 *priv, int id)
  1106. {
  1107. return s5c73m3_gpio_set_value(priv, id, !priv->gpio[id].level);
  1108. }
  1109. static int __s5c73m3_power_on(struct s5c73m3 *state)
  1110. {
  1111. int i, ret;
  1112. for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++) {
  1113. ret = regulator_enable(state->supplies[i].consumer);
  1114. if (ret)
  1115. goto err_reg_dis;
  1116. }
  1117. ret = clk_set_rate(state->clock, state->mclk_frequency);
  1118. if (ret < 0)
  1119. goto err_reg_dis;
  1120. ret = clk_prepare_enable(state->clock);
  1121. if (ret < 0)
  1122. goto err_reg_dis;
  1123. v4l2_dbg(1, s5c73m3_dbg, &state->oif_sd, "clock frequency: %ld\n",
  1124. clk_get_rate(state->clock));
  1125. s5c73m3_gpio_deassert(state, STBY);
  1126. usleep_range(100, 200);
  1127. s5c73m3_gpio_deassert(state, RST);
  1128. usleep_range(50, 100);
  1129. return 0;
  1130. err_reg_dis:
  1131. for (--i; i >= 0; i--)
  1132. regulator_disable(state->supplies[i].consumer);
  1133. return ret;
  1134. }
  1135. static int __s5c73m3_power_off(struct s5c73m3 *state)
  1136. {
  1137. int i, ret;
  1138. if (s5c73m3_gpio_assert(state, RST))
  1139. usleep_range(10, 50);
  1140. if (s5c73m3_gpio_assert(state, STBY))
  1141. usleep_range(100, 200);
  1142. clk_disable_unprepare(state->clock);
  1143. state->streaming = 0;
  1144. state->isp_ready = 0;
  1145. for (i = S5C73M3_MAX_SUPPLIES - 1; i >= 0; i--) {
  1146. ret = regulator_disable(state->supplies[i].consumer);
  1147. if (ret)
  1148. goto err;
  1149. }
  1150. return 0;
  1151. err:
  1152. for (++i; i < S5C73M3_MAX_SUPPLIES; i++) {
  1153. int r = regulator_enable(state->supplies[i].consumer);
  1154. if (r < 0)
  1155. v4l2_err(&state->oif_sd, "Failed to reenable %s: %d\n",
  1156. state->supplies[i].supply, r);
  1157. }
  1158. clk_prepare_enable(state->clock);
  1159. return ret;
  1160. }
  1161. static int s5c73m3_oif_set_power(struct v4l2_subdev *sd, int on)
  1162. {
  1163. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1164. int ret = 0;
  1165. mutex_lock(&state->lock);
  1166. if (on && !state->power) {
  1167. ret = __s5c73m3_power_on(state);
  1168. if (!ret)
  1169. ret = s5c73m3_isp_init(state);
  1170. if (!ret) {
  1171. state->apply_fiv = 1;
  1172. state->apply_fmt = 1;
  1173. }
  1174. } else if (!on == state->power) {
  1175. ret = s5c73m3_set_af_softlanding(state);
  1176. if (!ret)
  1177. ret = __s5c73m3_power_off(state);
  1178. else
  1179. v4l2_err(sd, "Soft landing lens failed\n");
  1180. }
  1181. if (!ret)
  1182. state->power += on ? 1 : -1;
  1183. v4l2_dbg(1, s5c73m3_dbg, sd, "%s: power: %d\n",
  1184. __func__, state->power);
  1185. mutex_unlock(&state->lock);
  1186. return ret;
  1187. }
  1188. static int s5c73m3_oif_registered(struct v4l2_subdev *sd)
  1189. {
  1190. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1191. int ret;
  1192. ret = v4l2_device_register_subdev(sd->v4l2_dev, &state->sensor_sd);
  1193. if (ret) {
  1194. v4l2_err(sd->v4l2_dev, "Failed to register %s\n",
  1195. state->oif_sd.name);
  1196. return ret;
  1197. }
  1198. ret = media_entity_create_link(&state->sensor_sd.entity,
  1199. S5C73M3_ISP_PAD, &state->oif_sd.entity, OIF_ISP_PAD,
  1200. MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
  1201. ret = media_entity_create_link(&state->sensor_sd.entity,
  1202. S5C73M3_JPEG_PAD, &state->oif_sd.entity, OIF_JPEG_PAD,
  1203. MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED);
  1204. return ret;
  1205. }
  1206. static void s5c73m3_oif_unregistered(struct v4l2_subdev *sd)
  1207. {
  1208. struct s5c73m3 *state = oif_sd_to_s5c73m3(sd);
  1209. v4l2_device_unregister_subdev(&state->sensor_sd);
  1210. }
  1211. static const struct v4l2_subdev_internal_ops s5c73m3_internal_ops = {
  1212. .open = s5c73m3_open,
  1213. };
  1214. static const struct v4l2_subdev_pad_ops s5c73m3_pad_ops = {
  1215. .enum_mbus_code = s5c73m3_enum_mbus_code,
  1216. .enum_frame_size = s5c73m3_enum_frame_size,
  1217. .get_fmt = s5c73m3_get_fmt,
  1218. .set_fmt = s5c73m3_set_fmt,
  1219. };
  1220. static const struct v4l2_subdev_ops s5c73m3_subdev_ops = {
  1221. .pad = &s5c73m3_pad_ops,
  1222. };
  1223. static const struct v4l2_subdev_internal_ops oif_internal_ops = {
  1224. .registered = s5c73m3_oif_registered,
  1225. .unregistered = s5c73m3_oif_unregistered,
  1226. .open = s5c73m3_oif_open,
  1227. };
  1228. static const struct v4l2_subdev_pad_ops s5c73m3_oif_pad_ops = {
  1229. .enum_mbus_code = s5c73m3_oif_enum_mbus_code,
  1230. .enum_frame_size = s5c73m3_oif_enum_frame_size,
  1231. .enum_frame_interval = s5c73m3_oif_enum_frame_interval,
  1232. .get_fmt = s5c73m3_oif_get_fmt,
  1233. .set_fmt = s5c73m3_oif_set_fmt,
  1234. .get_frame_desc = s5c73m3_oif_get_frame_desc,
  1235. .set_frame_desc = s5c73m3_oif_set_frame_desc,
  1236. };
  1237. static const struct v4l2_subdev_core_ops s5c73m3_oif_core_ops = {
  1238. .s_power = s5c73m3_oif_set_power,
  1239. .log_status = s5c73m3_oif_log_status,
  1240. };
  1241. static const struct v4l2_subdev_video_ops s5c73m3_oif_video_ops = {
  1242. .s_stream = s5c73m3_oif_s_stream,
  1243. .g_frame_interval = s5c73m3_oif_g_frame_interval,
  1244. .s_frame_interval = s5c73m3_oif_s_frame_interval,
  1245. };
  1246. static const struct v4l2_subdev_ops oif_subdev_ops = {
  1247. .core = &s5c73m3_oif_core_ops,
  1248. .pad = &s5c73m3_oif_pad_ops,
  1249. .video = &s5c73m3_oif_video_ops,
  1250. };
  1251. static int s5c73m3_configure_gpios(struct s5c73m3 *state)
  1252. {
  1253. static const char * const gpio_names[] = {
  1254. "S5C73M3_STBY", "S5C73M3_RST"
  1255. };
  1256. struct i2c_client *c = state->i2c_client;
  1257. struct s5c73m3_gpio *g = state->gpio;
  1258. int ret, i;
  1259. for (i = 0; i < GPIO_NUM; ++i) {
  1260. unsigned int flags = GPIOF_DIR_OUT;
  1261. if (g[i].level)
  1262. flags |= GPIOF_INIT_HIGH;
  1263. ret = devm_gpio_request_one(&c->dev, g[i].gpio, flags,
  1264. gpio_names[i]);
  1265. if (ret) {
  1266. v4l2_err(c, "failed to request gpio %s\n",
  1267. gpio_names[i]);
  1268. return ret;
  1269. }
  1270. }
  1271. return 0;
  1272. }
  1273. static int s5c73m3_parse_gpios(struct s5c73m3 *state)
  1274. {
  1275. static const char * const prop_names[] = {
  1276. "standby-gpios", "xshutdown-gpios",
  1277. };
  1278. struct device *dev = &state->i2c_client->dev;
  1279. struct device_node *node = dev->of_node;
  1280. int ret, i;
  1281. for (i = 0; i < GPIO_NUM; ++i) {
  1282. enum of_gpio_flags of_flags;
  1283. ret = of_get_named_gpio_flags(node, prop_names[i],
  1284. 0, &of_flags);
  1285. if (ret < 0) {
  1286. dev_err(dev, "failed to parse %s DT property\n",
  1287. prop_names[i]);
  1288. return -EINVAL;
  1289. }
  1290. state->gpio[i].gpio = ret;
  1291. state->gpio[i].level = !(of_flags & OF_GPIO_ACTIVE_LOW);
  1292. }
  1293. return 0;
  1294. }
  1295. static int s5c73m3_get_platform_data(struct s5c73m3 *state)
  1296. {
  1297. struct device *dev = &state->i2c_client->dev;
  1298. const struct s5c73m3_platform_data *pdata = dev->platform_data;
  1299. struct device_node *node = dev->of_node;
  1300. struct device_node *node_ep;
  1301. struct v4l2_of_endpoint ep;
  1302. int ret;
  1303. if (!node) {
  1304. if (!pdata) {
  1305. dev_err(dev, "Platform data not specified\n");
  1306. return -EINVAL;
  1307. }
  1308. state->mclk_frequency = pdata->mclk_frequency;
  1309. state->gpio[STBY] = pdata->gpio_stby;
  1310. state->gpio[RST] = pdata->gpio_reset;
  1311. return 0;
  1312. }
  1313. state->clock = devm_clk_get(dev, S5C73M3_CLK_NAME);
  1314. if (IS_ERR(state->clock))
  1315. return PTR_ERR(state->clock);
  1316. if (of_property_read_u32(node, "clock-frequency",
  1317. &state->mclk_frequency)) {
  1318. state->mclk_frequency = S5C73M3_DEFAULT_MCLK_FREQ;
  1319. dev_info(dev, "using default %u Hz clock frequency\n",
  1320. state->mclk_frequency);
  1321. }
  1322. ret = s5c73m3_parse_gpios(state);
  1323. if (ret < 0)
  1324. return -EINVAL;
  1325. node_ep = of_graph_get_next_endpoint(node, NULL);
  1326. if (!node_ep) {
  1327. dev_warn(dev, "no endpoint defined for node: %s\n",
  1328. node->full_name);
  1329. return 0;
  1330. }
  1331. v4l2_of_parse_endpoint(node_ep, &ep);
  1332. of_node_put(node_ep);
  1333. if (ep.bus_type != V4L2_MBUS_CSI2) {
  1334. dev_err(dev, "unsupported bus type\n");
  1335. return -EINVAL;
  1336. }
  1337. /*
  1338. * Number of MIPI CSI-2 data lanes is currently not configurable,
  1339. * always a default value of 4 lanes is used.
  1340. */
  1341. if (ep.bus.mipi_csi2.num_data_lanes != S5C73M3_MIPI_DATA_LANES)
  1342. dev_info(dev, "falling back to 4 MIPI CSI-2 data lanes\n");
  1343. return 0;
  1344. }
  1345. static int s5c73m3_probe(struct i2c_client *client,
  1346. const struct i2c_device_id *id)
  1347. {
  1348. struct device *dev = &client->dev;
  1349. struct v4l2_subdev *sd;
  1350. struct v4l2_subdev *oif_sd;
  1351. struct s5c73m3 *state;
  1352. int ret, i;
  1353. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  1354. if (!state)
  1355. return -ENOMEM;
  1356. state->i2c_client = client;
  1357. ret = s5c73m3_get_platform_data(state);
  1358. if (ret < 0)
  1359. return ret;
  1360. mutex_init(&state->lock);
  1361. sd = &state->sensor_sd;
  1362. oif_sd = &state->oif_sd;
  1363. v4l2_subdev_init(sd, &s5c73m3_subdev_ops);
  1364. sd->owner = client->dev.driver->owner;
  1365. v4l2_set_subdevdata(sd, state);
  1366. strlcpy(sd->name, "S5C73M3", sizeof(sd->name));
  1367. sd->internal_ops = &s5c73m3_internal_ops;
  1368. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1369. state->sensor_pads[S5C73M3_JPEG_PAD].flags = MEDIA_PAD_FL_SOURCE;
  1370. state->sensor_pads[S5C73M3_ISP_PAD].flags = MEDIA_PAD_FL_SOURCE;
  1371. sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
  1372. ret = media_entity_init(&sd->entity, S5C73M3_NUM_PADS,
  1373. state->sensor_pads, 0);
  1374. if (ret < 0)
  1375. return ret;
  1376. v4l2_i2c_subdev_init(oif_sd, client, &oif_subdev_ops);
  1377. strcpy(oif_sd->name, "S5C73M3-OIF");
  1378. oif_sd->internal_ops = &oif_internal_ops;
  1379. oif_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1380. state->oif_pads[OIF_ISP_PAD].flags = MEDIA_PAD_FL_SINK;
  1381. state->oif_pads[OIF_JPEG_PAD].flags = MEDIA_PAD_FL_SINK;
  1382. state->oif_pads[OIF_SOURCE_PAD].flags = MEDIA_PAD_FL_SOURCE;
  1383. oif_sd->entity.type = MEDIA_ENT_T_V4L2_SUBDEV;
  1384. ret = media_entity_init(&oif_sd->entity, OIF_NUM_PADS,
  1385. state->oif_pads, 0);
  1386. if (ret < 0)
  1387. return ret;
  1388. ret = s5c73m3_configure_gpios(state);
  1389. if (ret)
  1390. goto out_err;
  1391. for (i = 0; i < S5C73M3_MAX_SUPPLIES; i++)
  1392. state->supplies[i].supply = s5c73m3_supply_names[i];
  1393. ret = devm_regulator_bulk_get(dev, S5C73M3_MAX_SUPPLIES,
  1394. state->supplies);
  1395. if (ret) {
  1396. dev_err(dev, "failed to get regulators\n");
  1397. goto out_err;
  1398. }
  1399. ret = s5c73m3_init_controls(state);
  1400. if (ret)
  1401. goto out_err;
  1402. state->sensor_pix_size[RES_ISP] = &s5c73m3_isp_resolutions[1];
  1403. state->sensor_pix_size[RES_JPEG] = &s5c73m3_jpeg_resolutions[1];
  1404. state->oif_pix_size[RES_ISP] = state->sensor_pix_size[RES_ISP];
  1405. state->oif_pix_size[RES_JPEG] = state->sensor_pix_size[RES_JPEG];
  1406. state->mbus_code = S5C73M3_ISP_FMT;
  1407. state->fiv = &s5c73m3_intervals[S5C73M3_DEFAULT_FRAME_INTERVAL];
  1408. state->fw_file_version[0] = 'G';
  1409. state->fw_file_version[1] = 'C';
  1410. ret = s5c73m3_register_spi_driver(state);
  1411. if (ret < 0)
  1412. goto out_err;
  1413. oif_sd->dev = dev;
  1414. ret = __s5c73m3_power_on(state);
  1415. if (ret < 0)
  1416. goto out_err1;
  1417. ret = s5c73m3_get_fw_version(state);
  1418. __s5c73m3_power_off(state);
  1419. if (ret < 0) {
  1420. dev_err(dev, "Device detection failed: %d\n", ret);
  1421. goto out_err1;
  1422. }
  1423. ret = v4l2_async_register_subdev(oif_sd);
  1424. if (ret < 0)
  1425. goto out_err1;
  1426. v4l2_info(sd, "%s: completed successfully\n", __func__);
  1427. return 0;
  1428. out_err1:
  1429. s5c73m3_unregister_spi_driver(state);
  1430. out_err:
  1431. media_entity_cleanup(&sd->entity);
  1432. return ret;
  1433. }
  1434. static int s5c73m3_remove(struct i2c_client *client)
  1435. {
  1436. struct v4l2_subdev *oif_sd = i2c_get_clientdata(client);
  1437. struct s5c73m3 *state = oif_sd_to_s5c73m3(oif_sd);
  1438. struct v4l2_subdev *sensor_sd = &state->sensor_sd;
  1439. v4l2_async_unregister_subdev(oif_sd);
  1440. v4l2_ctrl_handler_free(oif_sd->ctrl_handler);
  1441. media_entity_cleanup(&oif_sd->entity);
  1442. v4l2_device_unregister_subdev(sensor_sd);
  1443. media_entity_cleanup(&sensor_sd->entity);
  1444. s5c73m3_unregister_spi_driver(state);
  1445. return 0;
  1446. }
  1447. static const struct i2c_device_id s5c73m3_id[] = {
  1448. { DRIVER_NAME, 0 },
  1449. { }
  1450. };
  1451. MODULE_DEVICE_TABLE(i2c, s5c73m3_id);
  1452. #ifdef CONFIG_OF
  1453. static const struct of_device_id s5c73m3_of_match[] = {
  1454. { .compatible = "samsung,s5c73m3" },
  1455. { }
  1456. };
  1457. MODULE_DEVICE_TABLE(of, s5c73m3_of_match);
  1458. #endif
  1459. static struct i2c_driver s5c73m3_i2c_driver = {
  1460. .driver = {
  1461. .of_match_table = of_match_ptr(s5c73m3_of_match),
  1462. .name = DRIVER_NAME,
  1463. },
  1464. .probe = s5c73m3_probe,
  1465. .remove = s5c73m3_remove,
  1466. .id_table = s5c73m3_id,
  1467. };
  1468. module_i2c_driver(s5c73m3_i2c_driver);
  1469. MODULE_DESCRIPTION("Samsung S5C73M3 camera driver");
  1470. MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
  1471. MODULE_LICENSE("GPL");