irq-mtk-sysirq.c 4.2 KB

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  1. /*
  2. * Copyright (c) 2014 MediaTek Inc.
  3. * Author: Joe.C <yingjoe.chen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <linux/irq.h>
  15. #include <linux/irqdomain.h>
  16. #include <linux/of.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/of_address.h>
  19. #include <linux/io.h>
  20. #include <linux/slab.h>
  21. #include <linux/spinlock.h>
  22. #include "irqchip.h"
  23. #define MT6577_SYS_INTPOL_NUM (224)
  24. struct mtk_sysirq_chip_data {
  25. spinlock_t lock;
  26. void __iomem *intpol_base;
  27. };
  28. static int mtk_sysirq_set_type(struct irq_data *data, unsigned int type)
  29. {
  30. irq_hw_number_t hwirq = data->hwirq;
  31. struct mtk_sysirq_chip_data *chip_data = data->chip_data;
  32. u32 offset, reg_index, value;
  33. unsigned long flags;
  34. int ret;
  35. offset = hwirq & 0x1f;
  36. reg_index = hwirq >> 5;
  37. spin_lock_irqsave(&chip_data->lock, flags);
  38. value = readl_relaxed(chip_data->intpol_base + reg_index * 4);
  39. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_EDGE_FALLING) {
  40. if (type == IRQ_TYPE_LEVEL_LOW)
  41. type = IRQ_TYPE_LEVEL_HIGH;
  42. else
  43. type = IRQ_TYPE_EDGE_RISING;
  44. value |= (1 << offset);
  45. } else {
  46. value &= ~(1 << offset);
  47. }
  48. writel(value, chip_data->intpol_base + reg_index * 4);
  49. data = data->parent_data;
  50. ret = data->chip->irq_set_type(data, type);
  51. spin_unlock_irqrestore(&chip_data->lock, flags);
  52. return ret;
  53. }
  54. static struct irq_chip mtk_sysirq_chip = {
  55. .name = "MT_SYSIRQ",
  56. .irq_mask = irq_chip_mask_parent,
  57. .irq_unmask = irq_chip_unmask_parent,
  58. .irq_eoi = irq_chip_eoi_parent,
  59. .irq_set_type = mtk_sysirq_set_type,
  60. .irq_retrigger = irq_chip_retrigger_hierarchy,
  61. .irq_set_affinity = irq_chip_set_affinity_parent,
  62. };
  63. static int mtk_sysirq_domain_xlate(struct irq_domain *d,
  64. struct device_node *controller,
  65. const u32 *intspec, unsigned int intsize,
  66. unsigned long *out_hwirq,
  67. unsigned int *out_type)
  68. {
  69. if (intsize != 3)
  70. return -EINVAL;
  71. /* sysirq doesn't support PPI */
  72. if (intspec[0])
  73. return -EINVAL;
  74. *out_hwirq = intspec[1];
  75. *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
  76. return 0;
  77. }
  78. static int mtk_sysirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
  79. unsigned int nr_irqs, void *arg)
  80. {
  81. int i;
  82. irq_hw_number_t hwirq;
  83. struct of_phandle_args *irq_data = arg;
  84. struct of_phandle_args gic_data = *irq_data;
  85. if (irq_data->args_count != 3)
  86. return -EINVAL;
  87. /* sysirq doesn't support PPI */
  88. if (irq_data->args[0])
  89. return -EINVAL;
  90. hwirq = irq_data->args[1];
  91. for (i = 0; i < nr_irqs; i++)
  92. irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
  93. &mtk_sysirq_chip,
  94. domain->host_data);
  95. gic_data.np = domain->parent->of_node;
  96. return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &gic_data);
  97. }
  98. static struct irq_domain_ops sysirq_domain_ops = {
  99. .xlate = mtk_sysirq_domain_xlate,
  100. .alloc = mtk_sysirq_domain_alloc,
  101. .free = irq_domain_free_irqs_common,
  102. };
  103. static int __init mtk_sysirq_of_init(struct device_node *node,
  104. struct device_node *parent)
  105. {
  106. struct irq_domain *domain, *domain_parent;
  107. struct mtk_sysirq_chip_data *chip_data;
  108. int ret = 0;
  109. domain_parent = irq_find_host(parent);
  110. if (!domain_parent) {
  111. pr_err("mtk_sysirq: interrupt-parent not found\n");
  112. return -EINVAL;
  113. }
  114. chip_data = kzalloc(sizeof(*chip_data), GFP_KERNEL);
  115. if (!chip_data)
  116. return -ENOMEM;
  117. chip_data->intpol_base = of_io_request_and_map(node, 0, "intpol");
  118. if (IS_ERR(chip_data->intpol_base)) {
  119. pr_err("mtk_sysirq: unable to map sysirq register\n");
  120. ret = PTR_ERR(chip_data->intpol_base);
  121. goto out_free;
  122. }
  123. domain = irq_domain_add_hierarchy(domain_parent, 0,
  124. MT6577_SYS_INTPOL_NUM, node,
  125. &sysirq_domain_ops, chip_data);
  126. if (!domain) {
  127. ret = -ENOMEM;
  128. goto out_unmap;
  129. }
  130. spin_lock_init(&chip_data->lock);
  131. return 0;
  132. out_unmap:
  133. iounmap(chip_data->intpol_base);
  134. out_free:
  135. kfree(chip_data);
  136. return ret;
  137. }
  138. IRQCHIP_DECLARE(mtk_sysirq, "mediatek,mt6577-sysirq", mtk_sysirq_of_init);