device.c 42 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include <linux/moduleparam.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/vmalloc.h>
  36. #include <linux/math64.h>
  37. #include <rdma/ib_verbs.h>
  38. #include "iw_cxgb4.h"
  39. #define DRV_VERSION "0.1"
  40. MODULE_AUTHOR("Steve Wise");
  41. MODULE_DESCRIPTION("Chelsio T4/T5 RDMA Driver");
  42. MODULE_LICENSE("Dual BSD/GPL");
  43. MODULE_VERSION(DRV_VERSION);
  44. static int allow_db_fc_on_t5;
  45. module_param(allow_db_fc_on_t5, int, 0644);
  46. MODULE_PARM_DESC(allow_db_fc_on_t5,
  47. "Allow DB Flow Control on T5 (default = 0)");
  48. static int allow_db_coalescing_on_t5;
  49. module_param(allow_db_coalescing_on_t5, int, 0644);
  50. MODULE_PARM_DESC(allow_db_coalescing_on_t5,
  51. "Allow DB Coalescing on T5 (default = 0)");
  52. int c4iw_wr_log = 0;
  53. module_param(c4iw_wr_log, int, 0444);
  54. MODULE_PARM_DESC(c4iw_wr_log, "Enables logging of work request timing data.");
  55. static int c4iw_wr_log_size_order = 12;
  56. module_param(c4iw_wr_log_size_order, int, 0444);
  57. MODULE_PARM_DESC(c4iw_wr_log_size_order,
  58. "Number of entries (log2) in the work request timing log.");
  59. struct uld_ctx {
  60. struct list_head entry;
  61. struct cxgb4_lld_info lldi;
  62. struct c4iw_dev *dev;
  63. };
  64. static LIST_HEAD(uld_ctx_list);
  65. static DEFINE_MUTEX(dev_mutex);
  66. #define DB_FC_RESUME_SIZE 64
  67. #define DB_FC_RESUME_DELAY 1
  68. #define DB_FC_DRAIN_THRESH 0
  69. static struct dentry *c4iw_debugfs_root;
  70. struct c4iw_debugfs_data {
  71. struct c4iw_dev *devp;
  72. char *buf;
  73. int bufsize;
  74. int pos;
  75. };
  76. /* registered cxgb4 netlink callbacks */
  77. static struct ibnl_client_cbs c4iw_nl_cb_table[] = {
  78. [RDMA_NL_IWPM_REG_PID] = {.dump = iwpm_register_pid_cb},
  79. [RDMA_NL_IWPM_ADD_MAPPING] = {.dump = iwpm_add_mapping_cb},
  80. [RDMA_NL_IWPM_QUERY_MAPPING] = {.dump = iwpm_add_and_query_mapping_cb},
  81. [RDMA_NL_IWPM_HANDLE_ERR] = {.dump = iwpm_mapping_error_cb},
  82. [RDMA_NL_IWPM_MAPINFO] = {.dump = iwpm_mapping_info_cb},
  83. [RDMA_NL_IWPM_MAPINFO_NUM] = {.dump = iwpm_ack_mapping_info_cb}
  84. };
  85. static int count_idrs(int id, void *p, void *data)
  86. {
  87. int *countp = data;
  88. *countp = *countp + 1;
  89. return 0;
  90. }
  91. static ssize_t debugfs_read(struct file *file, char __user *buf, size_t count,
  92. loff_t *ppos)
  93. {
  94. struct c4iw_debugfs_data *d = file->private_data;
  95. return simple_read_from_buffer(buf, count, ppos, d->buf, d->pos);
  96. }
  97. void c4iw_log_wr_stats(struct t4_wq *wq, struct t4_cqe *cqe)
  98. {
  99. struct wr_log_entry le;
  100. int idx;
  101. if (!wq->rdev->wr_log)
  102. return;
  103. idx = (atomic_inc_return(&wq->rdev->wr_log_idx) - 1) &
  104. (wq->rdev->wr_log_size - 1);
  105. le.poll_sge_ts = cxgb4_read_sge_timestamp(wq->rdev->lldi.ports[0]);
  106. getnstimeofday(&le.poll_host_ts);
  107. le.valid = 1;
  108. le.cqe_sge_ts = CQE_TS(cqe);
  109. if (SQ_TYPE(cqe)) {
  110. le.qid = wq->sq.qid;
  111. le.opcode = CQE_OPCODE(cqe);
  112. le.post_host_ts = wq->sq.sw_sq[wq->sq.cidx].host_ts;
  113. le.post_sge_ts = wq->sq.sw_sq[wq->sq.cidx].sge_ts;
  114. le.wr_id = CQE_WRID_SQ_IDX(cqe);
  115. } else {
  116. le.qid = wq->rq.qid;
  117. le.opcode = FW_RI_RECEIVE;
  118. le.post_host_ts = wq->rq.sw_rq[wq->rq.cidx].host_ts;
  119. le.post_sge_ts = wq->rq.sw_rq[wq->rq.cidx].sge_ts;
  120. le.wr_id = CQE_WRID_MSN(cqe);
  121. }
  122. wq->rdev->wr_log[idx] = le;
  123. }
  124. static int wr_log_show(struct seq_file *seq, void *v)
  125. {
  126. struct c4iw_dev *dev = seq->private;
  127. struct timespec prev_ts = {0, 0};
  128. struct wr_log_entry *lep;
  129. int prev_ts_set = 0;
  130. int idx, end;
  131. #define ts2ns(ts) div64_ul((ts) * dev->rdev.lldi.cclk_ps, 1000)
  132. idx = atomic_read(&dev->rdev.wr_log_idx) &
  133. (dev->rdev.wr_log_size - 1);
  134. end = idx - 1;
  135. if (end < 0)
  136. end = dev->rdev.wr_log_size - 1;
  137. lep = &dev->rdev.wr_log[idx];
  138. while (idx != end) {
  139. if (lep->valid) {
  140. if (!prev_ts_set) {
  141. prev_ts_set = 1;
  142. prev_ts = lep->poll_host_ts;
  143. }
  144. seq_printf(seq, "%04u: sec %lu nsec %lu qid %u opcode "
  145. "%u %s 0x%x host_wr_delta sec %lu nsec %lu "
  146. "post_sge_ts 0x%llx cqe_sge_ts 0x%llx "
  147. "poll_sge_ts 0x%llx post_poll_delta_ns %llu "
  148. "cqe_poll_delta_ns %llu\n",
  149. idx,
  150. timespec_sub(lep->poll_host_ts,
  151. prev_ts).tv_sec,
  152. timespec_sub(lep->poll_host_ts,
  153. prev_ts).tv_nsec,
  154. lep->qid, lep->opcode,
  155. lep->opcode == FW_RI_RECEIVE ?
  156. "msn" : "wrid",
  157. lep->wr_id,
  158. timespec_sub(lep->poll_host_ts,
  159. lep->post_host_ts).tv_sec,
  160. timespec_sub(lep->poll_host_ts,
  161. lep->post_host_ts).tv_nsec,
  162. lep->post_sge_ts, lep->cqe_sge_ts,
  163. lep->poll_sge_ts,
  164. ts2ns(lep->poll_sge_ts - lep->post_sge_ts),
  165. ts2ns(lep->poll_sge_ts - lep->cqe_sge_ts));
  166. prev_ts = lep->poll_host_ts;
  167. }
  168. idx++;
  169. if (idx > (dev->rdev.wr_log_size - 1))
  170. idx = 0;
  171. lep = &dev->rdev.wr_log[idx];
  172. }
  173. #undef ts2ns
  174. return 0;
  175. }
  176. static int wr_log_open(struct inode *inode, struct file *file)
  177. {
  178. return single_open(file, wr_log_show, inode->i_private);
  179. }
  180. static ssize_t wr_log_clear(struct file *file, const char __user *buf,
  181. size_t count, loff_t *pos)
  182. {
  183. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  184. int i;
  185. if (dev->rdev.wr_log)
  186. for (i = 0; i < dev->rdev.wr_log_size; i++)
  187. dev->rdev.wr_log[i].valid = 0;
  188. return count;
  189. }
  190. static const struct file_operations wr_log_debugfs_fops = {
  191. .owner = THIS_MODULE,
  192. .open = wr_log_open,
  193. .release = single_release,
  194. .read = seq_read,
  195. .llseek = seq_lseek,
  196. .write = wr_log_clear,
  197. };
  198. static int dump_qp(int id, void *p, void *data)
  199. {
  200. struct c4iw_qp *qp = p;
  201. struct c4iw_debugfs_data *qpd = data;
  202. int space;
  203. int cc;
  204. if (id != qp->wq.sq.qid)
  205. return 0;
  206. space = qpd->bufsize - qpd->pos - 1;
  207. if (space == 0)
  208. return 1;
  209. if (qp->ep) {
  210. if (qp->ep->com.local_addr.ss_family == AF_INET) {
  211. struct sockaddr_in *lsin = (struct sockaddr_in *)
  212. &qp->ep->com.local_addr;
  213. struct sockaddr_in *rsin = (struct sockaddr_in *)
  214. &qp->ep->com.remote_addr;
  215. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  216. &qp->ep->com.mapped_local_addr;
  217. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  218. &qp->ep->com.mapped_remote_addr;
  219. cc = snprintf(qpd->buf + qpd->pos, space,
  220. "rc qp sq id %u rq id %u state %u "
  221. "onchip %u ep tid %u state %u "
  222. "%pI4:%u/%u->%pI4:%u/%u\n",
  223. qp->wq.sq.qid, qp->wq.rq.qid,
  224. (int)qp->attr.state,
  225. qp->wq.sq.flags & T4_SQ_ONCHIP,
  226. qp->ep->hwtid, (int)qp->ep->com.state,
  227. &lsin->sin_addr, ntohs(lsin->sin_port),
  228. ntohs(mapped_lsin->sin_port),
  229. &rsin->sin_addr, ntohs(rsin->sin_port),
  230. ntohs(mapped_rsin->sin_port));
  231. } else {
  232. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  233. &qp->ep->com.local_addr;
  234. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  235. &qp->ep->com.remote_addr;
  236. struct sockaddr_in6 *mapped_lsin6 =
  237. (struct sockaddr_in6 *)
  238. &qp->ep->com.mapped_local_addr;
  239. struct sockaddr_in6 *mapped_rsin6 =
  240. (struct sockaddr_in6 *)
  241. &qp->ep->com.mapped_remote_addr;
  242. cc = snprintf(qpd->buf + qpd->pos, space,
  243. "rc qp sq id %u rq id %u state %u "
  244. "onchip %u ep tid %u state %u "
  245. "%pI6:%u/%u->%pI6:%u/%u\n",
  246. qp->wq.sq.qid, qp->wq.rq.qid,
  247. (int)qp->attr.state,
  248. qp->wq.sq.flags & T4_SQ_ONCHIP,
  249. qp->ep->hwtid, (int)qp->ep->com.state,
  250. &lsin6->sin6_addr,
  251. ntohs(lsin6->sin6_port),
  252. ntohs(mapped_lsin6->sin6_port),
  253. &rsin6->sin6_addr,
  254. ntohs(rsin6->sin6_port),
  255. ntohs(mapped_rsin6->sin6_port));
  256. }
  257. } else
  258. cc = snprintf(qpd->buf + qpd->pos, space,
  259. "qp sq id %u rq id %u state %u onchip %u\n",
  260. qp->wq.sq.qid, qp->wq.rq.qid,
  261. (int)qp->attr.state,
  262. qp->wq.sq.flags & T4_SQ_ONCHIP);
  263. if (cc < space)
  264. qpd->pos += cc;
  265. return 0;
  266. }
  267. static int qp_release(struct inode *inode, struct file *file)
  268. {
  269. struct c4iw_debugfs_data *qpd = file->private_data;
  270. if (!qpd) {
  271. printk(KERN_INFO "%s null qpd?\n", __func__);
  272. return 0;
  273. }
  274. vfree(qpd->buf);
  275. kfree(qpd);
  276. return 0;
  277. }
  278. static int qp_open(struct inode *inode, struct file *file)
  279. {
  280. struct c4iw_debugfs_data *qpd;
  281. int ret = 0;
  282. int count = 1;
  283. qpd = kmalloc(sizeof *qpd, GFP_KERNEL);
  284. if (!qpd) {
  285. ret = -ENOMEM;
  286. goto out;
  287. }
  288. qpd->devp = inode->i_private;
  289. qpd->pos = 0;
  290. spin_lock_irq(&qpd->devp->lock);
  291. idr_for_each(&qpd->devp->qpidr, count_idrs, &count);
  292. spin_unlock_irq(&qpd->devp->lock);
  293. qpd->bufsize = count * 128;
  294. qpd->buf = vmalloc(qpd->bufsize);
  295. if (!qpd->buf) {
  296. ret = -ENOMEM;
  297. goto err1;
  298. }
  299. spin_lock_irq(&qpd->devp->lock);
  300. idr_for_each(&qpd->devp->qpidr, dump_qp, qpd);
  301. spin_unlock_irq(&qpd->devp->lock);
  302. qpd->buf[qpd->pos++] = 0;
  303. file->private_data = qpd;
  304. goto out;
  305. err1:
  306. kfree(qpd);
  307. out:
  308. return ret;
  309. }
  310. static const struct file_operations qp_debugfs_fops = {
  311. .owner = THIS_MODULE,
  312. .open = qp_open,
  313. .release = qp_release,
  314. .read = debugfs_read,
  315. .llseek = default_llseek,
  316. };
  317. static int dump_stag(int id, void *p, void *data)
  318. {
  319. struct c4iw_debugfs_data *stagd = data;
  320. int space;
  321. int cc;
  322. struct fw_ri_tpte tpte;
  323. int ret;
  324. space = stagd->bufsize - stagd->pos - 1;
  325. if (space == 0)
  326. return 1;
  327. ret = cxgb4_read_tpte(stagd->devp->rdev.lldi.ports[0], (u32)id<<8,
  328. (__be32 *)&tpte);
  329. if (ret) {
  330. dev_err(&stagd->devp->rdev.lldi.pdev->dev,
  331. "%s cxgb4_read_tpte err %d\n", __func__, ret);
  332. return ret;
  333. }
  334. cc = snprintf(stagd->buf + stagd->pos, space,
  335. "stag: idx 0x%x valid %d key 0x%x state %d pdid %d "
  336. "perm 0x%x ps %d len 0x%llx va 0x%llx\n",
  337. (u32)id<<8,
  338. G_FW_RI_TPTE_VALID(ntohl(tpte.valid_to_pdid)),
  339. G_FW_RI_TPTE_STAGKEY(ntohl(tpte.valid_to_pdid)),
  340. G_FW_RI_TPTE_STAGSTATE(ntohl(tpte.valid_to_pdid)),
  341. G_FW_RI_TPTE_PDID(ntohl(tpte.valid_to_pdid)),
  342. G_FW_RI_TPTE_PERM(ntohl(tpte.locread_to_qpid)),
  343. G_FW_RI_TPTE_PS(ntohl(tpte.locread_to_qpid)),
  344. ((u64)ntohl(tpte.len_hi) << 32) | ntohl(tpte.len_lo),
  345. ((u64)ntohl(tpte.va_hi) << 32) | ntohl(tpte.va_lo_fbo));
  346. if (cc < space)
  347. stagd->pos += cc;
  348. return 0;
  349. }
  350. static int stag_release(struct inode *inode, struct file *file)
  351. {
  352. struct c4iw_debugfs_data *stagd = file->private_data;
  353. if (!stagd) {
  354. printk(KERN_INFO "%s null stagd?\n", __func__);
  355. return 0;
  356. }
  357. vfree(stagd->buf);
  358. kfree(stagd);
  359. return 0;
  360. }
  361. static int stag_open(struct inode *inode, struct file *file)
  362. {
  363. struct c4iw_debugfs_data *stagd;
  364. int ret = 0;
  365. int count = 1;
  366. stagd = kmalloc(sizeof *stagd, GFP_KERNEL);
  367. if (!stagd) {
  368. ret = -ENOMEM;
  369. goto out;
  370. }
  371. stagd->devp = inode->i_private;
  372. stagd->pos = 0;
  373. spin_lock_irq(&stagd->devp->lock);
  374. idr_for_each(&stagd->devp->mmidr, count_idrs, &count);
  375. spin_unlock_irq(&stagd->devp->lock);
  376. stagd->bufsize = count * 256;
  377. stagd->buf = vmalloc(stagd->bufsize);
  378. if (!stagd->buf) {
  379. ret = -ENOMEM;
  380. goto err1;
  381. }
  382. spin_lock_irq(&stagd->devp->lock);
  383. idr_for_each(&stagd->devp->mmidr, dump_stag, stagd);
  384. spin_unlock_irq(&stagd->devp->lock);
  385. stagd->buf[stagd->pos++] = 0;
  386. file->private_data = stagd;
  387. goto out;
  388. err1:
  389. kfree(stagd);
  390. out:
  391. return ret;
  392. }
  393. static const struct file_operations stag_debugfs_fops = {
  394. .owner = THIS_MODULE,
  395. .open = stag_open,
  396. .release = stag_release,
  397. .read = debugfs_read,
  398. .llseek = default_llseek,
  399. };
  400. static char *db_state_str[] = {"NORMAL", "FLOW_CONTROL", "RECOVERY", "STOPPED"};
  401. static int stats_show(struct seq_file *seq, void *v)
  402. {
  403. struct c4iw_dev *dev = seq->private;
  404. seq_printf(seq, " Object: %10s %10s %10s %10s\n", "Total", "Current",
  405. "Max", "Fail");
  406. seq_printf(seq, " PDID: %10llu %10llu %10llu %10llu\n",
  407. dev->rdev.stats.pd.total, dev->rdev.stats.pd.cur,
  408. dev->rdev.stats.pd.max, dev->rdev.stats.pd.fail);
  409. seq_printf(seq, " QID: %10llu %10llu %10llu %10llu\n",
  410. dev->rdev.stats.qid.total, dev->rdev.stats.qid.cur,
  411. dev->rdev.stats.qid.max, dev->rdev.stats.qid.fail);
  412. seq_printf(seq, " TPTMEM: %10llu %10llu %10llu %10llu\n",
  413. dev->rdev.stats.stag.total, dev->rdev.stats.stag.cur,
  414. dev->rdev.stats.stag.max, dev->rdev.stats.stag.fail);
  415. seq_printf(seq, " PBLMEM: %10llu %10llu %10llu %10llu\n",
  416. dev->rdev.stats.pbl.total, dev->rdev.stats.pbl.cur,
  417. dev->rdev.stats.pbl.max, dev->rdev.stats.pbl.fail);
  418. seq_printf(seq, " RQTMEM: %10llu %10llu %10llu %10llu\n",
  419. dev->rdev.stats.rqt.total, dev->rdev.stats.rqt.cur,
  420. dev->rdev.stats.rqt.max, dev->rdev.stats.rqt.fail);
  421. seq_printf(seq, " OCQPMEM: %10llu %10llu %10llu %10llu\n",
  422. dev->rdev.stats.ocqp.total, dev->rdev.stats.ocqp.cur,
  423. dev->rdev.stats.ocqp.max, dev->rdev.stats.ocqp.fail);
  424. seq_printf(seq, " DB FULL: %10llu\n", dev->rdev.stats.db_full);
  425. seq_printf(seq, " DB EMPTY: %10llu\n", dev->rdev.stats.db_empty);
  426. seq_printf(seq, " DB DROP: %10llu\n", dev->rdev.stats.db_drop);
  427. seq_printf(seq, " DB State: %s Transitions %llu FC Interruptions %llu\n",
  428. db_state_str[dev->db_state],
  429. dev->rdev.stats.db_state_transitions,
  430. dev->rdev.stats.db_fc_interruptions);
  431. seq_printf(seq, "TCAM_FULL: %10llu\n", dev->rdev.stats.tcam_full);
  432. seq_printf(seq, "ACT_OFLD_CONN_FAILS: %10llu\n",
  433. dev->rdev.stats.act_ofld_conn_fails);
  434. seq_printf(seq, "PAS_OFLD_CONN_FAILS: %10llu\n",
  435. dev->rdev.stats.pas_ofld_conn_fails);
  436. seq_printf(seq, "AVAILABLE IRD: %10u\n", dev->avail_ird);
  437. return 0;
  438. }
  439. static int stats_open(struct inode *inode, struct file *file)
  440. {
  441. return single_open(file, stats_show, inode->i_private);
  442. }
  443. static ssize_t stats_clear(struct file *file, const char __user *buf,
  444. size_t count, loff_t *pos)
  445. {
  446. struct c4iw_dev *dev = ((struct seq_file *)file->private_data)->private;
  447. mutex_lock(&dev->rdev.stats.lock);
  448. dev->rdev.stats.pd.max = 0;
  449. dev->rdev.stats.pd.fail = 0;
  450. dev->rdev.stats.qid.max = 0;
  451. dev->rdev.stats.qid.fail = 0;
  452. dev->rdev.stats.stag.max = 0;
  453. dev->rdev.stats.stag.fail = 0;
  454. dev->rdev.stats.pbl.max = 0;
  455. dev->rdev.stats.pbl.fail = 0;
  456. dev->rdev.stats.rqt.max = 0;
  457. dev->rdev.stats.rqt.fail = 0;
  458. dev->rdev.stats.ocqp.max = 0;
  459. dev->rdev.stats.ocqp.fail = 0;
  460. dev->rdev.stats.db_full = 0;
  461. dev->rdev.stats.db_empty = 0;
  462. dev->rdev.stats.db_drop = 0;
  463. dev->rdev.stats.db_state_transitions = 0;
  464. dev->rdev.stats.tcam_full = 0;
  465. dev->rdev.stats.act_ofld_conn_fails = 0;
  466. dev->rdev.stats.pas_ofld_conn_fails = 0;
  467. mutex_unlock(&dev->rdev.stats.lock);
  468. return count;
  469. }
  470. static const struct file_operations stats_debugfs_fops = {
  471. .owner = THIS_MODULE,
  472. .open = stats_open,
  473. .release = single_release,
  474. .read = seq_read,
  475. .llseek = seq_lseek,
  476. .write = stats_clear,
  477. };
  478. static int dump_ep(int id, void *p, void *data)
  479. {
  480. struct c4iw_ep *ep = p;
  481. struct c4iw_debugfs_data *epd = data;
  482. int space;
  483. int cc;
  484. space = epd->bufsize - epd->pos - 1;
  485. if (space == 0)
  486. return 1;
  487. if (ep->com.local_addr.ss_family == AF_INET) {
  488. struct sockaddr_in *lsin = (struct sockaddr_in *)
  489. &ep->com.local_addr;
  490. struct sockaddr_in *rsin = (struct sockaddr_in *)
  491. &ep->com.remote_addr;
  492. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  493. &ep->com.mapped_local_addr;
  494. struct sockaddr_in *mapped_rsin = (struct sockaddr_in *)
  495. &ep->com.mapped_remote_addr;
  496. cc = snprintf(epd->buf + epd->pos, space,
  497. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  498. "history 0x%lx hwtid %d atid %d "
  499. "%pI4:%d/%d <-> %pI4:%d/%d\n",
  500. ep, ep->com.cm_id, ep->com.qp,
  501. (int)ep->com.state, ep->com.flags,
  502. ep->com.history, ep->hwtid, ep->atid,
  503. &lsin->sin_addr, ntohs(lsin->sin_port),
  504. ntohs(mapped_lsin->sin_port),
  505. &rsin->sin_addr, ntohs(rsin->sin_port),
  506. ntohs(mapped_rsin->sin_port));
  507. } else {
  508. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  509. &ep->com.local_addr;
  510. struct sockaddr_in6 *rsin6 = (struct sockaddr_in6 *)
  511. &ep->com.remote_addr;
  512. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  513. &ep->com.mapped_local_addr;
  514. struct sockaddr_in6 *mapped_rsin6 = (struct sockaddr_in6 *)
  515. &ep->com.mapped_remote_addr;
  516. cc = snprintf(epd->buf + epd->pos, space,
  517. "ep %p cm_id %p qp %p state %d flags 0x%lx "
  518. "history 0x%lx hwtid %d atid %d "
  519. "%pI6:%d/%d <-> %pI6:%d/%d\n",
  520. ep, ep->com.cm_id, ep->com.qp,
  521. (int)ep->com.state, ep->com.flags,
  522. ep->com.history, ep->hwtid, ep->atid,
  523. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  524. ntohs(mapped_lsin6->sin6_port),
  525. &rsin6->sin6_addr, ntohs(rsin6->sin6_port),
  526. ntohs(mapped_rsin6->sin6_port));
  527. }
  528. if (cc < space)
  529. epd->pos += cc;
  530. return 0;
  531. }
  532. static int dump_listen_ep(int id, void *p, void *data)
  533. {
  534. struct c4iw_listen_ep *ep = p;
  535. struct c4iw_debugfs_data *epd = data;
  536. int space;
  537. int cc;
  538. space = epd->bufsize - epd->pos - 1;
  539. if (space == 0)
  540. return 1;
  541. if (ep->com.local_addr.ss_family == AF_INET) {
  542. struct sockaddr_in *lsin = (struct sockaddr_in *)
  543. &ep->com.local_addr;
  544. struct sockaddr_in *mapped_lsin = (struct sockaddr_in *)
  545. &ep->com.mapped_local_addr;
  546. cc = snprintf(epd->buf + epd->pos, space,
  547. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  548. "backlog %d %pI4:%d/%d\n",
  549. ep, ep->com.cm_id, (int)ep->com.state,
  550. ep->com.flags, ep->stid, ep->backlog,
  551. &lsin->sin_addr, ntohs(lsin->sin_port),
  552. ntohs(mapped_lsin->sin_port));
  553. } else {
  554. struct sockaddr_in6 *lsin6 = (struct sockaddr_in6 *)
  555. &ep->com.local_addr;
  556. struct sockaddr_in6 *mapped_lsin6 = (struct sockaddr_in6 *)
  557. &ep->com.mapped_local_addr;
  558. cc = snprintf(epd->buf + epd->pos, space,
  559. "ep %p cm_id %p state %d flags 0x%lx stid %d "
  560. "backlog %d %pI6:%d/%d\n",
  561. ep, ep->com.cm_id, (int)ep->com.state,
  562. ep->com.flags, ep->stid, ep->backlog,
  563. &lsin6->sin6_addr, ntohs(lsin6->sin6_port),
  564. ntohs(mapped_lsin6->sin6_port));
  565. }
  566. if (cc < space)
  567. epd->pos += cc;
  568. return 0;
  569. }
  570. static int ep_release(struct inode *inode, struct file *file)
  571. {
  572. struct c4iw_debugfs_data *epd = file->private_data;
  573. if (!epd) {
  574. pr_info("%s null qpd?\n", __func__);
  575. return 0;
  576. }
  577. vfree(epd->buf);
  578. kfree(epd);
  579. return 0;
  580. }
  581. static int ep_open(struct inode *inode, struct file *file)
  582. {
  583. struct c4iw_debugfs_data *epd;
  584. int ret = 0;
  585. int count = 1;
  586. epd = kmalloc(sizeof(*epd), GFP_KERNEL);
  587. if (!epd) {
  588. ret = -ENOMEM;
  589. goto out;
  590. }
  591. epd->devp = inode->i_private;
  592. epd->pos = 0;
  593. spin_lock_irq(&epd->devp->lock);
  594. idr_for_each(&epd->devp->hwtid_idr, count_idrs, &count);
  595. idr_for_each(&epd->devp->atid_idr, count_idrs, &count);
  596. idr_for_each(&epd->devp->stid_idr, count_idrs, &count);
  597. spin_unlock_irq(&epd->devp->lock);
  598. epd->bufsize = count * 240;
  599. epd->buf = vmalloc(epd->bufsize);
  600. if (!epd->buf) {
  601. ret = -ENOMEM;
  602. goto err1;
  603. }
  604. spin_lock_irq(&epd->devp->lock);
  605. idr_for_each(&epd->devp->hwtid_idr, dump_ep, epd);
  606. idr_for_each(&epd->devp->atid_idr, dump_ep, epd);
  607. idr_for_each(&epd->devp->stid_idr, dump_listen_ep, epd);
  608. spin_unlock_irq(&epd->devp->lock);
  609. file->private_data = epd;
  610. goto out;
  611. err1:
  612. kfree(epd);
  613. out:
  614. return ret;
  615. }
  616. static const struct file_operations ep_debugfs_fops = {
  617. .owner = THIS_MODULE,
  618. .open = ep_open,
  619. .release = ep_release,
  620. .read = debugfs_read,
  621. };
  622. static int setup_debugfs(struct c4iw_dev *devp)
  623. {
  624. struct dentry *de;
  625. if (!devp->debugfs_root)
  626. return -1;
  627. de = debugfs_create_file("qps", S_IWUSR, devp->debugfs_root,
  628. (void *)devp, &qp_debugfs_fops);
  629. if (de && de->d_inode)
  630. de->d_inode->i_size = 4096;
  631. de = debugfs_create_file("stags", S_IWUSR, devp->debugfs_root,
  632. (void *)devp, &stag_debugfs_fops);
  633. if (de && de->d_inode)
  634. de->d_inode->i_size = 4096;
  635. de = debugfs_create_file("stats", S_IWUSR, devp->debugfs_root,
  636. (void *)devp, &stats_debugfs_fops);
  637. if (de && de->d_inode)
  638. de->d_inode->i_size = 4096;
  639. de = debugfs_create_file("eps", S_IWUSR, devp->debugfs_root,
  640. (void *)devp, &ep_debugfs_fops);
  641. if (de && de->d_inode)
  642. de->d_inode->i_size = 4096;
  643. if (c4iw_wr_log) {
  644. de = debugfs_create_file("wr_log", S_IWUSR, devp->debugfs_root,
  645. (void *)devp, &wr_log_debugfs_fops);
  646. if (de && de->d_inode)
  647. de->d_inode->i_size = 4096;
  648. }
  649. return 0;
  650. }
  651. void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
  652. struct c4iw_dev_ucontext *uctx)
  653. {
  654. struct list_head *pos, *nxt;
  655. struct c4iw_qid_list *entry;
  656. mutex_lock(&uctx->lock);
  657. list_for_each_safe(pos, nxt, &uctx->qpids) {
  658. entry = list_entry(pos, struct c4iw_qid_list, entry);
  659. list_del_init(&entry->entry);
  660. if (!(entry->qid & rdev->qpmask)) {
  661. c4iw_put_resource(&rdev->resource.qid_table,
  662. entry->qid);
  663. mutex_lock(&rdev->stats.lock);
  664. rdev->stats.qid.cur -= rdev->qpmask + 1;
  665. mutex_unlock(&rdev->stats.lock);
  666. }
  667. kfree(entry);
  668. }
  669. list_for_each_safe(pos, nxt, &uctx->qpids) {
  670. entry = list_entry(pos, struct c4iw_qid_list, entry);
  671. list_del_init(&entry->entry);
  672. kfree(entry);
  673. }
  674. mutex_unlock(&uctx->lock);
  675. }
  676. void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
  677. struct c4iw_dev_ucontext *uctx)
  678. {
  679. INIT_LIST_HEAD(&uctx->qpids);
  680. INIT_LIST_HEAD(&uctx->cqids);
  681. mutex_init(&uctx->lock);
  682. }
  683. /* Caller takes care of locking if needed */
  684. static int c4iw_rdev_open(struct c4iw_rdev *rdev)
  685. {
  686. int err;
  687. c4iw_init_dev_ucontext(rdev, &rdev->uctx);
  688. /*
  689. * qpshift is the number of bits to shift the qpid left in order
  690. * to get the correct address of the doorbell for that qp.
  691. */
  692. rdev->qpshift = PAGE_SHIFT - ilog2(rdev->lldi.udb_density);
  693. rdev->qpmask = rdev->lldi.udb_density - 1;
  694. rdev->cqshift = PAGE_SHIFT - ilog2(rdev->lldi.ucq_density);
  695. rdev->cqmask = rdev->lldi.ucq_density - 1;
  696. PDBG("%s dev %s stag start 0x%0x size 0x%0x num stags %d "
  697. "pbl start 0x%0x size 0x%0x rq start 0x%0x size 0x%0x "
  698. "qp qid start %u size %u cq qid start %u size %u\n",
  699. __func__, pci_name(rdev->lldi.pdev), rdev->lldi.vr->stag.start,
  700. rdev->lldi.vr->stag.size, c4iw_num_stags(rdev),
  701. rdev->lldi.vr->pbl.start,
  702. rdev->lldi.vr->pbl.size, rdev->lldi.vr->rq.start,
  703. rdev->lldi.vr->rq.size,
  704. rdev->lldi.vr->qp.start,
  705. rdev->lldi.vr->qp.size,
  706. rdev->lldi.vr->cq.start,
  707. rdev->lldi.vr->cq.size);
  708. PDBG("udb len 0x%x udb base %llx db_reg %p gts_reg %p qpshift %lu "
  709. "qpmask 0x%x cqshift %lu cqmask 0x%x\n",
  710. (unsigned)pci_resource_len(rdev->lldi.pdev, 2),
  711. (u64)pci_resource_start(rdev->lldi.pdev, 2),
  712. rdev->lldi.db_reg,
  713. rdev->lldi.gts_reg,
  714. rdev->qpshift, rdev->qpmask,
  715. rdev->cqshift, rdev->cqmask);
  716. if (c4iw_num_stags(rdev) == 0) {
  717. err = -EINVAL;
  718. goto err1;
  719. }
  720. rdev->stats.pd.total = T4_MAX_NUM_PD;
  721. rdev->stats.stag.total = rdev->lldi.vr->stag.size;
  722. rdev->stats.pbl.total = rdev->lldi.vr->pbl.size;
  723. rdev->stats.rqt.total = rdev->lldi.vr->rq.size;
  724. rdev->stats.ocqp.total = rdev->lldi.vr->ocq.size;
  725. rdev->stats.qid.total = rdev->lldi.vr->qp.size;
  726. err = c4iw_init_resource(rdev, c4iw_num_stags(rdev), T4_MAX_NUM_PD);
  727. if (err) {
  728. printk(KERN_ERR MOD "error %d initializing resources\n", err);
  729. goto err1;
  730. }
  731. err = c4iw_pblpool_create(rdev);
  732. if (err) {
  733. printk(KERN_ERR MOD "error %d initializing pbl pool\n", err);
  734. goto err2;
  735. }
  736. err = c4iw_rqtpool_create(rdev);
  737. if (err) {
  738. printk(KERN_ERR MOD "error %d initializing rqt pool\n", err);
  739. goto err3;
  740. }
  741. err = c4iw_ocqp_pool_create(rdev);
  742. if (err) {
  743. printk(KERN_ERR MOD "error %d initializing ocqp pool\n", err);
  744. goto err4;
  745. }
  746. rdev->status_page = (struct t4_dev_status_page *)
  747. __get_free_page(GFP_KERNEL);
  748. if (!rdev->status_page) {
  749. pr_err(MOD "error allocating status page\n");
  750. goto err4;
  751. }
  752. if (c4iw_wr_log) {
  753. rdev->wr_log = kzalloc((1 << c4iw_wr_log_size_order) *
  754. sizeof(*rdev->wr_log), GFP_KERNEL);
  755. if (rdev->wr_log) {
  756. rdev->wr_log_size = 1 << c4iw_wr_log_size_order;
  757. atomic_set(&rdev->wr_log_idx, 0);
  758. } else {
  759. pr_err(MOD "error allocating wr_log. Logging disabled\n");
  760. }
  761. }
  762. rdev->status_page->db_off = 0;
  763. return 0;
  764. err4:
  765. c4iw_rqtpool_destroy(rdev);
  766. err3:
  767. c4iw_pblpool_destroy(rdev);
  768. err2:
  769. c4iw_destroy_resource(&rdev->resource);
  770. err1:
  771. return err;
  772. }
  773. static void c4iw_rdev_close(struct c4iw_rdev *rdev)
  774. {
  775. kfree(rdev->wr_log);
  776. free_page((unsigned long)rdev->status_page);
  777. c4iw_pblpool_destroy(rdev);
  778. c4iw_rqtpool_destroy(rdev);
  779. c4iw_destroy_resource(&rdev->resource);
  780. }
  781. static void c4iw_dealloc(struct uld_ctx *ctx)
  782. {
  783. c4iw_rdev_close(&ctx->dev->rdev);
  784. idr_destroy(&ctx->dev->cqidr);
  785. idr_destroy(&ctx->dev->qpidr);
  786. idr_destroy(&ctx->dev->mmidr);
  787. idr_destroy(&ctx->dev->hwtid_idr);
  788. idr_destroy(&ctx->dev->stid_idr);
  789. idr_destroy(&ctx->dev->atid_idr);
  790. if (ctx->dev->rdev.bar2_kva)
  791. iounmap(ctx->dev->rdev.bar2_kva);
  792. if (ctx->dev->rdev.oc_mw_kva)
  793. iounmap(ctx->dev->rdev.oc_mw_kva);
  794. ib_dealloc_device(&ctx->dev->ibdev);
  795. ctx->dev = NULL;
  796. }
  797. static void c4iw_remove(struct uld_ctx *ctx)
  798. {
  799. PDBG("%s c4iw_dev %p\n", __func__, ctx->dev);
  800. c4iw_unregister_device(ctx->dev);
  801. c4iw_dealloc(ctx);
  802. }
  803. static int rdma_supported(const struct cxgb4_lld_info *infop)
  804. {
  805. return infop->vr->stag.size > 0 && infop->vr->pbl.size > 0 &&
  806. infop->vr->rq.size > 0 && infop->vr->qp.size > 0 &&
  807. infop->vr->cq.size > 0;
  808. }
  809. static struct c4iw_dev *c4iw_alloc(const struct cxgb4_lld_info *infop)
  810. {
  811. struct c4iw_dev *devp;
  812. int ret;
  813. if (!rdma_supported(infop)) {
  814. printk(KERN_INFO MOD "%s: RDMA not supported on this device.\n",
  815. pci_name(infop->pdev));
  816. return ERR_PTR(-ENOSYS);
  817. }
  818. if (!ocqp_supported(infop))
  819. pr_info("%s: On-Chip Queues not supported on this device.\n",
  820. pci_name(infop->pdev));
  821. devp = (struct c4iw_dev *)ib_alloc_device(sizeof(*devp));
  822. if (!devp) {
  823. printk(KERN_ERR MOD "Cannot allocate ib device\n");
  824. return ERR_PTR(-ENOMEM);
  825. }
  826. devp->rdev.lldi = *infop;
  827. /* init various hw-queue params based on lld info */
  828. PDBG("%s: Ing. padding boundary is %d, egrsstatuspagesize = %d\n",
  829. __func__, devp->rdev.lldi.sge_ingpadboundary,
  830. devp->rdev.lldi.sge_egrstatuspagesize);
  831. devp->rdev.hw_queue.t4_eq_status_entries =
  832. devp->rdev.lldi.sge_ingpadboundary > 64 ? 2 : 1;
  833. devp->rdev.hw_queue.t4_max_eq_size = 65520;
  834. devp->rdev.hw_queue.t4_max_iq_size = 65520;
  835. devp->rdev.hw_queue.t4_max_rq_size = 8192 -
  836. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  837. devp->rdev.hw_queue.t4_max_sq_size =
  838. devp->rdev.hw_queue.t4_max_eq_size -
  839. devp->rdev.hw_queue.t4_eq_status_entries - 1;
  840. devp->rdev.hw_queue.t4_max_qp_depth =
  841. devp->rdev.hw_queue.t4_max_rq_size;
  842. devp->rdev.hw_queue.t4_max_cq_depth =
  843. devp->rdev.hw_queue.t4_max_iq_size - 2;
  844. devp->rdev.hw_queue.t4_stat_len =
  845. devp->rdev.lldi.sge_egrstatuspagesize;
  846. /*
  847. * For T5 devices, we map all of BAR2 with WC.
  848. * For T4 devices with onchip qp mem, we map only that part
  849. * of BAR2 with WC.
  850. */
  851. devp->rdev.bar2_pa = pci_resource_start(devp->rdev.lldi.pdev, 2);
  852. if (is_t5(devp->rdev.lldi.adapter_type)) {
  853. devp->rdev.bar2_kva = ioremap_wc(devp->rdev.bar2_pa,
  854. pci_resource_len(devp->rdev.lldi.pdev, 2));
  855. if (!devp->rdev.bar2_kva) {
  856. pr_err(MOD "Unable to ioremap BAR2\n");
  857. ib_dealloc_device(&devp->ibdev);
  858. return ERR_PTR(-EINVAL);
  859. }
  860. } else if (ocqp_supported(infop)) {
  861. devp->rdev.oc_mw_pa =
  862. pci_resource_start(devp->rdev.lldi.pdev, 2) +
  863. pci_resource_len(devp->rdev.lldi.pdev, 2) -
  864. roundup_pow_of_two(devp->rdev.lldi.vr->ocq.size);
  865. devp->rdev.oc_mw_kva = ioremap_wc(devp->rdev.oc_mw_pa,
  866. devp->rdev.lldi.vr->ocq.size);
  867. if (!devp->rdev.oc_mw_kva) {
  868. pr_err(MOD "Unable to ioremap onchip mem\n");
  869. ib_dealloc_device(&devp->ibdev);
  870. return ERR_PTR(-EINVAL);
  871. }
  872. }
  873. PDBG(KERN_INFO MOD "ocq memory: "
  874. "hw_start 0x%x size %u mw_pa 0x%lx mw_kva %p\n",
  875. devp->rdev.lldi.vr->ocq.start, devp->rdev.lldi.vr->ocq.size,
  876. devp->rdev.oc_mw_pa, devp->rdev.oc_mw_kva);
  877. ret = c4iw_rdev_open(&devp->rdev);
  878. if (ret) {
  879. printk(KERN_ERR MOD "Unable to open CXIO rdev err %d\n", ret);
  880. ib_dealloc_device(&devp->ibdev);
  881. return ERR_PTR(ret);
  882. }
  883. idr_init(&devp->cqidr);
  884. idr_init(&devp->qpidr);
  885. idr_init(&devp->mmidr);
  886. idr_init(&devp->hwtid_idr);
  887. idr_init(&devp->stid_idr);
  888. idr_init(&devp->atid_idr);
  889. spin_lock_init(&devp->lock);
  890. mutex_init(&devp->rdev.stats.lock);
  891. mutex_init(&devp->db_mutex);
  892. INIT_LIST_HEAD(&devp->db_fc_list);
  893. devp->avail_ird = devp->rdev.lldi.max_ird_adapter;
  894. if (c4iw_debugfs_root) {
  895. devp->debugfs_root = debugfs_create_dir(
  896. pci_name(devp->rdev.lldi.pdev),
  897. c4iw_debugfs_root);
  898. setup_debugfs(devp);
  899. }
  900. return devp;
  901. }
  902. static void *c4iw_uld_add(const struct cxgb4_lld_info *infop)
  903. {
  904. struct uld_ctx *ctx;
  905. static int vers_printed;
  906. int i;
  907. if (!vers_printed++)
  908. pr_info("Chelsio T4/T5 RDMA Driver - version %s\n",
  909. DRV_VERSION);
  910. ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
  911. if (!ctx) {
  912. ctx = ERR_PTR(-ENOMEM);
  913. goto out;
  914. }
  915. ctx->lldi = *infop;
  916. PDBG("%s found device %s nchan %u nrxq %u ntxq %u nports %u\n",
  917. __func__, pci_name(ctx->lldi.pdev),
  918. ctx->lldi.nchan, ctx->lldi.nrxq,
  919. ctx->lldi.ntxq, ctx->lldi.nports);
  920. mutex_lock(&dev_mutex);
  921. list_add_tail(&ctx->entry, &uld_ctx_list);
  922. mutex_unlock(&dev_mutex);
  923. for (i = 0; i < ctx->lldi.nrxq; i++)
  924. PDBG("rxqid[%u] %u\n", i, ctx->lldi.rxq_ids[i]);
  925. out:
  926. return ctx;
  927. }
  928. static inline struct sk_buff *copy_gl_to_skb_pkt(const struct pkt_gl *gl,
  929. const __be64 *rsp,
  930. u32 pktshift)
  931. {
  932. struct sk_buff *skb;
  933. /*
  934. * Allocate space for cpl_pass_accept_req which will be synthesized by
  935. * driver. Once the driver synthesizes the request the skb will go
  936. * through the regular cpl_pass_accept_req processing.
  937. * The math here assumes sizeof cpl_pass_accept_req >= sizeof
  938. * cpl_rx_pkt.
  939. */
  940. skb = alloc_skb(gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  941. sizeof(struct rss_header) - pktshift, GFP_ATOMIC);
  942. if (unlikely(!skb))
  943. return NULL;
  944. __skb_put(skb, gl->tot_len + sizeof(struct cpl_pass_accept_req) +
  945. sizeof(struct rss_header) - pktshift);
  946. /*
  947. * This skb will contain:
  948. * rss_header from the rspq descriptor (1 flit)
  949. * cpl_rx_pkt struct from the rspq descriptor (2 flits)
  950. * space for the difference between the size of an
  951. * rx_pkt and pass_accept_req cpl (1 flit)
  952. * the packet data from the gl
  953. */
  954. skb_copy_to_linear_data(skb, rsp, sizeof(struct cpl_pass_accept_req) +
  955. sizeof(struct rss_header));
  956. skb_copy_to_linear_data_offset(skb, sizeof(struct rss_header) +
  957. sizeof(struct cpl_pass_accept_req),
  958. gl->va + pktshift,
  959. gl->tot_len - pktshift);
  960. return skb;
  961. }
  962. static inline int recv_rx_pkt(struct c4iw_dev *dev, const struct pkt_gl *gl,
  963. const __be64 *rsp)
  964. {
  965. unsigned int opcode = *(u8 *)rsp;
  966. struct sk_buff *skb;
  967. if (opcode != CPL_RX_PKT)
  968. goto out;
  969. skb = copy_gl_to_skb_pkt(gl , rsp, dev->rdev.lldi.sge_pktshift);
  970. if (skb == NULL)
  971. goto out;
  972. if (c4iw_handlers[opcode] == NULL) {
  973. pr_info("%s no handler opcode 0x%x...\n", __func__,
  974. opcode);
  975. kfree_skb(skb);
  976. goto out;
  977. }
  978. c4iw_handlers[opcode](dev, skb);
  979. return 1;
  980. out:
  981. return 0;
  982. }
  983. static int c4iw_uld_rx_handler(void *handle, const __be64 *rsp,
  984. const struct pkt_gl *gl)
  985. {
  986. struct uld_ctx *ctx = handle;
  987. struct c4iw_dev *dev = ctx->dev;
  988. struct sk_buff *skb;
  989. u8 opcode;
  990. if (gl == NULL) {
  991. /* omit RSS and rsp_ctrl at end of descriptor */
  992. unsigned int len = 64 - sizeof(struct rsp_ctrl) - 8;
  993. skb = alloc_skb(256, GFP_ATOMIC);
  994. if (!skb)
  995. goto nomem;
  996. __skb_put(skb, len);
  997. skb_copy_to_linear_data(skb, &rsp[1], len);
  998. } else if (gl == CXGB4_MSG_AN) {
  999. const struct rsp_ctrl *rc = (void *)rsp;
  1000. u32 qid = be32_to_cpu(rc->pldbuflen_qid);
  1001. c4iw_ev_handler(dev, qid);
  1002. return 0;
  1003. } else if (unlikely(*(u8 *)rsp != *(u8 *)gl->va)) {
  1004. if (recv_rx_pkt(dev, gl, rsp))
  1005. return 0;
  1006. pr_info("%s: unexpected FL contents at %p, " \
  1007. "RSS %#llx, FL %#llx, len %u\n",
  1008. pci_name(ctx->lldi.pdev), gl->va,
  1009. (unsigned long long)be64_to_cpu(*rsp),
  1010. (unsigned long long)be64_to_cpu(
  1011. *(__force __be64 *)gl->va),
  1012. gl->tot_len);
  1013. return 0;
  1014. } else {
  1015. skb = cxgb4_pktgl_to_skb(gl, 128, 128);
  1016. if (unlikely(!skb))
  1017. goto nomem;
  1018. }
  1019. opcode = *(u8 *)rsp;
  1020. if (c4iw_handlers[opcode]) {
  1021. c4iw_handlers[opcode](dev, skb);
  1022. } else {
  1023. pr_info("%s no handler opcode 0x%x...\n", __func__,
  1024. opcode);
  1025. kfree_skb(skb);
  1026. }
  1027. return 0;
  1028. nomem:
  1029. return -1;
  1030. }
  1031. static int c4iw_uld_state_change(void *handle, enum cxgb4_state new_state)
  1032. {
  1033. struct uld_ctx *ctx = handle;
  1034. PDBG("%s new_state %u\n", __func__, new_state);
  1035. switch (new_state) {
  1036. case CXGB4_STATE_UP:
  1037. printk(KERN_INFO MOD "%s: Up\n", pci_name(ctx->lldi.pdev));
  1038. if (!ctx->dev) {
  1039. int ret;
  1040. ctx->dev = c4iw_alloc(&ctx->lldi);
  1041. if (IS_ERR(ctx->dev)) {
  1042. printk(KERN_ERR MOD
  1043. "%s: initialization failed: %ld\n",
  1044. pci_name(ctx->lldi.pdev),
  1045. PTR_ERR(ctx->dev));
  1046. ctx->dev = NULL;
  1047. break;
  1048. }
  1049. ret = c4iw_register_device(ctx->dev);
  1050. if (ret) {
  1051. printk(KERN_ERR MOD
  1052. "%s: RDMA registration failed: %d\n",
  1053. pci_name(ctx->lldi.pdev), ret);
  1054. c4iw_dealloc(ctx);
  1055. }
  1056. }
  1057. break;
  1058. case CXGB4_STATE_DOWN:
  1059. printk(KERN_INFO MOD "%s: Down\n",
  1060. pci_name(ctx->lldi.pdev));
  1061. if (ctx->dev)
  1062. c4iw_remove(ctx);
  1063. break;
  1064. case CXGB4_STATE_START_RECOVERY:
  1065. printk(KERN_INFO MOD "%s: Fatal Error\n",
  1066. pci_name(ctx->lldi.pdev));
  1067. if (ctx->dev) {
  1068. struct ib_event event;
  1069. ctx->dev->rdev.flags |= T4_FATAL_ERROR;
  1070. memset(&event, 0, sizeof event);
  1071. event.event = IB_EVENT_DEVICE_FATAL;
  1072. event.device = &ctx->dev->ibdev;
  1073. ib_dispatch_event(&event);
  1074. c4iw_remove(ctx);
  1075. }
  1076. break;
  1077. case CXGB4_STATE_DETACH:
  1078. printk(KERN_INFO MOD "%s: Detach\n",
  1079. pci_name(ctx->lldi.pdev));
  1080. if (ctx->dev)
  1081. c4iw_remove(ctx);
  1082. break;
  1083. }
  1084. return 0;
  1085. }
  1086. static int disable_qp_db(int id, void *p, void *data)
  1087. {
  1088. struct c4iw_qp *qp = p;
  1089. t4_disable_wq_db(&qp->wq);
  1090. return 0;
  1091. }
  1092. static void stop_queues(struct uld_ctx *ctx)
  1093. {
  1094. unsigned long flags;
  1095. spin_lock_irqsave(&ctx->dev->lock, flags);
  1096. ctx->dev->rdev.stats.db_state_transitions++;
  1097. ctx->dev->db_state = STOPPED;
  1098. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED)
  1099. idr_for_each(&ctx->dev->qpidr, disable_qp_db, NULL);
  1100. else
  1101. ctx->dev->rdev.status_page->db_off = 1;
  1102. spin_unlock_irqrestore(&ctx->dev->lock, flags);
  1103. }
  1104. static int enable_qp_db(int id, void *p, void *data)
  1105. {
  1106. struct c4iw_qp *qp = p;
  1107. t4_enable_wq_db(&qp->wq);
  1108. return 0;
  1109. }
  1110. static void resume_rc_qp(struct c4iw_qp *qp)
  1111. {
  1112. spin_lock(&qp->lock);
  1113. t4_ring_sq_db(&qp->wq, qp->wq.sq.wq_pidx_inc,
  1114. is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
  1115. qp->wq.sq.wq_pidx_inc = 0;
  1116. t4_ring_rq_db(&qp->wq, qp->wq.rq.wq_pidx_inc,
  1117. is_t5(qp->rhp->rdev.lldi.adapter_type), NULL);
  1118. qp->wq.rq.wq_pidx_inc = 0;
  1119. spin_unlock(&qp->lock);
  1120. }
  1121. static void resume_a_chunk(struct uld_ctx *ctx)
  1122. {
  1123. int i;
  1124. struct c4iw_qp *qp;
  1125. for (i = 0; i < DB_FC_RESUME_SIZE; i++) {
  1126. qp = list_first_entry(&ctx->dev->db_fc_list, struct c4iw_qp,
  1127. db_fc_entry);
  1128. list_del_init(&qp->db_fc_entry);
  1129. resume_rc_qp(qp);
  1130. if (list_empty(&ctx->dev->db_fc_list))
  1131. break;
  1132. }
  1133. }
  1134. static void resume_queues(struct uld_ctx *ctx)
  1135. {
  1136. spin_lock_irq(&ctx->dev->lock);
  1137. if (ctx->dev->db_state != STOPPED)
  1138. goto out;
  1139. ctx->dev->db_state = FLOW_CONTROL;
  1140. while (1) {
  1141. if (list_empty(&ctx->dev->db_fc_list)) {
  1142. WARN_ON(ctx->dev->db_state != FLOW_CONTROL);
  1143. ctx->dev->db_state = NORMAL;
  1144. ctx->dev->rdev.stats.db_state_transitions++;
  1145. if (ctx->dev->rdev.flags & T4_STATUS_PAGE_DISABLED) {
  1146. idr_for_each(&ctx->dev->qpidr, enable_qp_db,
  1147. NULL);
  1148. } else {
  1149. ctx->dev->rdev.status_page->db_off = 0;
  1150. }
  1151. break;
  1152. } else {
  1153. if (cxgb4_dbfifo_count(ctx->dev->rdev.lldi.ports[0], 1)
  1154. < (ctx->dev->rdev.lldi.dbfifo_int_thresh <<
  1155. DB_FC_DRAIN_THRESH)) {
  1156. resume_a_chunk(ctx);
  1157. }
  1158. if (!list_empty(&ctx->dev->db_fc_list)) {
  1159. spin_unlock_irq(&ctx->dev->lock);
  1160. if (DB_FC_RESUME_DELAY) {
  1161. set_current_state(TASK_UNINTERRUPTIBLE);
  1162. schedule_timeout(DB_FC_RESUME_DELAY);
  1163. }
  1164. spin_lock_irq(&ctx->dev->lock);
  1165. if (ctx->dev->db_state != FLOW_CONTROL)
  1166. break;
  1167. }
  1168. }
  1169. }
  1170. out:
  1171. if (ctx->dev->db_state != NORMAL)
  1172. ctx->dev->rdev.stats.db_fc_interruptions++;
  1173. spin_unlock_irq(&ctx->dev->lock);
  1174. }
  1175. struct qp_list {
  1176. unsigned idx;
  1177. struct c4iw_qp **qps;
  1178. };
  1179. static int add_and_ref_qp(int id, void *p, void *data)
  1180. {
  1181. struct qp_list *qp_listp = data;
  1182. struct c4iw_qp *qp = p;
  1183. c4iw_qp_add_ref(&qp->ibqp);
  1184. qp_listp->qps[qp_listp->idx++] = qp;
  1185. return 0;
  1186. }
  1187. static int count_qps(int id, void *p, void *data)
  1188. {
  1189. unsigned *countp = data;
  1190. (*countp)++;
  1191. return 0;
  1192. }
  1193. static void deref_qps(struct qp_list *qp_list)
  1194. {
  1195. int idx;
  1196. for (idx = 0; idx < qp_list->idx; idx++)
  1197. c4iw_qp_rem_ref(&qp_list->qps[idx]->ibqp);
  1198. }
  1199. static void recover_lost_dbs(struct uld_ctx *ctx, struct qp_list *qp_list)
  1200. {
  1201. int idx;
  1202. int ret;
  1203. for (idx = 0; idx < qp_list->idx; idx++) {
  1204. struct c4iw_qp *qp = qp_list->qps[idx];
  1205. spin_lock_irq(&qp->rhp->lock);
  1206. spin_lock(&qp->lock);
  1207. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1208. qp->wq.sq.qid,
  1209. t4_sq_host_wq_pidx(&qp->wq),
  1210. t4_sq_wq_size(&qp->wq));
  1211. if (ret) {
  1212. pr_err(KERN_ERR MOD "%s: Fatal error - "
  1213. "DB overflow recovery failed - "
  1214. "error syncing SQ qid %u\n",
  1215. pci_name(ctx->lldi.pdev), qp->wq.sq.qid);
  1216. spin_unlock(&qp->lock);
  1217. spin_unlock_irq(&qp->rhp->lock);
  1218. return;
  1219. }
  1220. qp->wq.sq.wq_pidx_inc = 0;
  1221. ret = cxgb4_sync_txq_pidx(qp->rhp->rdev.lldi.ports[0],
  1222. qp->wq.rq.qid,
  1223. t4_rq_host_wq_pidx(&qp->wq),
  1224. t4_rq_wq_size(&qp->wq));
  1225. if (ret) {
  1226. pr_err(KERN_ERR MOD "%s: Fatal error - "
  1227. "DB overflow recovery failed - "
  1228. "error syncing RQ qid %u\n",
  1229. pci_name(ctx->lldi.pdev), qp->wq.rq.qid);
  1230. spin_unlock(&qp->lock);
  1231. spin_unlock_irq(&qp->rhp->lock);
  1232. return;
  1233. }
  1234. qp->wq.rq.wq_pidx_inc = 0;
  1235. spin_unlock(&qp->lock);
  1236. spin_unlock_irq(&qp->rhp->lock);
  1237. /* Wait for the dbfifo to drain */
  1238. while (cxgb4_dbfifo_count(qp->rhp->rdev.lldi.ports[0], 1) > 0) {
  1239. set_current_state(TASK_UNINTERRUPTIBLE);
  1240. schedule_timeout(usecs_to_jiffies(10));
  1241. }
  1242. }
  1243. }
  1244. static void recover_queues(struct uld_ctx *ctx)
  1245. {
  1246. int count = 0;
  1247. struct qp_list qp_list;
  1248. int ret;
  1249. /* slow everybody down */
  1250. set_current_state(TASK_UNINTERRUPTIBLE);
  1251. schedule_timeout(usecs_to_jiffies(1000));
  1252. /* flush the SGE contexts */
  1253. ret = cxgb4_flush_eq_cache(ctx->dev->rdev.lldi.ports[0]);
  1254. if (ret) {
  1255. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1256. pci_name(ctx->lldi.pdev));
  1257. return;
  1258. }
  1259. /* Count active queues so we can build a list of queues to recover */
  1260. spin_lock_irq(&ctx->dev->lock);
  1261. WARN_ON(ctx->dev->db_state != STOPPED);
  1262. ctx->dev->db_state = RECOVERY;
  1263. idr_for_each(&ctx->dev->qpidr, count_qps, &count);
  1264. qp_list.qps = kzalloc(count * sizeof *qp_list.qps, GFP_ATOMIC);
  1265. if (!qp_list.qps) {
  1266. printk(KERN_ERR MOD "%s: Fatal error - DB overflow recovery failed\n",
  1267. pci_name(ctx->lldi.pdev));
  1268. spin_unlock_irq(&ctx->dev->lock);
  1269. return;
  1270. }
  1271. qp_list.idx = 0;
  1272. /* add and ref each qp so it doesn't get freed */
  1273. idr_for_each(&ctx->dev->qpidr, add_and_ref_qp, &qp_list);
  1274. spin_unlock_irq(&ctx->dev->lock);
  1275. /* now traverse the list in a safe context to recover the db state*/
  1276. recover_lost_dbs(ctx, &qp_list);
  1277. /* we're almost done! deref the qps and clean up */
  1278. deref_qps(&qp_list);
  1279. kfree(qp_list.qps);
  1280. spin_lock_irq(&ctx->dev->lock);
  1281. WARN_ON(ctx->dev->db_state != RECOVERY);
  1282. ctx->dev->db_state = STOPPED;
  1283. spin_unlock_irq(&ctx->dev->lock);
  1284. }
  1285. static int c4iw_uld_control(void *handle, enum cxgb4_control control, ...)
  1286. {
  1287. struct uld_ctx *ctx = handle;
  1288. switch (control) {
  1289. case CXGB4_CONTROL_DB_FULL:
  1290. stop_queues(ctx);
  1291. ctx->dev->rdev.stats.db_full++;
  1292. break;
  1293. case CXGB4_CONTROL_DB_EMPTY:
  1294. resume_queues(ctx);
  1295. mutex_lock(&ctx->dev->rdev.stats.lock);
  1296. ctx->dev->rdev.stats.db_empty++;
  1297. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1298. break;
  1299. case CXGB4_CONTROL_DB_DROP:
  1300. recover_queues(ctx);
  1301. mutex_lock(&ctx->dev->rdev.stats.lock);
  1302. ctx->dev->rdev.stats.db_drop++;
  1303. mutex_unlock(&ctx->dev->rdev.stats.lock);
  1304. break;
  1305. default:
  1306. printk(KERN_WARNING MOD "%s: unknown control cmd %u\n",
  1307. pci_name(ctx->lldi.pdev), control);
  1308. break;
  1309. }
  1310. return 0;
  1311. }
  1312. static struct cxgb4_uld_info c4iw_uld_info = {
  1313. .name = DRV_NAME,
  1314. .add = c4iw_uld_add,
  1315. .rx_handler = c4iw_uld_rx_handler,
  1316. .state_change = c4iw_uld_state_change,
  1317. .control = c4iw_uld_control,
  1318. };
  1319. static int __init c4iw_init_module(void)
  1320. {
  1321. int err;
  1322. err = c4iw_cm_init();
  1323. if (err)
  1324. return err;
  1325. c4iw_debugfs_root = debugfs_create_dir(DRV_NAME, NULL);
  1326. if (!c4iw_debugfs_root)
  1327. printk(KERN_WARNING MOD
  1328. "could not create debugfs entry, continuing\n");
  1329. if (ibnl_add_client(RDMA_NL_C4IW, RDMA_NL_IWPM_NUM_OPS,
  1330. c4iw_nl_cb_table))
  1331. pr_err("%s[%u]: Failed to add netlink callback\n"
  1332. , __func__, __LINE__);
  1333. err = iwpm_init(RDMA_NL_C4IW);
  1334. if (err) {
  1335. pr_err("port mapper initialization failed with %d\n", err);
  1336. ibnl_remove_client(RDMA_NL_C4IW);
  1337. c4iw_cm_term();
  1338. debugfs_remove_recursive(c4iw_debugfs_root);
  1339. return err;
  1340. }
  1341. cxgb4_register_uld(CXGB4_ULD_RDMA, &c4iw_uld_info);
  1342. return 0;
  1343. }
  1344. static void __exit c4iw_exit_module(void)
  1345. {
  1346. struct uld_ctx *ctx, *tmp;
  1347. mutex_lock(&dev_mutex);
  1348. list_for_each_entry_safe(ctx, tmp, &uld_ctx_list, entry) {
  1349. if (ctx->dev)
  1350. c4iw_remove(ctx);
  1351. kfree(ctx);
  1352. }
  1353. mutex_unlock(&dev_mutex);
  1354. cxgb4_unregister_uld(CXGB4_ULD_RDMA);
  1355. iwpm_exit(RDMA_NL_C4IW);
  1356. ibnl_remove_client(RDMA_NL_C4IW);
  1357. c4iw_cm_term();
  1358. debugfs_remove_recursive(c4iw_debugfs_root);
  1359. }
  1360. module_init(c4iw_init_module);
  1361. module_exit(c4iw_exit_module);