sti_hdmi.c 21 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2014
  3. * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
  4. * License terms: GNU General Public License (GPL), version 2
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/component.h>
  8. #include <linux/hdmi.h>
  9. #include <linux/module.h>
  10. #include <linux/of_gpio.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reset.h>
  13. #include <drm/drmP.h>
  14. #include <drm/drm_crtc_helper.h>
  15. #include <drm/drm_edid.h>
  16. #include "sti_hdmi.h"
  17. #include "sti_hdmi_tx3g4c28phy.h"
  18. #include "sti_hdmi_tx3g0c55phy.h"
  19. #include "sti_vtg.h"
  20. #define HDMI_CFG 0x0000
  21. #define HDMI_INT_EN 0x0004
  22. #define HDMI_INT_STA 0x0008
  23. #define HDMI_INT_CLR 0x000C
  24. #define HDMI_STA 0x0010
  25. #define HDMI_ACTIVE_VID_XMIN 0x0100
  26. #define HDMI_ACTIVE_VID_XMAX 0x0104
  27. #define HDMI_ACTIVE_VID_YMIN 0x0108
  28. #define HDMI_ACTIVE_VID_YMAX 0x010C
  29. #define HDMI_DFLT_CHL0_DAT 0x0110
  30. #define HDMI_DFLT_CHL1_DAT 0x0114
  31. #define HDMI_DFLT_CHL2_DAT 0x0118
  32. #define HDMI_SW_DI_1_HEAD_WORD 0x0210
  33. #define HDMI_SW_DI_1_PKT_WORD0 0x0214
  34. #define HDMI_SW_DI_1_PKT_WORD1 0x0218
  35. #define HDMI_SW_DI_1_PKT_WORD2 0x021C
  36. #define HDMI_SW_DI_1_PKT_WORD3 0x0220
  37. #define HDMI_SW_DI_1_PKT_WORD4 0x0224
  38. #define HDMI_SW_DI_1_PKT_WORD5 0x0228
  39. #define HDMI_SW_DI_1_PKT_WORD6 0x022C
  40. #define HDMI_SW_DI_CFG 0x0230
  41. #define HDMI_IFRAME_SLOT_AVI 1
  42. #define XCAT(prefix, x, suffix) prefix ## x ## suffix
  43. #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  44. #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  45. #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  46. #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  47. #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  48. #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  49. #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  50. #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  51. #define HDMI_IFRAME_DISABLED 0x0
  52. #define HDMI_IFRAME_SINGLE_SHOT 0x1
  53. #define HDMI_IFRAME_FIELD 0x2
  54. #define HDMI_IFRAME_FRAME 0x3
  55. #define HDMI_IFRAME_MASK 0x3
  56. #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
  57. #define HDMI_CFG_DEVICE_EN BIT(0)
  58. #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
  59. #define HDMI_CFG_HDCP_EN BIT(2)
  60. #define HDMI_CFG_ESS_NOT_OESS BIT(3)
  61. #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
  62. #define HDMI_CFG_SINK_TERM_DET_EN BIT(5)
  63. #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
  64. #define HDMI_CFG_422_EN BIT(8)
  65. #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
  66. #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
  67. #define HDMI_CFG_SW_RST_EN BIT(31)
  68. #define HDMI_INT_GLOBAL BIT(0)
  69. #define HDMI_INT_SW_RST BIT(1)
  70. #define HDMI_INT_PIX_CAP BIT(3)
  71. #define HDMI_INT_HOT_PLUG BIT(4)
  72. #define HDMI_INT_DLL_LCK BIT(5)
  73. #define HDMI_INT_NEW_FRAME BIT(6)
  74. #define HDMI_INT_GENCTRL_PKT BIT(7)
  75. #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
  76. #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
  77. | HDMI_INT_DLL_LCK \
  78. | HDMI_INT_HOT_PLUG \
  79. | HDMI_INT_GLOBAL)
  80. #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
  81. | HDMI_INT_GENCTRL_PKT \
  82. | HDMI_INT_NEW_FRAME \
  83. | HDMI_INT_DLL_LCK \
  84. | HDMI_INT_HOT_PLUG \
  85. | HDMI_INT_PIX_CAP \
  86. | HDMI_INT_SW_RST \
  87. | HDMI_INT_GLOBAL)
  88. #define HDMI_STA_SW_RST BIT(1)
  89. struct sti_hdmi_connector {
  90. struct drm_connector drm_connector;
  91. struct drm_encoder *encoder;
  92. struct sti_hdmi *hdmi;
  93. };
  94. #define to_sti_hdmi_connector(x) \
  95. container_of(x, struct sti_hdmi_connector, drm_connector)
  96. u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
  97. {
  98. return readl(hdmi->regs + offset);
  99. }
  100. void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
  101. {
  102. writel(val, hdmi->regs + offset);
  103. }
  104. /**
  105. * HDMI interrupt handler threaded
  106. *
  107. * @irq: irq number
  108. * @arg: connector structure
  109. */
  110. static irqreturn_t hdmi_irq_thread(int irq, void *arg)
  111. {
  112. struct sti_hdmi *hdmi = arg;
  113. /* Hot plug/unplug IRQ */
  114. if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
  115. hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
  116. if (hdmi->drm_dev)
  117. drm_helper_hpd_irq_event(hdmi->drm_dev);
  118. }
  119. /* Sw reset and PLL lock are exclusive so we can use the same
  120. * event to signal them
  121. */
  122. if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
  123. hdmi->event_received = true;
  124. wake_up_interruptible(&hdmi->wait_event);
  125. }
  126. return IRQ_HANDLED;
  127. }
  128. /**
  129. * HDMI interrupt handler
  130. *
  131. * @irq: irq number
  132. * @arg: connector structure
  133. */
  134. static irqreturn_t hdmi_irq(int irq, void *arg)
  135. {
  136. struct sti_hdmi *hdmi = arg;
  137. /* read interrupt status */
  138. hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
  139. /* clear interrupt status */
  140. hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
  141. /* force sync bus write */
  142. hdmi_read(hdmi, HDMI_INT_STA);
  143. return IRQ_WAKE_THREAD;
  144. }
  145. /**
  146. * Set hdmi active area depending on the drm display mode selected
  147. *
  148. * @hdmi: pointer on the hdmi internal structure
  149. */
  150. static void hdmi_active_area(struct sti_hdmi *hdmi)
  151. {
  152. u32 xmin, xmax;
  153. u32 ymin, ymax;
  154. xmin = sti_vtg_get_pixel_number(hdmi->mode, 0);
  155. xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay - 1);
  156. ymin = sti_vtg_get_line_number(hdmi->mode, 0);
  157. ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
  158. hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
  159. hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
  160. hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
  161. hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
  162. }
  163. /**
  164. * Overall hdmi configuration
  165. *
  166. * @hdmi: pointer on the hdmi internal structure
  167. */
  168. static void hdmi_config(struct sti_hdmi *hdmi)
  169. {
  170. u32 conf;
  171. DRM_DEBUG_DRIVER("\n");
  172. /* Clear overrun and underrun fifo */
  173. conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
  174. /* Enable HDMI mode not DVI */
  175. conf |= HDMI_CFG_HDMI_NOT_DVI | HDMI_CFG_ESS_NOT_OESS;
  176. /* Enable sink term detection */
  177. conf |= HDMI_CFG_SINK_TERM_DET_EN;
  178. /* Set Hsync polarity */
  179. if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
  180. DRM_DEBUG_DRIVER("H Sync Negative\n");
  181. conf |= HDMI_CFG_H_SYNC_POL_NEG;
  182. }
  183. /* Set Vsync polarity */
  184. if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
  185. DRM_DEBUG_DRIVER("V Sync Negative\n");
  186. conf |= HDMI_CFG_V_SYNC_POL_NEG;
  187. }
  188. /* Enable HDMI */
  189. conf |= HDMI_CFG_DEVICE_EN;
  190. hdmi_write(hdmi, conf, HDMI_CFG);
  191. }
  192. /**
  193. * Prepare and configure the AVI infoframe
  194. *
  195. * AVI infoframe are transmitted at least once per two video field and
  196. * contains information about HDMI transmission mode such as color space,
  197. * colorimetry, ...
  198. *
  199. * @hdmi: pointer on the hdmi internal structure
  200. *
  201. * Return negative value if error occurs
  202. */
  203. static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
  204. {
  205. struct drm_display_mode *mode = &hdmi->mode;
  206. struct hdmi_avi_infoframe infoframe;
  207. u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  208. u8 *frame = buffer + HDMI_INFOFRAME_HEADER_SIZE;
  209. u32 val;
  210. int ret;
  211. DRM_DEBUG_DRIVER("\n");
  212. ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode);
  213. if (ret < 0) {
  214. DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
  215. return ret;
  216. }
  217. /* fixed infoframe configuration not linked to the mode */
  218. infoframe.colorspace = HDMI_COLORSPACE_RGB;
  219. infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  220. infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
  221. ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
  222. if (ret < 0) {
  223. DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
  224. return ret;
  225. }
  226. /* Disable transmission slot for AVI infoframe */
  227. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  228. val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, HDMI_IFRAME_SLOT_AVI);
  229. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  230. /* Infoframe header */
  231. val = buffer[0];
  232. val |= buffer[1] << 8;
  233. val |= buffer[2] << 16;
  234. hdmi_write(hdmi, val, HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI));
  235. /* Infoframe packet bytes */
  236. val = buffer[3];
  237. val |= *(frame++) << 8;
  238. val |= *(frame++) << 16;
  239. val |= *(frame++) << 24;
  240. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI));
  241. val = *(frame++);
  242. val |= *(frame++) << 8;
  243. val |= *(frame++) << 16;
  244. val |= *(frame++) << 24;
  245. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD1(HDMI_IFRAME_SLOT_AVI));
  246. val = *(frame++);
  247. val |= *(frame++) << 8;
  248. val |= *(frame++) << 16;
  249. val |= *(frame++) << 24;
  250. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD2(HDMI_IFRAME_SLOT_AVI));
  251. val = *(frame++);
  252. val |= *(frame) << 8;
  253. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD3(HDMI_IFRAME_SLOT_AVI));
  254. /* Enable transmission slot for AVI infoframe
  255. * According to the hdmi specification, AVI infoframe should be
  256. * transmitted at least once per two video fields
  257. */
  258. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  259. val |= HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_FIELD, HDMI_IFRAME_SLOT_AVI);
  260. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  261. return 0;
  262. }
  263. /**
  264. * Software reset of the hdmi subsystem
  265. *
  266. * @hdmi: pointer on the hdmi internal structure
  267. *
  268. */
  269. #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
  270. static void hdmi_swreset(struct sti_hdmi *hdmi)
  271. {
  272. u32 val;
  273. DRM_DEBUG_DRIVER("\n");
  274. /* Enable hdmi_audio clock only during hdmi reset */
  275. if (clk_prepare_enable(hdmi->clk_audio))
  276. DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
  277. /* Sw reset */
  278. hdmi->event_received = false;
  279. val = hdmi_read(hdmi, HDMI_CFG);
  280. val |= HDMI_CFG_SW_RST_EN;
  281. hdmi_write(hdmi, val, HDMI_CFG);
  282. /* Wait reset completed */
  283. wait_event_interruptible_timeout(hdmi->wait_event,
  284. hdmi->event_received == true,
  285. msecs_to_jiffies
  286. (HDMI_TIMEOUT_SWRESET));
  287. /*
  288. * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
  289. * set to '1' and clk_audio is running.
  290. */
  291. if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
  292. DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
  293. val = hdmi_read(hdmi, HDMI_CFG);
  294. val &= ~HDMI_CFG_SW_RST_EN;
  295. hdmi_write(hdmi, val, HDMI_CFG);
  296. /* Disable hdmi_audio clock. Not used anymore for drm purpose */
  297. clk_disable_unprepare(hdmi->clk_audio);
  298. }
  299. static void sti_hdmi_disable(struct drm_bridge *bridge)
  300. {
  301. struct sti_hdmi *hdmi = bridge->driver_private;
  302. u32 val = hdmi_read(hdmi, HDMI_CFG);
  303. if (!hdmi->enabled)
  304. return;
  305. DRM_DEBUG_DRIVER("\n");
  306. /* Disable HDMI */
  307. val &= ~HDMI_CFG_DEVICE_EN;
  308. hdmi_write(hdmi, val, HDMI_CFG);
  309. hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
  310. /* Stop the phy */
  311. hdmi->phy_ops->stop(hdmi);
  312. /* Set the default channel data to be a dark red */
  313. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
  314. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
  315. hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
  316. /* Disable/unprepare hdmi clock */
  317. clk_disable_unprepare(hdmi->clk_phy);
  318. clk_disable_unprepare(hdmi->clk_tmds);
  319. clk_disable_unprepare(hdmi->clk_pix);
  320. hdmi->enabled = false;
  321. }
  322. static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
  323. {
  324. struct sti_hdmi *hdmi = bridge->driver_private;
  325. DRM_DEBUG_DRIVER("\n");
  326. if (hdmi->enabled)
  327. return;
  328. /* Prepare/enable clocks */
  329. if (clk_prepare_enable(hdmi->clk_pix))
  330. DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
  331. if (clk_prepare_enable(hdmi->clk_tmds))
  332. DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
  333. if (clk_prepare_enable(hdmi->clk_phy))
  334. DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
  335. hdmi->enabled = true;
  336. /* Program hdmi serializer and start phy */
  337. if (!hdmi->phy_ops->start(hdmi)) {
  338. DRM_ERROR("Unable to start hdmi phy\n");
  339. return;
  340. }
  341. /* Program hdmi active area */
  342. hdmi_active_area(hdmi);
  343. /* Enable working interrupts */
  344. hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
  345. /* Program hdmi config */
  346. hdmi_config(hdmi);
  347. /* Program AVI infoframe */
  348. if (hdmi_avi_infoframe_config(hdmi))
  349. DRM_ERROR("Unable to configure AVI infoframe\n");
  350. /* Sw reset */
  351. hdmi_swreset(hdmi);
  352. }
  353. static void sti_hdmi_set_mode(struct drm_bridge *bridge,
  354. struct drm_display_mode *mode,
  355. struct drm_display_mode *adjusted_mode)
  356. {
  357. struct sti_hdmi *hdmi = bridge->driver_private;
  358. int ret;
  359. DRM_DEBUG_DRIVER("\n");
  360. /* Copy the drm display mode in the connector local structure */
  361. memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
  362. /* Update clock framerate according to the selected mode */
  363. ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
  364. if (ret < 0) {
  365. DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
  366. mode->clock * 1000);
  367. return;
  368. }
  369. ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
  370. if (ret < 0) {
  371. DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
  372. mode->clock * 1000);
  373. return;
  374. }
  375. }
  376. static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
  377. {
  378. /* do nothing */
  379. }
  380. static void sti_hdmi_brigde_destroy(struct drm_bridge *bridge)
  381. {
  382. drm_bridge_cleanup(bridge);
  383. kfree(bridge);
  384. }
  385. static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
  386. .pre_enable = sti_hdmi_pre_enable,
  387. .enable = sti_hdmi_bridge_nope,
  388. .disable = sti_hdmi_disable,
  389. .post_disable = sti_hdmi_bridge_nope,
  390. .mode_set = sti_hdmi_set_mode,
  391. .destroy = sti_hdmi_brigde_destroy,
  392. };
  393. static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
  394. {
  395. struct sti_hdmi_connector *hdmi_connector
  396. = to_sti_hdmi_connector(connector);
  397. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  398. struct edid *edid;
  399. int count;
  400. DRM_DEBUG_DRIVER("\n");
  401. edid = drm_get_edid(connector, hdmi->ddc_adapt);
  402. if (!edid)
  403. goto fail;
  404. count = drm_add_edid_modes(connector, edid);
  405. drm_mode_connector_update_edid_property(connector, edid);
  406. kfree(edid);
  407. return count;
  408. fail:
  409. DRM_ERROR("Can not read HDMI EDID\n");
  410. return 0;
  411. }
  412. #define CLK_TOLERANCE_HZ 50
  413. static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
  414. struct drm_display_mode *mode)
  415. {
  416. int target = mode->clock * 1000;
  417. int target_min = target - CLK_TOLERANCE_HZ;
  418. int target_max = target + CLK_TOLERANCE_HZ;
  419. int result;
  420. struct sti_hdmi_connector *hdmi_connector
  421. = to_sti_hdmi_connector(connector);
  422. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  423. result = clk_round_rate(hdmi->clk_pix, target);
  424. DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
  425. target, result);
  426. if ((result < target_min) || (result > target_max)) {
  427. DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
  428. return MODE_BAD;
  429. }
  430. return MODE_OK;
  431. }
  432. struct drm_encoder *sti_hdmi_best_encoder(struct drm_connector *connector)
  433. {
  434. struct sti_hdmi_connector *hdmi_connector
  435. = to_sti_hdmi_connector(connector);
  436. /* Best encoder is the one associated during connector creation */
  437. return hdmi_connector->encoder;
  438. }
  439. static struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
  440. .get_modes = sti_hdmi_connector_get_modes,
  441. .mode_valid = sti_hdmi_connector_mode_valid,
  442. .best_encoder = sti_hdmi_best_encoder,
  443. };
  444. /* get detection status of display device */
  445. static enum drm_connector_status
  446. sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
  447. {
  448. struct sti_hdmi_connector *hdmi_connector
  449. = to_sti_hdmi_connector(connector);
  450. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  451. DRM_DEBUG_DRIVER("\n");
  452. if (hdmi->hpd) {
  453. DRM_DEBUG_DRIVER("hdmi cable connected\n");
  454. return connector_status_connected;
  455. }
  456. DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
  457. return connector_status_disconnected;
  458. }
  459. static void sti_hdmi_connector_destroy(struct drm_connector *connector)
  460. {
  461. struct sti_hdmi_connector *hdmi_connector
  462. = to_sti_hdmi_connector(connector);
  463. drm_connector_unregister(connector);
  464. drm_connector_cleanup(connector);
  465. kfree(hdmi_connector);
  466. }
  467. static struct drm_connector_funcs sti_hdmi_connector_funcs = {
  468. .dpms = drm_helper_connector_dpms,
  469. .fill_modes = drm_helper_probe_single_connector_modes,
  470. .detect = sti_hdmi_connector_detect,
  471. .destroy = sti_hdmi_connector_destroy,
  472. };
  473. static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
  474. {
  475. struct drm_encoder *encoder;
  476. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  477. if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
  478. return encoder;
  479. }
  480. return NULL;
  481. }
  482. static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
  483. {
  484. struct sti_hdmi *hdmi = dev_get_drvdata(dev);
  485. struct drm_device *drm_dev = data;
  486. struct drm_encoder *encoder;
  487. struct sti_hdmi_connector *connector;
  488. struct drm_connector *drm_connector;
  489. struct drm_bridge *bridge;
  490. struct device_node *ddc;
  491. int err;
  492. ddc = of_parse_phandle(dev->of_node, "ddc", 0);
  493. if (ddc) {
  494. hdmi->ddc_adapt = of_find_i2c_adapter_by_node(ddc);
  495. if (!hdmi->ddc_adapt) {
  496. err = -EPROBE_DEFER;
  497. of_node_put(ddc);
  498. return err;
  499. }
  500. of_node_put(ddc);
  501. }
  502. /* Set the drm device handle */
  503. hdmi->drm_dev = drm_dev;
  504. encoder = sti_hdmi_find_encoder(drm_dev);
  505. if (!encoder)
  506. goto err_adapt;
  507. connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
  508. if (!connector)
  509. goto err_adapt;
  510. connector->hdmi = hdmi;
  511. bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
  512. if (!bridge)
  513. goto err_adapt;
  514. bridge->driver_private = hdmi;
  515. drm_bridge_init(drm_dev, bridge, &sti_hdmi_bridge_funcs);
  516. encoder->bridge = bridge;
  517. connector->encoder = encoder;
  518. drm_connector = (struct drm_connector *)connector;
  519. drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
  520. drm_connector_init(drm_dev, drm_connector,
  521. &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
  522. drm_connector_helper_add(drm_connector,
  523. &sti_hdmi_connector_helper_funcs);
  524. err = drm_connector_register(drm_connector);
  525. if (err)
  526. goto err_connector;
  527. err = drm_mode_connector_attach_encoder(drm_connector, encoder);
  528. if (err) {
  529. DRM_ERROR("Failed to attach a connector to a encoder\n");
  530. goto err_sysfs;
  531. }
  532. /* Enable default interrupts */
  533. hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
  534. return 0;
  535. err_sysfs:
  536. drm_connector_unregister(drm_connector);
  537. err_connector:
  538. drm_bridge_cleanup(bridge);
  539. drm_connector_cleanup(drm_connector);
  540. err_adapt:
  541. put_device(&hdmi->ddc_adapt->dev);
  542. return -EINVAL;
  543. }
  544. static void sti_hdmi_unbind(struct device *dev,
  545. struct device *master, void *data)
  546. {
  547. /* do nothing */
  548. }
  549. static const struct component_ops sti_hdmi_ops = {
  550. .bind = sti_hdmi_bind,
  551. .unbind = sti_hdmi_unbind,
  552. };
  553. static const struct of_device_id hdmi_of_match[] = {
  554. {
  555. .compatible = "st,stih416-hdmi",
  556. .data = &tx3g0c55phy_ops,
  557. }, {
  558. .compatible = "st,stih407-hdmi",
  559. .data = &tx3g4c28phy_ops,
  560. }, {
  561. /* end node */
  562. }
  563. };
  564. MODULE_DEVICE_TABLE(of, hdmi_of_match);
  565. static int sti_hdmi_probe(struct platform_device *pdev)
  566. {
  567. struct device *dev = &pdev->dev;
  568. struct sti_hdmi *hdmi;
  569. struct device_node *np = dev->of_node;
  570. struct resource *res;
  571. int ret;
  572. DRM_INFO("%s\n", __func__);
  573. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  574. if (!hdmi)
  575. return -ENOMEM;
  576. hdmi->dev = pdev->dev;
  577. /* Get resources */
  578. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
  579. if (!res) {
  580. DRM_ERROR("Invalid hdmi resource\n");
  581. return -ENOMEM;
  582. }
  583. hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
  584. if (!hdmi->regs)
  585. return -ENOMEM;
  586. if (of_device_is_compatible(np, "st,stih416-hdmi")) {
  587. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  588. "syscfg");
  589. if (!res) {
  590. DRM_ERROR("Invalid syscfg resource\n");
  591. return -ENOMEM;
  592. }
  593. hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
  594. resource_size(res));
  595. if (!hdmi->syscfg)
  596. return -ENOMEM;
  597. }
  598. hdmi->phy_ops = (struct hdmi_phy_ops *)
  599. of_match_node(hdmi_of_match, np)->data;
  600. /* Get clock resources */
  601. hdmi->clk_pix = devm_clk_get(dev, "pix");
  602. if (IS_ERR(hdmi->clk_pix)) {
  603. DRM_ERROR("Cannot get hdmi_pix clock\n");
  604. return PTR_ERR(hdmi->clk_pix);
  605. }
  606. hdmi->clk_tmds = devm_clk_get(dev, "tmds");
  607. if (IS_ERR(hdmi->clk_tmds)) {
  608. DRM_ERROR("Cannot get hdmi_tmds clock\n");
  609. return PTR_ERR(hdmi->clk_tmds);
  610. }
  611. hdmi->clk_phy = devm_clk_get(dev, "phy");
  612. if (IS_ERR(hdmi->clk_phy)) {
  613. DRM_ERROR("Cannot get hdmi_phy clock\n");
  614. return PTR_ERR(hdmi->clk_phy);
  615. }
  616. hdmi->clk_audio = devm_clk_get(dev, "audio");
  617. if (IS_ERR(hdmi->clk_audio)) {
  618. DRM_ERROR("Cannot get hdmi_audio clock\n");
  619. return PTR_ERR(hdmi->clk_audio);
  620. }
  621. hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
  622. init_waitqueue_head(&hdmi->wait_event);
  623. hdmi->irq = platform_get_irq_byname(pdev, "irq");
  624. ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
  625. hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
  626. if (ret) {
  627. DRM_ERROR("Failed to register HDMI interrupt\n");
  628. return ret;
  629. }
  630. hdmi->reset = devm_reset_control_get(dev, "hdmi");
  631. /* Take hdmi out of reset */
  632. if (!IS_ERR(hdmi->reset))
  633. reset_control_deassert(hdmi->reset);
  634. platform_set_drvdata(pdev, hdmi);
  635. return component_add(&pdev->dev, &sti_hdmi_ops);
  636. }
  637. static int sti_hdmi_remove(struct platform_device *pdev)
  638. {
  639. struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
  640. if (hdmi->ddc_adapt)
  641. put_device(&hdmi->ddc_adapt->dev);
  642. component_del(&pdev->dev, &sti_hdmi_ops);
  643. return 0;
  644. }
  645. struct platform_driver sti_hdmi_driver = {
  646. .driver = {
  647. .name = "sti-hdmi",
  648. .owner = THIS_MODULE,
  649. .of_match_table = hdmi_of_match,
  650. },
  651. .probe = sti_hdmi_probe,
  652. .remove = sti_hdmi_remove,
  653. };
  654. module_platform_driver(sti_hdmi_driver);
  655. MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
  656. MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
  657. MODULE_LICENSE("GPL");