msm_drv.c 24 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "msm_drv.h"
  18. #include "msm_gpu.h"
  19. #include "msm_kms.h"
  20. static void msm_fb_output_poll_changed(struct drm_device *dev)
  21. {
  22. struct msm_drm_private *priv = dev->dev_private;
  23. if (priv->fbdev)
  24. drm_fb_helper_hotplug_event(priv->fbdev);
  25. }
  26. static const struct drm_mode_config_funcs mode_config_funcs = {
  27. .fb_create = msm_framebuffer_create,
  28. .output_poll_changed = msm_fb_output_poll_changed,
  29. .atomic_check = drm_atomic_helper_check,
  30. .atomic_commit = msm_atomic_commit,
  31. };
  32. int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
  33. {
  34. struct msm_drm_private *priv = dev->dev_private;
  35. int idx = priv->num_mmus++;
  36. if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
  37. return -EINVAL;
  38. priv->mmus[idx] = mmu;
  39. return idx;
  40. }
  41. #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
  42. static bool reglog = false;
  43. MODULE_PARM_DESC(reglog, "Enable register read/write logging");
  44. module_param(reglog, bool, 0600);
  45. #else
  46. #define reglog 0
  47. #endif
  48. static char *vram = "16m";
  49. MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
  50. module_param(vram, charp, 0);
  51. /*
  52. * Util/helpers:
  53. */
  54. void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
  55. const char *dbgname)
  56. {
  57. struct resource *res;
  58. unsigned long size;
  59. void __iomem *ptr;
  60. if (name)
  61. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  62. else
  63. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  64. if (!res) {
  65. dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
  66. return ERR_PTR(-EINVAL);
  67. }
  68. size = resource_size(res);
  69. ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
  70. if (!ptr) {
  71. dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
  72. return ERR_PTR(-ENOMEM);
  73. }
  74. if (reglog)
  75. printk(KERN_DEBUG "IO:region %s %08x %08lx\n", dbgname, (u32)ptr, size);
  76. return ptr;
  77. }
  78. void msm_writel(u32 data, void __iomem *addr)
  79. {
  80. if (reglog)
  81. printk(KERN_DEBUG "IO:W %08x %08x\n", (u32)addr, data);
  82. writel(data, addr);
  83. }
  84. u32 msm_readl(const void __iomem *addr)
  85. {
  86. u32 val = readl(addr);
  87. if (reglog)
  88. printk(KERN_ERR "IO:R %08x %08x\n", (u32)addr, val);
  89. return val;
  90. }
  91. /*
  92. * DRM operations:
  93. */
  94. static int msm_unload(struct drm_device *dev)
  95. {
  96. struct msm_drm_private *priv = dev->dev_private;
  97. struct msm_kms *kms = priv->kms;
  98. struct msm_gpu *gpu = priv->gpu;
  99. drm_kms_helper_poll_fini(dev);
  100. drm_mode_config_cleanup(dev);
  101. drm_vblank_cleanup(dev);
  102. pm_runtime_get_sync(dev->dev);
  103. drm_irq_uninstall(dev);
  104. pm_runtime_put_sync(dev->dev);
  105. flush_workqueue(priv->wq);
  106. destroy_workqueue(priv->wq);
  107. if (kms) {
  108. pm_runtime_disable(dev->dev);
  109. kms->funcs->destroy(kms);
  110. }
  111. if (gpu) {
  112. mutex_lock(&dev->struct_mutex);
  113. gpu->funcs->pm_suspend(gpu);
  114. gpu->funcs->destroy(gpu);
  115. mutex_unlock(&dev->struct_mutex);
  116. }
  117. if (priv->vram.paddr) {
  118. DEFINE_DMA_ATTRS(attrs);
  119. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  120. drm_mm_takedown(&priv->vram.mm);
  121. dma_free_attrs(dev->dev, priv->vram.size, NULL,
  122. priv->vram.paddr, &attrs);
  123. }
  124. component_unbind_all(dev->dev, dev);
  125. dev->dev_private = NULL;
  126. kfree(priv);
  127. return 0;
  128. }
  129. static int get_mdp_ver(struct platform_device *pdev)
  130. {
  131. #ifdef CONFIG_OF
  132. static const struct of_device_id match_types[] = { {
  133. .compatible = "qcom,mdss_mdp",
  134. .data = (void *)5,
  135. }, {
  136. /* end node */
  137. } };
  138. struct device *dev = &pdev->dev;
  139. const struct of_device_id *match;
  140. match = of_match_node(match_types, dev->of_node);
  141. if (match)
  142. return (int)match->data;
  143. #endif
  144. return 4;
  145. }
  146. static int msm_load(struct drm_device *dev, unsigned long flags)
  147. {
  148. struct platform_device *pdev = dev->platformdev;
  149. struct msm_drm_private *priv;
  150. struct msm_kms *kms;
  151. int ret;
  152. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  153. if (!priv) {
  154. dev_err(dev->dev, "failed to allocate private data\n");
  155. return -ENOMEM;
  156. }
  157. dev->dev_private = priv;
  158. priv->wq = alloc_ordered_workqueue("msm", 0);
  159. init_waitqueue_head(&priv->fence_event);
  160. init_waitqueue_head(&priv->pending_crtcs_event);
  161. INIT_LIST_HEAD(&priv->inactive_list);
  162. INIT_LIST_HEAD(&priv->fence_cbs);
  163. drm_mode_config_init(dev);
  164. /* if we have no IOMMU, then we need to use carveout allocator.
  165. * Grab the entire CMA chunk carved out in early startup in
  166. * mach-msm:
  167. */
  168. if (!iommu_present(&platform_bus_type)) {
  169. DEFINE_DMA_ATTRS(attrs);
  170. unsigned long size;
  171. void *p;
  172. DBG("using %s VRAM carveout", vram);
  173. size = memparse(vram, NULL);
  174. priv->vram.size = size;
  175. drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
  176. dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
  177. dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
  178. /* note that for no-kernel-mapping, the vaddr returned
  179. * is bogus, but non-null if allocation succeeded:
  180. */
  181. p = dma_alloc_attrs(dev->dev, size,
  182. &priv->vram.paddr, GFP_KERNEL, &attrs);
  183. if (!p) {
  184. dev_err(dev->dev, "failed to allocate VRAM\n");
  185. priv->vram.paddr = 0;
  186. ret = -ENOMEM;
  187. goto fail;
  188. }
  189. dev_info(dev->dev, "VRAM: %08x->%08x\n",
  190. (uint32_t)priv->vram.paddr,
  191. (uint32_t)(priv->vram.paddr + size));
  192. }
  193. platform_set_drvdata(pdev, dev);
  194. /* Bind all our sub-components: */
  195. ret = component_bind_all(dev->dev, dev);
  196. if (ret)
  197. return ret;
  198. switch (get_mdp_ver(pdev)) {
  199. case 4:
  200. kms = mdp4_kms_init(dev);
  201. break;
  202. case 5:
  203. kms = mdp5_kms_init(dev);
  204. break;
  205. default:
  206. kms = ERR_PTR(-ENODEV);
  207. break;
  208. }
  209. if (IS_ERR(kms)) {
  210. /*
  211. * NOTE: once we have GPU support, having no kms should not
  212. * be considered fatal.. ideally we would still support gpu
  213. * and (for example) use dmabuf/prime to share buffers with
  214. * imx drm driver on iMX5
  215. */
  216. dev_err(dev->dev, "failed to load kms\n");
  217. ret = PTR_ERR(kms);
  218. goto fail;
  219. }
  220. priv->kms = kms;
  221. if (kms) {
  222. pm_runtime_enable(dev->dev);
  223. ret = kms->funcs->hw_init(kms);
  224. if (ret) {
  225. dev_err(dev->dev, "kms hw init failed: %d\n", ret);
  226. goto fail;
  227. }
  228. }
  229. dev->mode_config.min_width = 0;
  230. dev->mode_config.min_height = 0;
  231. dev->mode_config.max_width = 2048;
  232. dev->mode_config.max_height = 2048;
  233. dev->mode_config.funcs = &mode_config_funcs;
  234. ret = drm_vblank_init(dev, priv->num_crtcs);
  235. if (ret < 0) {
  236. dev_err(dev->dev, "failed to initialize vblank\n");
  237. goto fail;
  238. }
  239. pm_runtime_get_sync(dev->dev);
  240. ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
  241. pm_runtime_put_sync(dev->dev);
  242. if (ret < 0) {
  243. dev_err(dev->dev, "failed to install IRQ handler\n");
  244. goto fail;
  245. }
  246. drm_mode_config_reset(dev);
  247. #ifdef CONFIG_DRM_MSM_FBDEV
  248. priv->fbdev = msm_fbdev_init(dev);
  249. #endif
  250. ret = msm_debugfs_late_init(dev);
  251. if (ret)
  252. goto fail;
  253. drm_kms_helper_poll_init(dev);
  254. return 0;
  255. fail:
  256. msm_unload(dev);
  257. return ret;
  258. }
  259. static void load_gpu(struct drm_device *dev)
  260. {
  261. static DEFINE_MUTEX(init_lock);
  262. struct msm_drm_private *priv = dev->dev_private;
  263. mutex_lock(&init_lock);
  264. if (!priv->gpu)
  265. priv->gpu = adreno_load_gpu(dev);
  266. mutex_unlock(&init_lock);
  267. }
  268. static int msm_open(struct drm_device *dev, struct drm_file *file)
  269. {
  270. struct msm_file_private *ctx;
  271. /* For now, load gpu on open.. to avoid the requirement of having
  272. * firmware in the initrd.
  273. */
  274. load_gpu(dev);
  275. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  276. if (!ctx)
  277. return -ENOMEM;
  278. file->driver_priv = ctx;
  279. return 0;
  280. }
  281. static void msm_preclose(struct drm_device *dev, struct drm_file *file)
  282. {
  283. struct msm_drm_private *priv = dev->dev_private;
  284. struct msm_file_private *ctx = file->driver_priv;
  285. struct msm_kms *kms = priv->kms;
  286. if (kms)
  287. kms->funcs->preclose(kms, file);
  288. mutex_lock(&dev->struct_mutex);
  289. if (ctx == priv->lastctx)
  290. priv->lastctx = NULL;
  291. mutex_unlock(&dev->struct_mutex);
  292. kfree(ctx);
  293. }
  294. static void msm_lastclose(struct drm_device *dev)
  295. {
  296. struct msm_drm_private *priv = dev->dev_private;
  297. if (priv->fbdev)
  298. drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  299. }
  300. static irqreturn_t msm_irq(int irq, void *arg)
  301. {
  302. struct drm_device *dev = arg;
  303. struct msm_drm_private *priv = dev->dev_private;
  304. struct msm_kms *kms = priv->kms;
  305. BUG_ON(!kms);
  306. return kms->funcs->irq(kms);
  307. }
  308. static void msm_irq_preinstall(struct drm_device *dev)
  309. {
  310. struct msm_drm_private *priv = dev->dev_private;
  311. struct msm_kms *kms = priv->kms;
  312. BUG_ON(!kms);
  313. kms->funcs->irq_preinstall(kms);
  314. }
  315. static int msm_irq_postinstall(struct drm_device *dev)
  316. {
  317. struct msm_drm_private *priv = dev->dev_private;
  318. struct msm_kms *kms = priv->kms;
  319. BUG_ON(!kms);
  320. return kms->funcs->irq_postinstall(kms);
  321. }
  322. static void msm_irq_uninstall(struct drm_device *dev)
  323. {
  324. struct msm_drm_private *priv = dev->dev_private;
  325. struct msm_kms *kms = priv->kms;
  326. BUG_ON(!kms);
  327. kms->funcs->irq_uninstall(kms);
  328. }
  329. static int msm_enable_vblank(struct drm_device *dev, int crtc_id)
  330. {
  331. struct msm_drm_private *priv = dev->dev_private;
  332. struct msm_kms *kms = priv->kms;
  333. if (!kms)
  334. return -ENXIO;
  335. DBG("dev=%p, crtc=%d", dev, crtc_id);
  336. return kms->funcs->enable_vblank(kms, priv->crtcs[crtc_id]);
  337. }
  338. static void msm_disable_vblank(struct drm_device *dev, int crtc_id)
  339. {
  340. struct msm_drm_private *priv = dev->dev_private;
  341. struct msm_kms *kms = priv->kms;
  342. if (!kms)
  343. return;
  344. DBG("dev=%p, crtc=%d", dev, crtc_id);
  345. kms->funcs->disable_vblank(kms, priv->crtcs[crtc_id]);
  346. }
  347. /*
  348. * DRM debugfs:
  349. */
  350. #ifdef CONFIG_DEBUG_FS
  351. static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
  352. {
  353. struct msm_drm_private *priv = dev->dev_private;
  354. struct msm_gpu *gpu = priv->gpu;
  355. if (gpu) {
  356. seq_printf(m, "%s Status:\n", gpu->name);
  357. gpu->funcs->show(gpu, m);
  358. }
  359. return 0;
  360. }
  361. static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
  362. {
  363. struct msm_drm_private *priv = dev->dev_private;
  364. struct msm_gpu *gpu = priv->gpu;
  365. if (gpu) {
  366. seq_printf(m, "Active Objects (%s):\n", gpu->name);
  367. msm_gem_describe_objects(&gpu->active_list, m);
  368. }
  369. seq_printf(m, "Inactive Objects:\n");
  370. msm_gem_describe_objects(&priv->inactive_list, m);
  371. return 0;
  372. }
  373. static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
  374. {
  375. return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
  376. }
  377. static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
  378. {
  379. struct msm_drm_private *priv = dev->dev_private;
  380. struct drm_framebuffer *fb, *fbdev_fb = NULL;
  381. if (priv->fbdev) {
  382. seq_printf(m, "fbcon ");
  383. fbdev_fb = priv->fbdev->fb;
  384. msm_framebuffer_describe(fbdev_fb, m);
  385. }
  386. mutex_lock(&dev->mode_config.fb_lock);
  387. list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
  388. if (fb == fbdev_fb)
  389. continue;
  390. seq_printf(m, "user ");
  391. msm_framebuffer_describe(fb, m);
  392. }
  393. mutex_unlock(&dev->mode_config.fb_lock);
  394. return 0;
  395. }
  396. static int show_locked(struct seq_file *m, void *arg)
  397. {
  398. struct drm_info_node *node = (struct drm_info_node *) m->private;
  399. struct drm_device *dev = node->minor->dev;
  400. int (*show)(struct drm_device *dev, struct seq_file *m) =
  401. node->info_ent->data;
  402. int ret;
  403. ret = mutex_lock_interruptible(&dev->struct_mutex);
  404. if (ret)
  405. return ret;
  406. ret = show(dev, m);
  407. mutex_unlock(&dev->struct_mutex);
  408. return ret;
  409. }
  410. static struct drm_info_list msm_debugfs_list[] = {
  411. {"gpu", show_locked, 0, msm_gpu_show},
  412. {"gem", show_locked, 0, msm_gem_show},
  413. { "mm", show_locked, 0, msm_mm_show },
  414. { "fb", show_locked, 0, msm_fb_show },
  415. };
  416. static int late_init_minor(struct drm_minor *minor)
  417. {
  418. int ret;
  419. if (!minor)
  420. return 0;
  421. ret = msm_rd_debugfs_init(minor);
  422. if (ret) {
  423. dev_err(minor->dev->dev, "could not install rd debugfs\n");
  424. return ret;
  425. }
  426. ret = msm_perf_debugfs_init(minor);
  427. if (ret) {
  428. dev_err(minor->dev->dev, "could not install perf debugfs\n");
  429. return ret;
  430. }
  431. return 0;
  432. }
  433. int msm_debugfs_late_init(struct drm_device *dev)
  434. {
  435. int ret;
  436. ret = late_init_minor(dev->primary);
  437. if (ret)
  438. return ret;
  439. ret = late_init_minor(dev->render);
  440. if (ret)
  441. return ret;
  442. ret = late_init_minor(dev->control);
  443. return ret;
  444. }
  445. static int msm_debugfs_init(struct drm_minor *minor)
  446. {
  447. struct drm_device *dev = minor->dev;
  448. int ret;
  449. ret = drm_debugfs_create_files(msm_debugfs_list,
  450. ARRAY_SIZE(msm_debugfs_list),
  451. minor->debugfs_root, minor);
  452. if (ret) {
  453. dev_err(dev->dev, "could not install msm_debugfs_list\n");
  454. return ret;
  455. }
  456. return 0;
  457. }
  458. static void msm_debugfs_cleanup(struct drm_minor *minor)
  459. {
  460. drm_debugfs_remove_files(msm_debugfs_list,
  461. ARRAY_SIZE(msm_debugfs_list), minor);
  462. if (!minor->dev->dev_private)
  463. return;
  464. msm_rd_debugfs_cleanup(minor);
  465. msm_perf_debugfs_cleanup(minor);
  466. }
  467. #endif
  468. /*
  469. * Fences:
  470. */
  471. int msm_wait_fence_interruptable(struct drm_device *dev, uint32_t fence,
  472. struct timespec *timeout)
  473. {
  474. struct msm_drm_private *priv = dev->dev_private;
  475. int ret;
  476. if (!priv->gpu)
  477. return 0;
  478. if (fence > priv->gpu->submitted_fence) {
  479. DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
  480. fence, priv->gpu->submitted_fence);
  481. return -EINVAL;
  482. }
  483. if (!timeout) {
  484. /* no-wait: */
  485. ret = fence_completed(dev, fence) ? 0 : -EBUSY;
  486. } else {
  487. unsigned long timeout_jiffies = timespec_to_jiffies(timeout);
  488. unsigned long start_jiffies = jiffies;
  489. unsigned long remaining_jiffies;
  490. if (time_after(start_jiffies, timeout_jiffies))
  491. remaining_jiffies = 0;
  492. else
  493. remaining_jiffies = timeout_jiffies - start_jiffies;
  494. ret = wait_event_interruptible_timeout(priv->fence_event,
  495. fence_completed(dev, fence),
  496. remaining_jiffies);
  497. if (ret == 0) {
  498. DBG("timeout waiting for fence: %u (completed: %u)",
  499. fence, priv->completed_fence);
  500. ret = -ETIMEDOUT;
  501. } else if (ret != -ERESTARTSYS) {
  502. ret = 0;
  503. }
  504. }
  505. return ret;
  506. }
  507. int msm_queue_fence_cb(struct drm_device *dev,
  508. struct msm_fence_cb *cb, uint32_t fence)
  509. {
  510. struct msm_drm_private *priv = dev->dev_private;
  511. int ret = 0;
  512. mutex_lock(&dev->struct_mutex);
  513. if (!list_empty(&cb->work.entry)) {
  514. ret = -EINVAL;
  515. } else if (fence > priv->completed_fence) {
  516. cb->fence = fence;
  517. list_add_tail(&cb->work.entry, &priv->fence_cbs);
  518. } else {
  519. queue_work(priv->wq, &cb->work);
  520. }
  521. mutex_unlock(&dev->struct_mutex);
  522. return ret;
  523. }
  524. /* called from workqueue */
  525. void msm_update_fence(struct drm_device *dev, uint32_t fence)
  526. {
  527. struct msm_drm_private *priv = dev->dev_private;
  528. mutex_lock(&dev->struct_mutex);
  529. priv->completed_fence = max(fence, priv->completed_fence);
  530. while (!list_empty(&priv->fence_cbs)) {
  531. struct msm_fence_cb *cb;
  532. cb = list_first_entry(&priv->fence_cbs,
  533. struct msm_fence_cb, work.entry);
  534. if (cb->fence > priv->completed_fence)
  535. break;
  536. list_del_init(&cb->work.entry);
  537. queue_work(priv->wq, &cb->work);
  538. }
  539. mutex_unlock(&dev->struct_mutex);
  540. wake_up_all(&priv->fence_event);
  541. }
  542. void __msm_fence_worker(struct work_struct *work)
  543. {
  544. struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
  545. cb->func(cb);
  546. }
  547. /*
  548. * DRM ioctls:
  549. */
  550. static int msm_ioctl_get_param(struct drm_device *dev, void *data,
  551. struct drm_file *file)
  552. {
  553. struct msm_drm_private *priv = dev->dev_private;
  554. struct drm_msm_param *args = data;
  555. struct msm_gpu *gpu;
  556. /* for now, we just have 3d pipe.. eventually this would need to
  557. * be more clever to dispatch to appropriate gpu module:
  558. */
  559. if (args->pipe != MSM_PIPE_3D0)
  560. return -EINVAL;
  561. gpu = priv->gpu;
  562. if (!gpu)
  563. return -ENXIO;
  564. return gpu->funcs->get_param(gpu, args->param, &args->value);
  565. }
  566. static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
  567. struct drm_file *file)
  568. {
  569. struct drm_msm_gem_new *args = data;
  570. if (args->flags & ~MSM_BO_FLAGS) {
  571. DRM_ERROR("invalid flags: %08x\n", args->flags);
  572. return -EINVAL;
  573. }
  574. return msm_gem_new_handle(dev, file, args->size,
  575. args->flags, &args->handle);
  576. }
  577. #define TS(t) ((struct timespec){ .tv_sec = (t).tv_sec, .tv_nsec = (t).tv_nsec })
  578. static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  579. struct drm_file *file)
  580. {
  581. struct drm_msm_gem_cpu_prep *args = data;
  582. struct drm_gem_object *obj;
  583. int ret;
  584. if (args->op & ~MSM_PREP_FLAGS) {
  585. DRM_ERROR("invalid op: %08x\n", args->op);
  586. return -EINVAL;
  587. }
  588. obj = drm_gem_object_lookup(dev, file, args->handle);
  589. if (!obj)
  590. return -ENOENT;
  591. ret = msm_gem_cpu_prep(obj, args->op, &TS(args->timeout));
  592. drm_gem_object_unreference_unlocked(obj);
  593. return ret;
  594. }
  595. static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  596. struct drm_file *file)
  597. {
  598. struct drm_msm_gem_cpu_fini *args = data;
  599. struct drm_gem_object *obj;
  600. int ret;
  601. obj = drm_gem_object_lookup(dev, file, args->handle);
  602. if (!obj)
  603. return -ENOENT;
  604. ret = msm_gem_cpu_fini(obj);
  605. drm_gem_object_unreference_unlocked(obj);
  606. return ret;
  607. }
  608. static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
  609. struct drm_file *file)
  610. {
  611. struct drm_msm_gem_info *args = data;
  612. struct drm_gem_object *obj;
  613. int ret = 0;
  614. if (args->pad)
  615. return -EINVAL;
  616. obj = drm_gem_object_lookup(dev, file, args->handle);
  617. if (!obj)
  618. return -ENOENT;
  619. args->offset = msm_gem_mmap_offset(obj);
  620. drm_gem_object_unreference_unlocked(obj);
  621. return ret;
  622. }
  623. static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
  624. struct drm_file *file)
  625. {
  626. struct drm_msm_wait_fence *args = data;
  627. if (args->pad) {
  628. DRM_ERROR("invalid pad: %08x\n", args->pad);
  629. return -EINVAL;
  630. }
  631. return msm_wait_fence_interruptable(dev, args->fence,
  632. &TS(args->timeout));
  633. }
  634. static const struct drm_ioctl_desc msm_ioctls[] = {
  635. DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  636. DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  637. DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  638. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  639. DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  640. DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  641. DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
  642. };
  643. static const struct vm_operations_struct vm_ops = {
  644. .fault = msm_gem_fault,
  645. .open = drm_gem_vm_open,
  646. .close = drm_gem_vm_close,
  647. };
  648. static const struct file_operations fops = {
  649. .owner = THIS_MODULE,
  650. .open = drm_open,
  651. .release = drm_release,
  652. .unlocked_ioctl = drm_ioctl,
  653. #ifdef CONFIG_COMPAT
  654. .compat_ioctl = drm_compat_ioctl,
  655. #endif
  656. .poll = drm_poll,
  657. .read = drm_read,
  658. .llseek = no_llseek,
  659. .mmap = msm_gem_mmap,
  660. };
  661. static struct drm_driver msm_driver = {
  662. .driver_features = DRIVER_HAVE_IRQ |
  663. DRIVER_GEM |
  664. DRIVER_PRIME |
  665. DRIVER_RENDER |
  666. DRIVER_MODESET,
  667. .load = msm_load,
  668. .unload = msm_unload,
  669. .open = msm_open,
  670. .preclose = msm_preclose,
  671. .lastclose = msm_lastclose,
  672. .set_busid = drm_platform_set_busid,
  673. .irq_handler = msm_irq,
  674. .irq_preinstall = msm_irq_preinstall,
  675. .irq_postinstall = msm_irq_postinstall,
  676. .irq_uninstall = msm_irq_uninstall,
  677. .get_vblank_counter = drm_vblank_count,
  678. .enable_vblank = msm_enable_vblank,
  679. .disable_vblank = msm_disable_vblank,
  680. .gem_free_object = msm_gem_free_object,
  681. .gem_vm_ops = &vm_ops,
  682. .dumb_create = msm_gem_dumb_create,
  683. .dumb_map_offset = msm_gem_dumb_map_offset,
  684. .dumb_destroy = drm_gem_dumb_destroy,
  685. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  686. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  687. .gem_prime_export = drm_gem_prime_export,
  688. .gem_prime_import = drm_gem_prime_import,
  689. .gem_prime_pin = msm_gem_prime_pin,
  690. .gem_prime_unpin = msm_gem_prime_unpin,
  691. .gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
  692. .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
  693. .gem_prime_vmap = msm_gem_prime_vmap,
  694. .gem_prime_vunmap = msm_gem_prime_vunmap,
  695. .gem_prime_mmap = msm_gem_prime_mmap,
  696. #ifdef CONFIG_DEBUG_FS
  697. .debugfs_init = msm_debugfs_init,
  698. .debugfs_cleanup = msm_debugfs_cleanup,
  699. #endif
  700. .ioctls = msm_ioctls,
  701. .num_ioctls = DRM_MSM_NUM_IOCTLS,
  702. .fops = &fops,
  703. .name = "msm",
  704. .desc = "MSM Snapdragon DRM",
  705. .date = "20130625",
  706. .major = 1,
  707. .minor = 0,
  708. };
  709. #ifdef CONFIG_PM_SLEEP
  710. static int msm_pm_suspend(struct device *dev)
  711. {
  712. struct drm_device *ddev = dev_get_drvdata(dev);
  713. drm_kms_helper_poll_disable(ddev);
  714. return 0;
  715. }
  716. static int msm_pm_resume(struct device *dev)
  717. {
  718. struct drm_device *ddev = dev_get_drvdata(dev);
  719. drm_kms_helper_poll_enable(ddev);
  720. return 0;
  721. }
  722. #endif
  723. static const struct dev_pm_ops msm_pm_ops = {
  724. SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
  725. };
  726. /*
  727. * Componentized driver support:
  728. */
  729. #ifdef CONFIG_OF
  730. /* NOTE: the CONFIG_OF case duplicates the same code as exynos or imx
  731. * (or probably any other).. so probably some room for some helpers
  732. */
  733. static int compare_of(struct device *dev, void *data)
  734. {
  735. return dev->of_node == data;
  736. }
  737. static int add_components(struct device *dev, struct component_match **matchptr,
  738. const char *name)
  739. {
  740. struct device_node *np = dev->of_node;
  741. unsigned i;
  742. for (i = 0; ; i++) {
  743. struct device_node *node;
  744. node = of_parse_phandle(np, name, i);
  745. if (!node)
  746. break;
  747. component_match_add(dev, matchptr, compare_of, node);
  748. }
  749. return 0;
  750. }
  751. #else
  752. static int compare_dev(struct device *dev, void *data)
  753. {
  754. return dev == data;
  755. }
  756. #endif
  757. static int msm_drm_bind(struct device *dev)
  758. {
  759. return drm_platform_init(&msm_driver, to_platform_device(dev));
  760. }
  761. static void msm_drm_unbind(struct device *dev)
  762. {
  763. drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
  764. }
  765. static const struct component_master_ops msm_drm_ops = {
  766. .bind = msm_drm_bind,
  767. .unbind = msm_drm_unbind,
  768. };
  769. /*
  770. * Platform driver:
  771. */
  772. static int msm_pdev_probe(struct platform_device *pdev)
  773. {
  774. struct component_match *match = NULL;
  775. #ifdef CONFIG_OF
  776. add_components(&pdev->dev, &match, "connectors");
  777. add_components(&pdev->dev, &match, "gpus");
  778. #else
  779. /* For non-DT case, it kinda sucks. We don't actually have a way
  780. * to know whether or not we are waiting for certain devices (or if
  781. * they are simply not present). But for non-DT we only need to
  782. * care about apq8064/apq8060/etc (all mdp4/a3xx):
  783. */
  784. static const char *devnames[] = {
  785. "hdmi_msm.0", "kgsl-3d0.0",
  786. };
  787. int i;
  788. DBG("Adding components..");
  789. for (i = 0; i < ARRAY_SIZE(devnames); i++) {
  790. struct device *dev;
  791. dev = bus_find_device_by_name(&platform_bus_type,
  792. NULL, devnames[i]);
  793. if (!dev) {
  794. dev_info(&pdev->dev, "still waiting for %s\n", devnames[i]);
  795. return -EPROBE_DEFER;
  796. }
  797. component_match_add(&pdev->dev, &match, compare_dev, dev);
  798. }
  799. #endif
  800. pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
  801. return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
  802. }
  803. static int msm_pdev_remove(struct platform_device *pdev)
  804. {
  805. component_master_del(&pdev->dev, &msm_drm_ops);
  806. return 0;
  807. }
  808. static const struct platform_device_id msm_id[] = {
  809. { "mdp", 0 },
  810. { }
  811. };
  812. static const struct of_device_id dt_match[] = {
  813. { .compatible = "qcom,mdp" }, /* mdp4 */
  814. { .compatible = "qcom,mdss_mdp" }, /* mdp5 */
  815. {}
  816. };
  817. MODULE_DEVICE_TABLE(of, dt_match);
  818. static struct platform_driver msm_platform_driver = {
  819. .probe = msm_pdev_probe,
  820. .remove = msm_pdev_remove,
  821. .driver = {
  822. .name = "msm",
  823. .of_match_table = dt_match,
  824. .pm = &msm_pm_ops,
  825. },
  826. .id_table = msm_id,
  827. };
  828. static int __init msm_drm_register(void)
  829. {
  830. DBG("init");
  831. hdmi_register();
  832. adreno_register();
  833. return platform_driver_register(&msm_platform_driver);
  834. }
  835. static void __exit msm_drm_unregister(void)
  836. {
  837. DBG("fini");
  838. platform_driver_unregister(&msm_platform_driver);
  839. hdmi_unregister();
  840. adreno_unregister();
  841. }
  842. module_init(msm_drm_register);
  843. module_exit(msm_drm_unregister);
  844. MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
  845. MODULE_DESCRIPTION("MSM DRM Driver");
  846. MODULE_LICENSE("GPL");