mdp4_kms.c 13 KB

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  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of the GNU General Public License version 2 as published by
  7. * the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program. If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #include "msm_drv.h"
  18. #include "msm_mmu.h"
  19. #include "mdp4_kms.h"
  20. static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev);
  21. static int mdp4_hw_init(struct msm_kms *kms)
  22. {
  23. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  24. struct drm_device *dev = mdp4_kms->dev;
  25. uint32_t version, major, minor, dmap_cfg, vg_cfg;
  26. unsigned long clk;
  27. int ret = 0;
  28. pm_runtime_get_sync(dev->dev);
  29. mdp4_enable(mdp4_kms);
  30. version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
  31. mdp4_disable(mdp4_kms);
  32. major = FIELD(version, MDP4_VERSION_MAJOR);
  33. minor = FIELD(version, MDP4_VERSION_MINOR);
  34. DBG("found MDP4 version v%d.%d", major, minor);
  35. if (major != 4) {
  36. dev_err(dev->dev, "unexpected MDP version: v%d.%d\n",
  37. major, minor);
  38. ret = -ENXIO;
  39. goto out;
  40. }
  41. mdp4_kms->rev = minor;
  42. if (mdp4_kms->dsi_pll_vdda) {
  43. if ((mdp4_kms->rev == 2) || (mdp4_kms->rev == 4)) {
  44. ret = regulator_set_voltage(mdp4_kms->dsi_pll_vdda,
  45. 1200000, 1200000);
  46. if (ret) {
  47. dev_err(dev->dev,
  48. "failed to set dsi_pll_vdda voltage: %d\n", ret);
  49. goto out;
  50. }
  51. }
  52. }
  53. if (mdp4_kms->dsi_pll_vddio) {
  54. if (mdp4_kms->rev == 2) {
  55. ret = regulator_set_voltage(mdp4_kms->dsi_pll_vddio,
  56. 1800000, 1800000);
  57. if (ret) {
  58. dev_err(dev->dev,
  59. "failed to set dsi_pll_vddio voltage: %d\n", ret);
  60. goto out;
  61. }
  62. }
  63. }
  64. if (mdp4_kms->rev > 1) {
  65. mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
  66. mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
  67. }
  68. mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
  69. /* max read pending cmd config, 3 pending requests: */
  70. mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
  71. clk = clk_get_rate(mdp4_kms->clk);
  72. if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
  73. dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
  74. vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
  75. } else {
  76. dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
  77. vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
  78. }
  79. DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
  80. mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
  81. mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
  82. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
  83. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
  84. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
  85. mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
  86. if (mdp4_kms->rev >= 2)
  87. mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
  88. mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
  89. /* disable CSC matrix / YUV by default: */
  90. mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
  91. mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
  92. mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
  93. mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
  94. mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
  95. mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
  96. if (mdp4_kms->rev > 1)
  97. mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
  98. out:
  99. pm_runtime_put_sync(dev->dev);
  100. return ret;
  101. }
  102. static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
  103. struct drm_encoder *encoder)
  104. {
  105. /* if we had >1 encoder, we'd need something more clever: */
  106. return mdp4_dtv_round_pixclk(encoder, rate);
  107. }
  108. static void mdp4_preclose(struct msm_kms *kms, struct drm_file *file)
  109. {
  110. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  111. struct msm_drm_private *priv = mdp4_kms->dev->dev_private;
  112. unsigned i;
  113. for (i = 0; i < priv->num_crtcs; i++)
  114. mdp4_crtc_cancel_pending_flip(priv->crtcs[i], file);
  115. }
  116. static void mdp4_destroy(struct msm_kms *kms)
  117. {
  118. struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
  119. if (mdp4_kms->blank_cursor_iova)
  120. msm_gem_put_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id);
  121. if (mdp4_kms->blank_cursor_bo)
  122. drm_gem_object_unreference_unlocked(mdp4_kms->blank_cursor_bo);
  123. kfree(mdp4_kms);
  124. }
  125. static const struct mdp_kms_funcs kms_funcs = {
  126. .base = {
  127. .hw_init = mdp4_hw_init,
  128. .irq_preinstall = mdp4_irq_preinstall,
  129. .irq_postinstall = mdp4_irq_postinstall,
  130. .irq_uninstall = mdp4_irq_uninstall,
  131. .irq = mdp4_irq,
  132. .enable_vblank = mdp4_enable_vblank,
  133. .disable_vblank = mdp4_disable_vblank,
  134. .get_format = mdp_get_format,
  135. .round_pixclk = mdp4_round_pixclk,
  136. .preclose = mdp4_preclose,
  137. .destroy = mdp4_destroy,
  138. },
  139. .set_irqmask = mdp4_set_irqmask,
  140. };
  141. int mdp4_disable(struct mdp4_kms *mdp4_kms)
  142. {
  143. DBG("");
  144. clk_disable_unprepare(mdp4_kms->clk);
  145. if (mdp4_kms->pclk)
  146. clk_disable_unprepare(mdp4_kms->pclk);
  147. clk_disable_unprepare(mdp4_kms->lut_clk);
  148. if (mdp4_kms->axi_clk)
  149. clk_disable_unprepare(mdp4_kms->axi_clk);
  150. return 0;
  151. }
  152. int mdp4_enable(struct mdp4_kms *mdp4_kms)
  153. {
  154. DBG("");
  155. clk_prepare_enable(mdp4_kms->clk);
  156. if (mdp4_kms->pclk)
  157. clk_prepare_enable(mdp4_kms->pclk);
  158. clk_prepare_enable(mdp4_kms->lut_clk);
  159. if (mdp4_kms->axi_clk)
  160. clk_prepare_enable(mdp4_kms->axi_clk);
  161. return 0;
  162. }
  163. #ifdef CONFIG_OF
  164. static struct drm_panel *detect_panel(struct drm_device *dev, const char *name)
  165. {
  166. struct device_node *n;
  167. struct drm_panel *panel = NULL;
  168. n = of_parse_phandle(dev->dev->of_node, name, 0);
  169. if (n) {
  170. panel = of_drm_find_panel(n);
  171. if (!panel)
  172. panel = ERR_PTR(-EPROBE_DEFER);
  173. }
  174. return panel;
  175. }
  176. #else
  177. static struct drm_panel *detect_panel(struct drm_device *dev, const char *name)
  178. {
  179. // ??? maybe use a module param to specify which panel is attached?
  180. }
  181. #endif
  182. static int modeset_init(struct mdp4_kms *mdp4_kms)
  183. {
  184. struct drm_device *dev = mdp4_kms->dev;
  185. struct msm_drm_private *priv = dev->dev_private;
  186. struct drm_plane *plane;
  187. struct drm_crtc *crtc;
  188. struct drm_encoder *encoder;
  189. struct drm_connector *connector;
  190. struct drm_panel *panel;
  191. int ret;
  192. /* construct non-private planes: */
  193. plane = mdp4_plane_init(dev, VG1, false);
  194. if (IS_ERR(plane)) {
  195. dev_err(dev->dev, "failed to construct plane for VG1\n");
  196. ret = PTR_ERR(plane);
  197. goto fail;
  198. }
  199. priv->planes[priv->num_planes++] = plane;
  200. plane = mdp4_plane_init(dev, VG2, false);
  201. if (IS_ERR(plane)) {
  202. dev_err(dev->dev, "failed to construct plane for VG2\n");
  203. ret = PTR_ERR(plane);
  204. goto fail;
  205. }
  206. priv->planes[priv->num_planes++] = plane;
  207. /*
  208. * Setup the LCDC/LVDS path: RGB2 -> DMA_P -> LCDC -> LVDS:
  209. */
  210. panel = detect_panel(dev, "qcom,lvds-panel");
  211. if (IS_ERR(panel)) {
  212. ret = PTR_ERR(panel);
  213. dev_err(dev->dev, "failed to detect LVDS panel: %d\n", ret);
  214. goto fail;
  215. }
  216. plane = mdp4_plane_init(dev, RGB2, true);
  217. if (IS_ERR(plane)) {
  218. dev_err(dev->dev, "failed to construct plane for RGB2\n");
  219. ret = PTR_ERR(plane);
  220. goto fail;
  221. }
  222. crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, 0, DMA_P);
  223. if (IS_ERR(crtc)) {
  224. dev_err(dev->dev, "failed to construct crtc for DMA_P\n");
  225. ret = PTR_ERR(crtc);
  226. goto fail;
  227. }
  228. encoder = mdp4_lcdc_encoder_init(dev, panel);
  229. if (IS_ERR(encoder)) {
  230. dev_err(dev->dev, "failed to construct LCDC encoder\n");
  231. ret = PTR_ERR(encoder);
  232. goto fail;
  233. }
  234. /* LCDC can be hooked to DMA_P: */
  235. encoder->possible_crtcs = 1 << priv->num_crtcs;
  236. priv->crtcs[priv->num_crtcs++] = crtc;
  237. priv->encoders[priv->num_encoders++] = encoder;
  238. connector = mdp4_lvds_connector_init(dev, panel, encoder);
  239. if (IS_ERR(connector)) {
  240. ret = PTR_ERR(connector);
  241. dev_err(dev->dev, "failed to initialize LVDS connector: %d\n", ret);
  242. goto fail;
  243. }
  244. priv->connectors[priv->num_connectors++] = connector;
  245. /*
  246. * Setup DTV/HDMI path: RGB1 -> DMA_E -> DTV -> HDMI:
  247. */
  248. plane = mdp4_plane_init(dev, RGB1, true);
  249. if (IS_ERR(plane)) {
  250. dev_err(dev->dev, "failed to construct plane for RGB1\n");
  251. ret = PTR_ERR(plane);
  252. goto fail;
  253. }
  254. crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, 1, DMA_E);
  255. if (IS_ERR(crtc)) {
  256. dev_err(dev->dev, "failed to construct crtc for DMA_E\n");
  257. ret = PTR_ERR(crtc);
  258. goto fail;
  259. }
  260. encoder = mdp4_dtv_encoder_init(dev);
  261. if (IS_ERR(encoder)) {
  262. dev_err(dev->dev, "failed to construct DTV encoder\n");
  263. ret = PTR_ERR(encoder);
  264. goto fail;
  265. }
  266. /* DTV can be hooked to DMA_E: */
  267. encoder->possible_crtcs = 1 << priv->num_crtcs;
  268. priv->crtcs[priv->num_crtcs++] = crtc;
  269. priv->encoders[priv->num_encoders++] = encoder;
  270. if (priv->hdmi) {
  271. /* Construct bridge/connector for HDMI: */
  272. ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
  273. if (ret) {
  274. dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
  275. goto fail;
  276. }
  277. }
  278. return 0;
  279. fail:
  280. return ret;
  281. }
  282. static const char *iommu_ports[] = {
  283. "mdp_port0_cb0", "mdp_port1_cb0",
  284. };
  285. struct msm_kms *mdp4_kms_init(struct drm_device *dev)
  286. {
  287. struct platform_device *pdev = dev->platformdev;
  288. struct mdp4_platform_config *config = mdp4_get_config(pdev);
  289. struct mdp4_kms *mdp4_kms;
  290. struct msm_kms *kms = NULL;
  291. struct msm_mmu *mmu;
  292. int ret;
  293. mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL);
  294. if (!mdp4_kms) {
  295. dev_err(dev->dev, "failed to allocate kms\n");
  296. ret = -ENOMEM;
  297. goto fail;
  298. }
  299. mdp_kms_init(&mdp4_kms->base, &kms_funcs);
  300. kms = &mdp4_kms->base.base;
  301. mdp4_kms->dev = dev;
  302. mdp4_kms->mmio = msm_ioremap(pdev, NULL, "MDP4");
  303. if (IS_ERR(mdp4_kms->mmio)) {
  304. ret = PTR_ERR(mdp4_kms->mmio);
  305. goto fail;
  306. }
  307. mdp4_kms->dsi_pll_vdda =
  308. devm_regulator_get_optional(&pdev->dev, "dsi_pll_vdda");
  309. if (IS_ERR(mdp4_kms->dsi_pll_vdda))
  310. mdp4_kms->dsi_pll_vdda = NULL;
  311. mdp4_kms->dsi_pll_vddio =
  312. devm_regulator_get_optional(&pdev->dev, "dsi_pll_vddio");
  313. if (IS_ERR(mdp4_kms->dsi_pll_vddio))
  314. mdp4_kms->dsi_pll_vddio = NULL;
  315. /* NOTE: driver for this regulator still missing upstream.. use
  316. * _get_exclusive() and ignore the error if it does not exist
  317. * (and hope that the bootloader left it on for us)
  318. */
  319. mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
  320. if (IS_ERR(mdp4_kms->vdd))
  321. mdp4_kms->vdd = NULL;
  322. if (mdp4_kms->vdd) {
  323. ret = regulator_enable(mdp4_kms->vdd);
  324. if (ret) {
  325. dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
  326. goto fail;
  327. }
  328. }
  329. mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
  330. if (IS_ERR(mdp4_kms->clk)) {
  331. dev_err(dev->dev, "failed to get core_clk\n");
  332. ret = PTR_ERR(mdp4_kms->clk);
  333. goto fail;
  334. }
  335. mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
  336. if (IS_ERR(mdp4_kms->pclk))
  337. mdp4_kms->pclk = NULL;
  338. // XXX if (rev >= MDP_REV_42) { ???
  339. mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk");
  340. if (IS_ERR(mdp4_kms->lut_clk)) {
  341. dev_err(dev->dev, "failed to get lut_clk\n");
  342. ret = PTR_ERR(mdp4_kms->lut_clk);
  343. goto fail;
  344. }
  345. mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "mdp_axi_clk");
  346. if (IS_ERR(mdp4_kms->axi_clk)) {
  347. dev_err(dev->dev, "failed to get axi_clk\n");
  348. ret = PTR_ERR(mdp4_kms->axi_clk);
  349. goto fail;
  350. }
  351. clk_set_rate(mdp4_kms->clk, config->max_clk);
  352. clk_set_rate(mdp4_kms->lut_clk, config->max_clk);
  353. /* make sure things are off before attaching iommu (bootloader could
  354. * have left things on, in which case we'll start getting faults if
  355. * we don't disable):
  356. */
  357. mdp4_enable(mdp4_kms);
  358. mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
  359. mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
  360. mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
  361. mdp4_disable(mdp4_kms);
  362. mdelay(16);
  363. if (config->iommu) {
  364. mmu = msm_iommu_new(&pdev->dev, config->iommu);
  365. if (IS_ERR(mmu)) {
  366. ret = PTR_ERR(mmu);
  367. goto fail;
  368. }
  369. ret = mmu->funcs->attach(mmu, iommu_ports,
  370. ARRAY_SIZE(iommu_ports));
  371. if (ret)
  372. goto fail;
  373. } else {
  374. dev_info(dev->dev, "no iommu, fallback to phys "
  375. "contig buffers for scanout\n");
  376. mmu = NULL;
  377. }
  378. mdp4_kms->id = msm_register_mmu(dev, mmu);
  379. if (mdp4_kms->id < 0) {
  380. ret = mdp4_kms->id;
  381. dev_err(dev->dev, "failed to register mdp4 iommu: %d\n", ret);
  382. goto fail;
  383. }
  384. ret = modeset_init(mdp4_kms);
  385. if (ret) {
  386. dev_err(dev->dev, "modeset_init failed: %d\n", ret);
  387. goto fail;
  388. }
  389. mutex_lock(&dev->struct_mutex);
  390. mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC);
  391. mutex_unlock(&dev->struct_mutex);
  392. if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
  393. ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
  394. dev_err(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
  395. mdp4_kms->blank_cursor_bo = NULL;
  396. goto fail;
  397. }
  398. ret = msm_gem_get_iova(mdp4_kms->blank_cursor_bo, mdp4_kms->id,
  399. &mdp4_kms->blank_cursor_iova);
  400. if (ret) {
  401. dev_err(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
  402. goto fail;
  403. }
  404. return kms;
  405. fail:
  406. if (kms)
  407. mdp4_destroy(kms);
  408. return ERR_PTR(ret);
  409. }
  410. static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev)
  411. {
  412. static struct mdp4_platform_config config = {};
  413. #ifdef CONFIG_OF
  414. /* TODO */
  415. config.max_clk = 266667000;
  416. config.iommu = iommu_domain_alloc(&platform_bus_type);
  417. #else
  418. if (cpu_is_apq8064())
  419. config.max_clk = 266667000;
  420. else
  421. config.max_clk = 200000000;
  422. config.iommu = msm_get_iommu_domain(DISPLAY_READ_DOMAIN);
  423. #endif
  424. return &config;
  425. }