gpio-sch.c 6.1 KB

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  1. /*
  2. * GPIO interface for Intel Poulsbo SCH
  3. *
  4. * Copyright (c) 2010 CompuLab Ltd
  5. * Author: Denis Turischev <denis@compulab.co.il>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License 2 as published
  9. * by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; see the file COPYING. If not, write to
  18. * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/init.h>
  21. #include <linux/kernel.h>
  22. #include <linux/module.h>
  23. #include <linux/io.h>
  24. #include <linux/errno.h>
  25. #include <linux/acpi.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/pci_ids.h>
  28. #include <linux/gpio.h>
  29. #define GEN 0x00
  30. #define GIO 0x04
  31. #define GLV 0x08
  32. struct sch_gpio {
  33. struct gpio_chip chip;
  34. spinlock_t lock;
  35. unsigned short iobase;
  36. unsigned short core_base;
  37. unsigned short resume_base;
  38. };
  39. #define to_sch_gpio(c) container_of(c, struct sch_gpio, chip)
  40. static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
  41. unsigned reg)
  42. {
  43. unsigned base = 0;
  44. if (gpio >= sch->resume_base) {
  45. gpio -= sch->resume_base;
  46. base += 0x20;
  47. }
  48. return base + reg + gpio / 8;
  49. }
  50. static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
  51. {
  52. if (gpio >= sch->resume_base)
  53. gpio -= sch->resume_base;
  54. return gpio % 8;
  55. }
  56. static void sch_gpio_enable(struct sch_gpio *sch, unsigned gpio)
  57. {
  58. unsigned short offset, bit;
  59. u8 enable;
  60. spin_lock(&sch->lock);
  61. offset = sch_gpio_offset(sch, gpio, GEN);
  62. bit = sch_gpio_bit(sch, gpio);
  63. enable = inb(sch->iobase + offset);
  64. if (!(enable & (1 << bit)))
  65. outb(enable | (1 << bit), sch->iobase + offset);
  66. spin_unlock(&sch->lock);
  67. }
  68. static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
  69. {
  70. struct sch_gpio *sch = to_sch_gpio(gc);
  71. u8 curr_dirs;
  72. unsigned short offset, bit;
  73. spin_lock(&sch->lock);
  74. offset = sch_gpio_offset(sch, gpio_num, GIO);
  75. bit = sch_gpio_bit(sch, gpio_num);
  76. curr_dirs = inb(sch->iobase + offset);
  77. if (!(curr_dirs & (1 << bit)))
  78. outb(curr_dirs | (1 << bit), sch->iobase + offset);
  79. spin_unlock(&sch->lock);
  80. return 0;
  81. }
  82. static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
  83. {
  84. struct sch_gpio *sch = to_sch_gpio(gc);
  85. int res;
  86. unsigned short offset, bit;
  87. offset = sch_gpio_offset(sch, gpio_num, GLV);
  88. bit = sch_gpio_bit(sch, gpio_num);
  89. res = !!(inb(sch->iobase + offset) & (1 << bit));
  90. return res;
  91. }
  92. static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
  93. {
  94. struct sch_gpio *sch = to_sch_gpio(gc);
  95. u8 curr_vals;
  96. unsigned short offset, bit;
  97. spin_lock(&sch->lock);
  98. offset = sch_gpio_offset(sch, gpio_num, GLV);
  99. bit = sch_gpio_bit(sch, gpio_num);
  100. curr_vals = inb(sch->iobase + offset);
  101. if (val)
  102. outb(curr_vals | (1 << bit), sch->iobase + offset);
  103. else
  104. outb((curr_vals & ~(1 << bit)), sch->iobase + offset);
  105. spin_unlock(&sch->lock);
  106. }
  107. static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
  108. int val)
  109. {
  110. struct sch_gpio *sch = to_sch_gpio(gc);
  111. u8 curr_dirs;
  112. unsigned short offset, bit;
  113. spin_lock(&sch->lock);
  114. offset = sch_gpio_offset(sch, gpio_num, GIO);
  115. bit = sch_gpio_bit(sch, gpio_num);
  116. curr_dirs = inb(sch->iobase + offset);
  117. if (curr_dirs & (1 << bit))
  118. outb(curr_dirs & ~(1 << bit), sch->iobase + offset);
  119. spin_unlock(&sch->lock);
  120. /*
  121. * according to the datasheet, writing to the level register has no
  122. * effect when GPIO is programmed as input.
  123. * Actually the the level register is read-only when configured as input.
  124. * Thus presetting the output level before switching to output is _NOT_ possible.
  125. * Hence we set the level after configuring the GPIO as output.
  126. * But we cannot prevent a short low pulse if direction is set to high
  127. * and an external pull-up is connected.
  128. */
  129. sch_gpio_set(gc, gpio_num, val);
  130. return 0;
  131. }
  132. static struct gpio_chip sch_gpio_chip = {
  133. .label = "sch_gpio",
  134. .owner = THIS_MODULE,
  135. .direction_input = sch_gpio_direction_in,
  136. .get = sch_gpio_get,
  137. .direction_output = sch_gpio_direction_out,
  138. .set = sch_gpio_set,
  139. };
  140. static int sch_gpio_probe(struct platform_device *pdev)
  141. {
  142. struct sch_gpio *sch;
  143. struct resource *res;
  144. sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
  145. if (!sch)
  146. return -ENOMEM;
  147. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  148. if (!res)
  149. return -EBUSY;
  150. if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
  151. pdev->name))
  152. return -EBUSY;
  153. spin_lock_init(&sch->lock);
  154. sch->iobase = res->start;
  155. sch->chip = sch_gpio_chip;
  156. sch->chip.label = dev_name(&pdev->dev);
  157. sch->chip.dev = &pdev->dev;
  158. switch (pdev->id) {
  159. case PCI_DEVICE_ID_INTEL_SCH_LPC:
  160. sch->core_base = 0;
  161. sch->resume_base = 10;
  162. sch->chip.ngpio = 14;
  163. /*
  164. * GPIO[6:0] enabled by default
  165. * GPIO7 is configured by the CMC as SLPIOVR
  166. * Enable GPIO[9:8] core powered gpios explicitly
  167. */
  168. sch_gpio_enable(sch, 8);
  169. sch_gpio_enable(sch, 9);
  170. /*
  171. * SUS_GPIO[2:0] enabled by default
  172. * Enable SUS_GPIO3 resume powered gpio explicitly
  173. */
  174. sch_gpio_enable(sch, 13);
  175. break;
  176. case PCI_DEVICE_ID_INTEL_ITC_LPC:
  177. sch->core_base = 0;
  178. sch->resume_base = 5;
  179. sch->chip.ngpio = 14;
  180. break;
  181. case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
  182. sch->core_base = 0;
  183. sch->resume_base = 21;
  184. sch->chip.ngpio = 30;
  185. break;
  186. default:
  187. return -ENODEV;
  188. }
  189. platform_set_drvdata(pdev, sch);
  190. return gpiochip_add(&sch->chip);
  191. }
  192. static int sch_gpio_remove(struct platform_device *pdev)
  193. {
  194. struct sch_gpio *sch = platform_get_drvdata(pdev);
  195. gpiochip_remove(&sch->chip);
  196. return 0;
  197. }
  198. static struct platform_driver sch_gpio_driver = {
  199. .driver = {
  200. .name = "sch_gpio",
  201. },
  202. .probe = sch_gpio_probe,
  203. .remove = sch_gpio_remove,
  204. };
  205. module_platform_driver(sch_gpio_driver);
  206. MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
  207. MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
  208. MODULE_LICENSE("GPL");
  209. MODULE_ALIAS("platform:sch_gpio");