edac_mc_sysfs.c 29 KB

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  1. /*
  2. * edac_mc kernel module
  3. * (C) 2005-2007 Linux Networx (http://lnxi.com)
  4. *
  5. * This file may be distributed under the terms of the
  6. * GNU General Public License.
  7. *
  8. * Written Doug Thompson <norsk5@xmission.com> www.softwarebitmaker.com
  9. *
  10. * (c) 2012-2013 - Mauro Carvalho Chehab
  11. * The entire API were re-written, and ported to use struct device
  12. *
  13. */
  14. #include <linux/ctype.h>
  15. #include <linux/slab.h>
  16. #include <linux/edac.h>
  17. #include <linux/bug.h>
  18. #include <linux/pm_runtime.h>
  19. #include <linux/uaccess.h>
  20. #include "edac_core.h"
  21. #include "edac_module.h"
  22. /* MC EDAC Controls, setable by module parameter, and sysfs */
  23. static int edac_mc_log_ue = 1;
  24. static int edac_mc_log_ce = 1;
  25. static int edac_mc_panic_on_ue;
  26. static int edac_mc_poll_msec = 1000;
  27. /* Getter functions for above */
  28. int edac_mc_get_log_ue(void)
  29. {
  30. return edac_mc_log_ue;
  31. }
  32. int edac_mc_get_log_ce(void)
  33. {
  34. return edac_mc_log_ce;
  35. }
  36. int edac_mc_get_panic_on_ue(void)
  37. {
  38. return edac_mc_panic_on_ue;
  39. }
  40. /* this is temporary */
  41. int edac_mc_get_poll_msec(void)
  42. {
  43. return edac_mc_poll_msec;
  44. }
  45. static int edac_set_poll_msec(const char *val, struct kernel_param *kp)
  46. {
  47. unsigned long l;
  48. int ret;
  49. if (!val)
  50. return -EINVAL;
  51. ret = kstrtoul(val, 0, &l);
  52. if (ret)
  53. return ret;
  54. if (l < 1000)
  55. return -EINVAL;
  56. *((unsigned long *)kp->arg) = l;
  57. /* notify edac_mc engine to reset the poll period */
  58. edac_mc_reset_delay_period(l);
  59. return 0;
  60. }
  61. /* Parameter declarations for above */
  62. module_param(edac_mc_panic_on_ue, int, 0644);
  63. MODULE_PARM_DESC(edac_mc_panic_on_ue, "Panic on uncorrected error: 0=off 1=on");
  64. module_param(edac_mc_log_ue, int, 0644);
  65. MODULE_PARM_DESC(edac_mc_log_ue,
  66. "Log uncorrectable error to console: 0=off 1=on");
  67. module_param(edac_mc_log_ce, int, 0644);
  68. MODULE_PARM_DESC(edac_mc_log_ce,
  69. "Log correctable error to console: 0=off 1=on");
  70. module_param_call(edac_mc_poll_msec, edac_set_poll_msec, param_get_int,
  71. &edac_mc_poll_msec, 0644);
  72. MODULE_PARM_DESC(edac_mc_poll_msec, "Polling period in milliseconds");
  73. static struct device *mci_pdev;
  74. /*
  75. * various constants for Memory Controllers
  76. */
  77. static const char * const mem_types[] = {
  78. [MEM_EMPTY] = "Empty",
  79. [MEM_RESERVED] = "Reserved",
  80. [MEM_UNKNOWN] = "Unknown",
  81. [MEM_FPM] = "FPM",
  82. [MEM_EDO] = "EDO",
  83. [MEM_BEDO] = "BEDO",
  84. [MEM_SDR] = "Unbuffered-SDR",
  85. [MEM_RDR] = "Registered-SDR",
  86. [MEM_DDR] = "Unbuffered-DDR",
  87. [MEM_RDDR] = "Registered-DDR",
  88. [MEM_RMBS] = "RMBS",
  89. [MEM_DDR2] = "Unbuffered-DDR2",
  90. [MEM_FB_DDR2] = "FullyBuffered-DDR2",
  91. [MEM_RDDR2] = "Registered-DDR2",
  92. [MEM_XDR] = "XDR",
  93. [MEM_DDR3] = "Unbuffered-DDR3",
  94. [MEM_RDDR3] = "Registered-DDR3",
  95. [MEM_DDR4] = "Unbuffered-DDR4",
  96. [MEM_RDDR4] = "Registered-DDR4"
  97. };
  98. static const char * const dev_types[] = {
  99. [DEV_UNKNOWN] = "Unknown",
  100. [DEV_X1] = "x1",
  101. [DEV_X2] = "x2",
  102. [DEV_X4] = "x4",
  103. [DEV_X8] = "x8",
  104. [DEV_X16] = "x16",
  105. [DEV_X32] = "x32",
  106. [DEV_X64] = "x64"
  107. };
  108. static const char * const edac_caps[] = {
  109. [EDAC_UNKNOWN] = "Unknown",
  110. [EDAC_NONE] = "None",
  111. [EDAC_RESERVED] = "Reserved",
  112. [EDAC_PARITY] = "PARITY",
  113. [EDAC_EC] = "EC",
  114. [EDAC_SECDED] = "SECDED",
  115. [EDAC_S2ECD2ED] = "S2ECD2ED",
  116. [EDAC_S4ECD4ED] = "S4ECD4ED",
  117. [EDAC_S8ECD8ED] = "S8ECD8ED",
  118. [EDAC_S16ECD16ED] = "S16ECD16ED"
  119. };
  120. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  121. /*
  122. * EDAC sysfs CSROW data structures and methods
  123. */
  124. #define to_csrow(k) container_of(k, struct csrow_info, dev)
  125. /*
  126. * We need it to avoid namespace conflicts between the legacy API
  127. * and the per-dimm/per-rank one
  128. */
  129. #define DEVICE_ATTR_LEGACY(_name, _mode, _show, _store) \
  130. static struct device_attribute dev_attr_legacy_##_name = __ATTR(_name, _mode, _show, _store)
  131. struct dev_ch_attribute {
  132. struct device_attribute attr;
  133. int channel;
  134. };
  135. #define DEVICE_CHANNEL(_name, _mode, _show, _store, _var) \
  136. struct dev_ch_attribute dev_attr_legacy_##_name = \
  137. { __ATTR(_name, _mode, _show, _store), (_var) }
  138. #define to_channel(k) (container_of(k, struct dev_ch_attribute, attr)->channel)
  139. /* Set of more default csrow<id> attribute show/store functions */
  140. static ssize_t csrow_ue_count_show(struct device *dev,
  141. struct device_attribute *mattr, char *data)
  142. {
  143. struct csrow_info *csrow = to_csrow(dev);
  144. return sprintf(data, "%u\n", csrow->ue_count);
  145. }
  146. static ssize_t csrow_ce_count_show(struct device *dev,
  147. struct device_attribute *mattr, char *data)
  148. {
  149. struct csrow_info *csrow = to_csrow(dev);
  150. return sprintf(data, "%u\n", csrow->ce_count);
  151. }
  152. static ssize_t csrow_size_show(struct device *dev,
  153. struct device_attribute *mattr, char *data)
  154. {
  155. struct csrow_info *csrow = to_csrow(dev);
  156. int i;
  157. u32 nr_pages = 0;
  158. for (i = 0; i < csrow->nr_channels; i++)
  159. nr_pages += csrow->channels[i]->dimm->nr_pages;
  160. return sprintf(data, "%u\n", PAGES_TO_MiB(nr_pages));
  161. }
  162. static ssize_t csrow_mem_type_show(struct device *dev,
  163. struct device_attribute *mattr, char *data)
  164. {
  165. struct csrow_info *csrow = to_csrow(dev);
  166. return sprintf(data, "%s\n", mem_types[csrow->channels[0]->dimm->mtype]);
  167. }
  168. static ssize_t csrow_dev_type_show(struct device *dev,
  169. struct device_attribute *mattr, char *data)
  170. {
  171. struct csrow_info *csrow = to_csrow(dev);
  172. return sprintf(data, "%s\n", dev_types[csrow->channels[0]->dimm->dtype]);
  173. }
  174. static ssize_t csrow_edac_mode_show(struct device *dev,
  175. struct device_attribute *mattr,
  176. char *data)
  177. {
  178. struct csrow_info *csrow = to_csrow(dev);
  179. return sprintf(data, "%s\n", edac_caps[csrow->channels[0]->dimm->edac_mode]);
  180. }
  181. /* show/store functions for DIMM Label attributes */
  182. static ssize_t channel_dimm_label_show(struct device *dev,
  183. struct device_attribute *mattr,
  184. char *data)
  185. {
  186. struct csrow_info *csrow = to_csrow(dev);
  187. unsigned chan = to_channel(mattr);
  188. struct rank_info *rank = csrow->channels[chan];
  189. /* if field has not been initialized, there is nothing to send */
  190. if (!rank->dimm->label[0])
  191. return 0;
  192. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n",
  193. rank->dimm->label);
  194. }
  195. static ssize_t channel_dimm_label_store(struct device *dev,
  196. struct device_attribute *mattr,
  197. const char *data, size_t count)
  198. {
  199. struct csrow_info *csrow = to_csrow(dev);
  200. unsigned chan = to_channel(mattr);
  201. struct rank_info *rank = csrow->channels[chan];
  202. ssize_t max_size = 0;
  203. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  204. strncpy(rank->dimm->label, data, max_size);
  205. rank->dimm->label[max_size] = '\0';
  206. return max_size;
  207. }
  208. /* show function for dynamic chX_ce_count attribute */
  209. static ssize_t channel_ce_count_show(struct device *dev,
  210. struct device_attribute *mattr, char *data)
  211. {
  212. struct csrow_info *csrow = to_csrow(dev);
  213. unsigned chan = to_channel(mattr);
  214. struct rank_info *rank = csrow->channels[chan];
  215. return sprintf(data, "%u\n", rank->ce_count);
  216. }
  217. /* cwrow<id>/attribute files */
  218. DEVICE_ATTR_LEGACY(size_mb, S_IRUGO, csrow_size_show, NULL);
  219. DEVICE_ATTR_LEGACY(dev_type, S_IRUGO, csrow_dev_type_show, NULL);
  220. DEVICE_ATTR_LEGACY(mem_type, S_IRUGO, csrow_mem_type_show, NULL);
  221. DEVICE_ATTR_LEGACY(edac_mode, S_IRUGO, csrow_edac_mode_show, NULL);
  222. DEVICE_ATTR_LEGACY(ue_count, S_IRUGO, csrow_ue_count_show, NULL);
  223. DEVICE_ATTR_LEGACY(ce_count, S_IRUGO, csrow_ce_count_show, NULL);
  224. /* default attributes of the CSROW<id> object */
  225. static struct attribute *csrow_attrs[] = {
  226. &dev_attr_legacy_dev_type.attr,
  227. &dev_attr_legacy_mem_type.attr,
  228. &dev_attr_legacy_edac_mode.attr,
  229. &dev_attr_legacy_size_mb.attr,
  230. &dev_attr_legacy_ue_count.attr,
  231. &dev_attr_legacy_ce_count.attr,
  232. NULL,
  233. };
  234. static struct attribute_group csrow_attr_grp = {
  235. .attrs = csrow_attrs,
  236. };
  237. static const struct attribute_group *csrow_attr_groups[] = {
  238. &csrow_attr_grp,
  239. NULL
  240. };
  241. static void csrow_attr_release(struct device *dev)
  242. {
  243. struct csrow_info *csrow = container_of(dev, struct csrow_info, dev);
  244. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  245. kfree(csrow);
  246. }
  247. static struct device_type csrow_attr_type = {
  248. .groups = csrow_attr_groups,
  249. .release = csrow_attr_release,
  250. };
  251. /*
  252. * possible dynamic channel DIMM Label attribute files
  253. *
  254. */
  255. #define EDAC_NR_CHANNELS 6
  256. DEVICE_CHANNEL(ch0_dimm_label, S_IRUGO | S_IWUSR,
  257. channel_dimm_label_show, channel_dimm_label_store, 0);
  258. DEVICE_CHANNEL(ch1_dimm_label, S_IRUGO | S_IWUSR,
  259. channel_dimm_label_show, channel_dimm_label_store, 1);
  260. DEVICE_CHANNEL(ch2_dimm_label, S_IRUGO | S_IWUSR,
  261. channel_dimm_label_show, channel_dimm_label_store, 2);
  262. DEVICE_CHANNEL(ch3_dimm_label, S_IRUGO | S_IWUSR,
  263. channel_dimm_label_show, channel_dimm_label_store, 3);
  264. DEVICE_CHANNEL(ch4_dimm_label, S_IRUGO | S_IWUSR,
  265. channel_dimm_label_show, channel_dimm_label_store, 4);
  266. DEVICE_CHANNEL(ch5_dimm_label, S_IRUGO | S_IWUSR,
  267. channel_dimm_label_show, channel_dimm_label_store, 5);
  268. /* Total possible dynamic DIMM Label attribute file table */
  269. static struct device_attribute *dynamic_csrow_dimm_attr[] = {
  270. &dev_attr_legacy_ch0_dimm_label.attr,
  271. &dev_attr_legacy_ch1_dimm_label.attr,
  272. &dev_attr_legacy_ch2_dimm_label.attr,
  273. &dev_attr_legacy_ch3_dimm_label.attr,
  274. &dev_attr_legacy_ch4_dimm_label.attr,
  275. &dev_attr_legacy_ch5_dimm_label.attr
  276. };
  277. /* possible dynamic channel ce_count attribute files */
  278. DEVICE_CHANNEL(ch0_ce_count, S_IRUGO,
  279. channel_ce_count_show, NULL, 0);
  280. DEVICE_CHANNEL(ch1_ce_count, S_IRUGO,
  281. channel_ce_count_show, NULL, 1);
  282. DEVICE_CHANNEL(ch2_ce_count, S_IRUGO,
  283. channel_ce_count_show, NULL, 2);
  284. DEVICE_CHANNEL(ch3_ce_count, S_IRUGO,
  285. channel_ce_count_show, NULL, 3);
  286. DEVICE_CHANNEL(ch4_ce_count, S_IRUGO,
  287. channel_ce_count_show, NULL, 4);
  288. DEVICE_CHANNEL(ch5_ce_count, S_IRUGO,
  289. channel_ce_count_show, NULL, 5);
  290. /* Total possible dynamic ce_count attribute file table */
  291. static struct device_attribute *dynamic_csrow_ce_count_attr[] = {
  292. &dev_attr_legacy_ch0_ce_count.attr,
  293. &dev_attr_legacy_ch1_ce_count.attr,
  294. &dev_attr_legacy_ch2_ce_count.attr,
  295. &dev_attr_legacy_ch3_ce_count.attr,
  296. &dev_attr_legacy_ch4_ce_count.attr,
  297. &dev_attr_legacy_ch5_ce_count.attr
  298. };
  299. static inline int nr_pages_per_csrow(struct csrow_info *csrow)
  300. {
  301. int chan, nr_pages = 0;
  302. for (chan = 0; chan < csrow->nr_channels; chan++)
  303. nr_pages += csrow->channels[chan]->dimm->nr_pages;
  304. return nr_pages;
  305. }
  306. /* Create a CSROW object under specifed edac_mc_device */
  307. static int edac_create_csrow_object(struct mem_ctl_info *mci,
  308. struct csrow_info *csrow, int index)
  309. {
  310. int err, chan;
  311. if (csrow->nr_channels > EDAC_NR_CHANNELS)
  312. return -ENODEV;
  313. csrow->dev.type = &csrow_attr_type;
  314. csrow->dev.bus = mci->bus;
  315. device_initialize(&csrow->dev);
  316. csrow->dev.parent = &mci->dev;
  317. csrow->mci = mci;
  318. dev_set_name(&csrow->dev, "csrow%d", index);
  319. dev_set_drvdata(&csrow->dev, csrow);
  320. edac_dbg(0, "creating (virtual) csrow node %s\n",
  321. dev_name(&csrow->dev));
  322. err = device_add(&csrow->dev);
  323. if (err < 0)
  324. return err;
  325. for (chan = 0; chan < csrow->nr_channels; chan++) {
  326. /* Only expose populated DIMMs */
  327. if (!csrow->channels[chan]->dimm->nr_pages)
  328. continue;
  329. err = device_create_file(&csrow->dev,
  330. dynamic_csrow_dimm_attr[chan]);
  331. if (err < 0)
  332. goto error;
  333. err = device_create_file(&csrow->dev,
  334. dynamic_csrow_ce_count_attr[chan]);
  335. if (err < 0) {
  336. device_remove_file(&csrow->dev,
  337. dynamic_csrow_dimm_attr[chan]);
  338. goto error;
  339. }
  340. }
  341. return 0;
  342. error:
  343. for (--chan; chan >= 0; chan--) {
  344. device_remove_file(&csrow->dev,
  345. dynamic_csrow_dimm_attr[chan]);
  346. device_remove_file(&csrow->dev,
  347. dynamic_csrow_ce_count_attr[chan]);
  348. }
  349. put_device(&csrow->dev);
  350. return err;
  351. }
  352. /* Create a CSROW object under specifed edac_mc_device */
  353. static int edac_create_csrow_objects(struct mem_ctl_info *mci)
  354. {
  355. int err, i, chan;
  356. struct csrow_info *csrow;
  357. for (i = 0; i < mci->nr_csrows; i++) {
  358. csrow = mci->csrows[i];
  359. if (!nr_pages_per_csrow(csrow))
  360. continue;
  361. err = edac_create_csrow_object(mci, mci->csrows[i], i);
  362. if (err < 0) {
  363. edac_dbg(1,
  364. "failure: create csrow objects for csrow %d\n",
  365. i);
  366. goto error;
  367. }
  368. }
  369. return 0;
  370. error:
  371. for (--i; i >= 0; i--) {
  372. csrow = mci->csrows[i];
  373. if (!nr_pages_per_csrow(csrow))
  374. continue;
  375. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  376. if (!csrow->channels[chan]->dimm->nr_pages)
  377. continue;
  378. device_remove_file(&csrow->dev,
  379. dynamic_csrow_dimm_attr[chan]);
  380. device_remove_file(&csrow->dev,
  381. dynamic_csrow_ce_count_attr[chan]);
  382. }
  383. put_device(&mci->csrows[i]->dev);
  384. }
  385. return err;
  386. }
  387. static void edac_delete_csrow_objects(struct mem_ctl_info *mci)
  388. {
  389. int i, chan;
  390. struct csrow_info *csrow;
  391. for (i = mci->nr_csrows - 1; i >= 0; i--) {
  392. csrow = mci->csrows[i];
  393. if (!nr_pages_per_csrow(csrow))
  394. continue;
  395. for (chan = csrow->nr_channels - 1; chan >= 0; chan--) {
  396. if (!csrow->channels[chan]->dimm->nr_pages)
  397. continue;
  398. edac_dbg(1, "Removing csrow %d channel %d sysfs nodes\n",
  399. i, chan);
  400. device_remove_file(&csrow->dev,
  401. dynamic_csrow_dimm_attr[chan]);
  402. device_remove_file(&csrow->dev,
  403. dynamic_csrow_ce_count_attr[chan]);
  404. }
  405. device_unregister(&mci->csrows[i]->dev);
  406. }
  407. }
  408. #endif
  409. /*
  410. * Per-dimm (or per-rank) devices
  411. */
  412. #define to_dimm(k) container_of(k, struct dimm_info, dev)
  413. /* show/store functions for DIMM Label attributes */
  414. static ssize_t dimmdev_location_show(struct device *dev,
  415. struct device_attribute *mattr, char *data)
  416. {
  417. struct dimm_info *dimm = to_dimm(dev);
  418. return edac_dimm_info_location(dimm, data, PAGE_SIZE);
  419. }
  420. static ssize_t dimmdev_label_show(struct device *dev,
  421. struct device_attribute *mattr, char *data)
  422. {
  423. struct dimm_info *dimm = to_dimm(dev);
  424. /* if field has not been initialized, there is nothing to send */
  425. if (!dimm->label[0])
  426. return 0;
  427. return snprintf(data, EDAC_MC_LABEL_LEN, "%s\n", dimm->label);
  428. }
  429. static ssize_t dimmdev_label_store(struct device *dev,
  430. struct device_attribute *mattr,
  431. const char *data,
  432. size_t count)
  433. {
  434. struct dimm_info *dimm = to_dimm(dev);
  435. ssize_t max_size = 0;
  436. max_size = min((ssize_t) count, (ssize_t) EDAC_MC_LABEL_LEN - 1);
  437. strncpy(dimm->label, data, max_size);
  438. dimm->label[max_size] = '\0';
  439. return max_size;
  440. }
  441. static ssize_t dimmdev_size_show(struct device *dev,
  442. struct device_attribute *mattr, char *data)
  443. {
  444. struct dimm_info *dimm = to_dimm(dev);
  445. return sprintf(data, "%u\n", PAGES_TO_MiB(dimm->nr_pages));
  446. }
  447. static ssize_t dimmdev_mem_type_show(struct device *dev,
  448. struct device_attribute *mattr, char *data)
  449. {
  450. struct dimm_info *dimm = to_dimm(dev);
  451. return sprintf(data, "%s\n", mem_types[dimm->mtype]);
  452. }
  453. static ssize_t dimmdev_dev_type_show(struct device *dev,
  454. struct device_attribute *mattr, char *data)
  455. {
  456. struct dimm_info *dimm = to_dimm(dev);
  457. return sprintf(data, "%s\n", dev_types[dimm->dtype]);
  458. }
  459. static ssize_t dimmdev_edac_mode_show(struct device *dev,
  460. struct device_attribute *mattr,
  461. char *data)
  462. {
  463. struct dimm_info *dimm = to_dimm(dev);
  464. return sprintf(data, "%s\n", edac_caps[dimm->edac_mode]);
  465. }
  466. /* dimm/rank attribute files */
  467. static DEVICE_ATTR(dimm_label, S_IRUGO | S_IWUSR,
  468. dimmdev_label_show, dimmdev_label_store);
  469. static DEVICE_ATTR(dimm_location, S_IRUGO, dimmdev_location_show, NULL);
  470. static DEVICE_ATTR(size, S_IRUGO, dimmdev_size_show, NULL);
  471. static DEVICE_ATTR(dimm_mem_type, S_IRUGO, dimmdev_mem_type_show, NULL);
  472. static DEVICE_ATTR(dimm_dev_type, S_IRUGO, dimmdev_dev_type_show, NULL);
  473. static DEVICE_ATTR(dimm_edac_mode, S_IRUGO, dimmdev_edac_mode_show, NULL);
  474. /* attributes of the dimm<id>/rank<id> object */
  475. static struct attribute *dimm_attrs[] = {
  476. &dev_attr_dimm_label.attr,
  477. &dev_attr_dimm_location.attr,
  478. &dev_attr_size.attr,
  479. &dev_attr_dimm_mem_type.attr,
  480. &dev_attr_dimm_dev_type.attr,
  481. &dev_attr_dimm_edac_mode.attr,
  482. NULL,
  483. };
  484. static struct attribute_group dimm_attr_grp = {
  485. .attrs = dimm_attrs,
  486. };
  487. static const struct attribute_group *dimm_attr_groups[] = {
  488. &dimm_attr_grp,
  489. NULL
  490. };
  491. static void dimm_attr_release(struct device *dev)
  492. {
  493. struct dimm_info *dimm = container_of(dev, struct dimm_info, dev);
  494. edac_dbg(1, "Releasing dimm device %s\n", dev_name(dev));
  495. kfree(dimm);
  496. }
  497. static struct device_type dimm_attr_type = {
  498. .groups = dimm_attr_groups,
  499. .release = dimm_attr_release,
  500. };
  501. /* Create a DIMM object under specifed memory controller device */
  502. static int edac_create_dimm_object(struct mem_ctl_info *mci,
  503. struct dimm_info *dimm,
  504. int index)
  505. {
  506. int err;
  507. dimm->mci = mci;
  508. dimm->dev.type = &dimm_attr_type;
  509. dimm->dev.bus = mci->bus;
  510. device_initialize(&dimm->dev);
  511. dimm->dev.parent = &mci->dev;
  512. if (mci->csbased)
  513. dev_set_name(&dimm->dev, "rank%d", index);
  514. else
  515. dev_set_name(&dimm->dev, "dimm%d", index);
  516. dev_set_drvdata(&dimm->dev, dimm);
  517. pm_runtime_forbid(&mci->dev);
  518. err = device_add(&dimm->dev);
  519. edac_dbg(0, "creating rank/dimm device %s\n", dev_name(&dimm->dev));
  520. return err;
  521. }
  522. /*
  523. * Memory controller device
  524. */
  525. #define to_mci(k) container_of(k, struct mem_ctl_info, dev)
  526. static ssize_t mci_reset_counters_store(struct device *dev,
  527. struct device_attribute *mattr,
  528. const char *data, size_t count)
  529. {
  530. struct mem_ctl_info *mci = to_mci(dev);
  531. int cnt, row, chan, i;
  532. mci->ue_mc = 0;
  533. mci->ce_mc = 0;
  534. mci->ue_noinfo_count = 0;
  535. mci->ce_noinfo_count = 0;
  536. for (row = 0; row < mci->nr_csrows; row++) {
  537. struct csrow_info *ri = mci->csrows[row];
  538. ri->ue_count = 0;
  539. ri->ce_count = 0;
  540. for (chan = 0; chan < ri->nr_channels; chan++)
  541. ri->channels[chan]->ce_count = 0;
  542. }
  543. cnt = 1;
  544. for (i = 0; i < mci->n_layers; i++) {
  545. cnt *= mci->layers[i].size;
  546. memset(mci->ce_per_layer[i], 0, cnt * sizeof(u32));
  547. memset(mci->ue_per_layer[i], 0, cnt * sizeof(u32));
  548. }
  549. mci->start_time = jiffies;
  550. return count;
  551. }
  552. /* Memory scrubbing interface:
  553. *
  554. * A MC driver can limit the scrubbing bandwidth based on the CPU type.
  555. * Therefore, ->set_sdram_scrub_rate should be made to return the actual
  556. * bandwidth that is accepted or 0 when scrubbing is to be disabled.
  557. *
  558. * Negative value still means that an error has occurred while setting
  559. * the scrub rate.
  560. */
  561. static ssize_t mci_sdram_scrub_rate_store(struct device *dev,
  562. struct device_attribute *mattr,
  563. const char *data, size_t count)
  564. {
  565. struct mem_ctl_info *mci = to_mci(dev);
  566. unsigned long bandwidth = 0;
  567. int new_bw = 0;
  568. if (kstrtoul(data, 10, &bandwidth) < 0)
  569. return -EINVAL;
  570. new_bw = mci->set_sdram_scrub_rate(mci, bandwidth);
  571. if (new_bw < 0) {
  572. edac_printk(KERN_WARNING, EDAC_MC,
  573. "Error setting scrub rate to: %lu\n", bandwidth);
  574. return -EINVAL;
  575. }
  576. return count;
  577. }
  578. /*
  579. * ->get_sdram_scrub_rate() return value semantics same as above.
  580. */
  581. static ssize_t mci_sdram_scrub_rate_show(struct device *dev,
  582. struct device_attribute *mattr,
  583. char *data)
  584. {
  585. struct mem_ctl_info *mci = to_mci(dev);
  586. int bandwidth = 0;
  587. bandwidth = mci->get_sdram_scrub_rate(mci);
  588. if (bandwidth < 0) {
  589. edac_printk(KERN_DEBUG, EDAC_MC, "Error reading scrub rate\n");
  590. return bandwidth;
  591. }
  592. return sprintf(data, "%d\n", bandwidth);
  593. }
  594. /* default attribute files for the MCI object */
  595. static ssize_t mci_ue_count_show(struct device *dev,
  596. struct device_attribute *mattr,
  597. char *data)
  598. {
  599. struct mem_ctl_info *mci = to_mci(dev);
  600. return sprintf(data, "%d\n", mci->ue_mc);
  601. }
  602. static ssize_t mci_ce_count_show(struct device *dev,
  603. struct device_attribute *mattr,
  604. char *data)
  605. {
  606. struct mem_ctl_info *mci = to_mci(dev);
  607. return sprintf(data, "%d\n", mci->ce_mc);
  608. }
  609. static ssize_t mci_ce_noinfo_show(struct device *dev,
  610. struct device_attribute *mattr,
  611. char *data)
  612. {
  613. struct mem_ctl_info *mci = to_mci(dev);
  614. return sprintf(data, "%d\n", mci->ce_noinfo_count);
  615. }
  616. static ssize_t mci_ue_noinfo_show(struct device *dev,
  617. struct device_attribute *mattr,
  618. char *data)
  619. {
  620. struct mem_ctl_info *mci = to_mci(dev);
  621. return sprintf(data, "%d\n", mci->ue_noinfo_count);
  622. }
  623. static ssize_t mci_seconds_show(struct device *dev,
  624. struct device_attribute *mattr,
  625. char *data)
  626. {
  627. struct mem_ctl_info *mci = to_mci(dev);
  628. return sprintf(data, "%ld\n", (jiffies - mci->start_time) / HZ);
  629. }
  630. static ssize_t mci_ctl_name_show(struct device *dev,
  631. struct device_attribute *mattr,
  632. char *data)
  633. {
  634. struct mem_ctl_info *mci = to_mci(dev);
  635. return sprintf(data, "%s\n", mci->ctl_name);
  636. }
  637. static ssize_t mci_size_mb_show(struct device *dev,
  638. struct device_attribute *mattr,
  639. char *data)
  640. {
  641. struct mem_ctl_info *mci = to_mci(dev);
  642. int total_pages = 0, csrow_idx, j;
  643. for (csrow_idx = 0; csrow_idx < mci->nr_csrows; csrow_idx++) {
  644. struct csrow_info *csrow = mci->csrows[csrow_idx];
  645. for (j = 0; j < csrow->nr_channels; j++) {
  646. struct dimm_info *dimm = csrow->channels[j]->dimm;
  647. total_pages += dimm->nr_pages;
  648. }
  649. }
  650. return sprintf(data, "%u\n", PAGES_TO_MiB(total_pages));
  651. }
  652. static ssize_t mci_max_location_show(struct device *dev,
  653. struct device_attribute *mattr,
  654. char *data)
  655. {
  656. struct mem_ctl_info *mci = to_mci(dev);
  657. int i;
  658. char *p = data;
  659. for (i = 0; i < mci->n_layers; i++) {
  660. p += sprintf(p, "%s %d ",
  661. edac_layer_name[mci->layers[i].type],
  662. mci->layers[i].size - 1);
  663. }
  664. return p - data;
  665. }
  666. #ifdef CONFIG_EDAC_DEBUG
  667. static ssize_t edac_fake_inject_write(struct file *file,
  668. const char __user *data,
  669. size_t count, loff_t *ppos)
  670. {
  671. struct device *dev = file->private_data;
  672. struct mem_ctl_info *mci = to_mci(dev);
  673. static enum hw_event_mc_err_type type;
  674. u16 errcount = mci->fake_inject_count;
  675. if (!errcount)
  676. errcount = 1;
  677. type = mci->fake_inject_ue ? HW_EVENT_ERR_UNCORRECTED
  678. : HW_EVENT_ERR_CORRECTED;
  679. printk(KERN_DEBUG
  680. "Generating %d %s fake error%s to %d.%d.%d to test core handling. NOTE: this won't test the driver-specific decoding logic.\n",
  681. errcount,
  682. (type == HW_EVENT_ERR_UNCORRECTED) ? "UE" : "CE",
  683. errcount > 1 ? "s" : "",
  684. mci->fake_inject_layer[0],
  685. mci->fake_inject_layer[1],
  686. mci->fake_inject_layer[2]
  687. );
  688. edac_mc_handle_error(type, mci, errcount, 0, 0, 0,
  689. mci->fake_inject_layer[0],
  690. mci->fake_inject_layer[1],
  691. mci->fake_inject_layer[2],
  692. "FAKE ERROR", "for EDAC testing only");
  693. return count;
  694. }
  695. static const struct file_operations debug_fake_inject_fops = {
  696. .open = simple_open,
  697. .write = edac_fake_inject_write,
  698. .llseek = generic_file_llseek,
  699. };
  700. #endif
  701. /* default Control file */
  702. DEVICE_ATTR(reset_counters, S_IWUSR, NULL, mci_reset_counters_store);
  703. /* default Attribute files */
  704. DEVICE_ATTR(mc_name, S_IRUGO, mci_ctl_name_show, NULL);
  705. DEVICE_ATTR(size_mb, S_IRUGO, mci_size_mb_show, NULL);
  706. DEVICE_ATTR(seconds_since_reset, S_IRUGO, mci_seconds_show, NULL);
  707. DEVICE_ATTR(ue_noinfo_count, S_IRUGO, mci_ue_noinfo_show, NULL);
  708. DEVICE_ATTR(ce_noinfo_count, S_IRUGO, mci_ce_noinfo_show, NULL);
  709. DEVICE_ATTR(ue_count, S_IRUGO, mci_ue_count_show, NULL);
  710. DEVICE_ATTR(ce_count, S_IRUGO, mci_ce_count_show, NULL);
  711. DEVICE_ATTR(max_location, S_IRUGO, mci_max_location_show, NULL);
  712. /* memory scrubber attribute file */
  713. DEVICE_ATTR(sdram_scrub_rate, 0, NULL, NULL);
  714. static struct attribute *mci_attrs[] = {
  715. &dev_attr_reset_counters.attr,
  716. &dev_attr_mc_name.attr,
  717. &dev_attr_size_mb.attr,
  718. &dev_attr_seconds_since_reset.attr,
  719. &dev_attr_ue_noinfo_count.attr,
  720. &dev_attr_ce_noinfo_count.attr,
  721. &dev_attr_ue_count.attr,
  722. &dev_attr_ce_count.attr,
  723. &dev_attr_max_location.attr,
  724. NULL
  725. };
  726. static struct attribute_group mci_attr_grp = {
  727. .attrs = mci_attrs,
  728. };
  729. static const struct attribute_group *mci_attr_groups[] = {
  730. &mci_attr_grp,
  731. NULL
  732. };
  733. static void mci_attr_release(struct device *dev)
  734. {
  735. struct mem_ctl_info *mci = container_of(dev, struct mem_ctl_info, dev);
  736. edac_dbg(1, "Releasing csrow device %s\n", dev_name(dev));
  737. kfree(mci);
  738. }
  739. static struct device_type mci_attr_type = {
  740. .groups = mci_attr_groups,
  741. .release = mci_attr_release,
  742. };
  743. #ifdef CONFIG_EDAC_DEBUG
  744. static struct dentry *edac_debugfs;
  745. int __init edac_debugfs_init(void)
  746. {
  747. edac_debugfs = debugfs_create_dir("edac", NULL);
  748. if (IS_ERR(edac_debugfs)) {
  749. edac_debugfs = NULL;
  750. return -ENOMEM;
  751. }
  752. return 0;
  753. }
  754. void __exit edac_debugfs_exit(void)
  755. {
  756. debugfs_remove(edac_debugfs);
  757. }
  758. static int edac_create_debug_nodes(struct mem_ctl_info *mci)
  759. {
  760. struct dentry *d, *parent;
  761. char name[80];
  762. int i;
  763. if (!edac_debugfs)
  764. return -ENODEV;
  765. d = debugfs_create_dir(mci->dev.kobj.name, edac_debugfs);
  766. if (!d)
  767. return -ENOMEM;
  768. parent = d;
  769. for (i = 0; i < mci->n_layers; i++) {
  770. sprintf(name, "fake_inject_%s",
  771. edac_layer_name[mci->layers[i].type]);
  772. d = debugfs_create_u8(name, S_IRUGO | S_IWUSR, parent,
  773. &mci->fake_inject_layer[i]);
  774. if (!d)
  775. goto nomem;
  776. }
  777. d = debugfs_create_bool("fake_inject_ue", S_IRUGO | S_IWUSR, parent,
  778. &mci->fake_inject_ue);
  779. if (!d)
  780. goto nomem;
  781. d = debugfs_create_u16("fake_inject_count", S_IRUGO | S_IWUSR, parent,
  782. &mci->fake_inject_count);
  783. if (!d)
  784. goto nomem;
  785. d = debugfs_create_file("fake_inject", S_IWUSR, parent,
  786. &mci->dev,
  787. &debug_fake_inject_fops);
  788. if (!d)
  789. goto nomem;
  790. mci->debugfs = parent;
  791. return 0;
  792. nomem:
  793. debugfs_remove(mci->debugfs);
  794. return -ENOMEM;
  795. }
  796. #endif
  797. /*
  798. * Create a new Memory Controller kobject instance,
  799. * mc<id> under the 'mc' directory
  800. *
  801. * Return:
  802. * 0 Success
  803. * !0 Failure
  804. */
  805. int edac_create_sysfs_mci_device(struct mem_ctl_info *mci)
  806. {
  807. int i, err;
  808. /*
  809. * The memory controller needs its own bus, in order to avoid
  810. * namespace conflicts at /sys/bus/edac.
  811. */
  812. mci->bus->name = kasprintf(GFP_KERNEL, "mc%d", mci->mc_idx);
  813. if (!mci->bus->name)
  814. return -ENOMEM;
  815. edac_dbg(0, "creating bus %s\n", mci->bus->name);
  816. err = bus_register(mci->bus);
  817. if (err < 0)
  818. return err;
  819. /* get the /sys/devices/system/edac subsys reference */
  820. mci->dev.type = &mci_attr_type;
  821. device_initialize(&mci->dev);
  822. mci->dev.parent = mci_pdev;
  823. mci->dev.bus = mci->bus;
  824. dev_set_name(&mci->dev, "mc%d", mci->mc_idx);
  825. dev_set_drvdata(&mci->dev, mci);
  826. pm_runtime_forbid(&mci->dev);
  827. edac_dbg(0, "creating device %s\n", dev_name(&mci->dev));
  828. err = device_add(&mci->dev);
  829. if (err < 0) {
  830. edac_dbg(1, "failure: create device %s\n", dev_name(&mci->dev));
  831. bus_unregister(mci->bus);
  832. kfree(mci->bus->name);
  833. return err;
  834. }
  835. if (mci->set_sdram_scrub_rate || mci->get_sdram_scrub_rate) {
  836. if (mci->get_sdram_scrub_rate) {
  837. dev_attr_sdram_scrub_rate.attr.mode |= S_IRUGO;
  838. dev_attr_sdram_scrub_rate.show = &mci_sdram_scrub_rate_show;
  839. }
  840. if (mci->set_sdram_scrub_rate) {
  841. dev_attr_sdram_scrub_rate.attr.mode |= S_IWUSR;
  842. dev_attr_sdram_scrub_rate.store = &mci_sdram_scrub_rate_store;
  843. }
  844. err = device_create_file(&mci->dev,
  845. &dev_attr_sdram_scrub_rate);
  846. if (err) {
  847. edac_dbg(1, "failure: create sdram_scrub_rate\n");
  848. goto fail2;
  849. }
  850. }
  851. /*
  852. * Create the dimm/rank devices
  853. */
  854. for (i = 0; i < mci->tot_dimms; i++) {
  855. struct dimm_info *dimm = mci->dimms[i];
  856. /* Only expose populated DIMMs */
  857. if (dimm->nr_pages == 0)
  858. continue;
  859. #ifdef CONFIG_EDAC_DEBUG
  860. edac_dbg(1, "creating dimm%d, located at ", i);
  861. if (edac_debug_level >= 1) {
  862. int lay;
  863. for (lay = 0; lay < mci->n_layers; lay++)
  864. printk(KERN_CONT "%s %d ",
  865. edac_layer_name[mci->layers[lay].type],
  866. dimm->location[lay]);
  867. printk(KERN_CONT "\n");
  868. }
  869. #endif
  870. err = edac_create_dimm_object(mci, dimm, i);
  871. if (err) {
  872. edac_dbg(1, "failure: create dimm %d obj\n", i);
  873. goto fail;
  874. }
  875. }
  876. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  877. err = edac_create_csrow_objects(mci);
  878. if (err < 0)
  879. goto fail;
  880. #endif
  881. #ifdef CONFIG_EDAC_DEBUG
  882. edac_create_debug_nodes(mci);
  883. #endif
  884. return 0;
  885. fail:
  886. for (i--; i >= 0; i--) {
  887. struct dimm_info *dimm = mci->dimms[i];
  888. if (dimm->nr_pages == 0)
  889. continue;
  890. device_unregister(&dimm->dev);
  891. }
  892. fail2:
  893. device_unregister(&mci->dev);
  894. bus_unregister(mci->bus);
  895. kfree(mci->bus->name);
  896. return err;
  897. }
  898. /*
  899. * remove a Memory Controller instance
  900. */
  901. void edac_remove_sysfs_mci_device(struct mem_ctl_info *mci)
  902. {
  903. int i;
  904. edac_dbg(0, "\n");
  905. #ifdef CONFIG_EDAC_DEBUG
  906. debugfs_remove(mci->debugfs);
  907. #endif
  908. #ifdef CONFIG_EDAC_LEGACY_SYSFS
  909. edac_delete_csrow_objects(mci);
  910. #endif
  911. for (i = 0; i < mci->tot_dimms; i++) {
  912. struct dimm_info *dimm = mci->dimms[i];
  913. if (dimm->nr_pages == 0)
  914. continue;
  915. edac_dbg(0, "removing device %s\n", dev_name(&dimm->dev));
  916. device_unregister(&dimm->dev);
  917. }
  918. }
  919. void edac_unregister_sysfs(struct mem_ctl_info *mci)
  920. {
  921. edac_dbg(1, "Unregistering device %s\n", dev_name(&mci->dev));
  922. device_unregister(&mci->dev);
  923. bus_unregister(mci->bus);
  924. kfree(mci->bus->name);
  925. }
  926. static void mc_attr_release(struct device *dev)
  927. {
  928. /*
  929. * There's no container structure here, as this is just the mci
  930. * parent device, used to create the /sys/devices/mc sysfs node.
  931. * So, there are no attributes on it.
  932. */
  933. edac_dbg(1, "Releasing device %s\n", dev_name(dev));
  934. kfree(dev);
  935. }
  936. static struct device_type mc_attr_type = {
  937. .release = mc_attr_release,
  938. };
  939. /*
  940. * Init/exit code for the module. Basically, creates/removes /sys/class/rc
  941. */
  942. int __init edac_mc_sysfs_init(void)
  943. {
  944. struct bus_type *edac_subsys;
  945. int err;
  946. /* get the /sys/devices/system/edac subsys reference */
  947. edac_subsys = edac_get_sysfs_subsys();
  948. if (edac_subsys == NULL) {
  949. edac_dbg(1, "no edac_subsys\n");
  950. err = -EINVAL;
  951. goto out;
  952. }
  953. mci_pdev = kzalloc(sizeof(*mci_pdev), GFP_KERNEL);
  954. if (!mci_pdev) {
  955. err = -ENOMEM;
  956. goto out_put_sysfs;
  957. }
  958. mci_pdev->bus = edac_subsys;
  959. mci_pdev->type = &mc_attr_type;
  960. device_initialize(mci_pdev);
  961. dev_set_name(mci_pdev, "mc");
  962. err = device_add(mci_pdev);
  963. if (err < 0)
  964. goto out_dev_free;
  965. edac_dbg(0, "device %s created\n", dev_name(mci_pdev));
  966. return 0;
  967. out_dev_free:
  968. kfree(mci_pdev);
  969. out_put_sysfs:
  970. edac_put_sysfs_subsys();
  971. out:
  972. return err;
  973. }
  974. void __exit edac_mc_sysfs_exit(void)
  975. {
  976. device_unregister(mci_pdev);
  977. edac_put_sysfs_subsys();
  978. }