dmaengine.c 30 KB

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  1. /*
  2. * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms of the GNU General Public License as published by the Free
  6. * Software Foundation; either version 2 of the License, or (at your option)
  7. * any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc., 59
  16. * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called COPYING.
  20. */
  21. /*
  22. * This code implements the DMA subsystem. It provides a HW-neutral interface
  23. * for other kernel code to use asynchronous memory copy capabilities,
  24. * if present, and allows different HW DMA drivers to register as providing
  25. * this capability.
  26. *
  27. * Due to the fact we are accelerating what is already a relatively fast
  28. * operation, the code goes to great lengths to avoid additional overhead,
  29. * such as locking.
  30. *
  31. * LOCKING:
  32. *
  33. * The subsystem keeps a global list of dma_device structs it is protected by a
  34. * mutex, dma_list_mutex.
  35. *
  36. * A subsystem can get access to a channel by calling dmaengine_get() followed
  37. * by dma_find_channel(), or if it has need for an exclusive channel it can call
  38. * dma_request_channel(). Once a channel is allocated a reference is taken
  39. * against its corresponding driver to disable removal.
  40. *
  41. * Each device has a channels list, which runs unlocked but is never modified
  42. * once the device is registered, it's just setup by the driver.
  43. *
  44. * See Documentation/dmaengine.txt for more details
  45. */
  46. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  47. #include <linux/dma-mapping.h>
  48. #include <linux/init.h>
  49. #include <linux/module.h>
  50. #include <linux/mm.h>
  51. #include <linux/device.h>
  52. #include <linux/dmaengine.h>
  53. #include <linux/hardirq.h>
  54. #include <linux/spinlock.h>
  55. #include <linux/percpu.h>
  56. #include <linux/rcupdate.h>
  57. #include <linux/mutex.h>
  58. #include <linux/jiffies.h>
  59. #include <linux/rculist.h>
  60. #include <linux/idr.h>
  61. #include <linux/slab.h>
  62. #include <linux/acpi.h>
  63. #include <linux/acpi_dma.h>
  64. #include <linux/of_dma.h>
  65. #include <linux/mempool.h>
  66. static DEFINE_MUTEX(dma_list_mutex);
  67. static DEFINE_IDR(dma_idr);
  68. static LIST_HEAD(dma_device_list);
  69. static long dmaengine_ref_count;
  70. /* --- sysfs implementation --- */
  71. /**
  72. * dev_to_dma_chan - convert a device pointer to the its sysfs container object
  73. * @dev - device node
  74. *
  75. * Must be called under dma_list_mutex
  76. */
  77. static struct dma_chan *dev_to_dma_chan(struct device *dev)
  78. {
  79. struct dma_chan_dev *chan_dev;
  80. chan_dev = container_of(dev, typeof(*chan_dev), device);
  81. return chan_dev->chan;
  82. }
  83. static ssize_t memcpy_count_show(struct device *dev,
  84. struct device_attribute *attr, char *buf)
  85. {
  86. struct dma_chan *chan;
  87. unsigned long count = 0;
  88. int i;
  89. int err;
  90. mutex_lock(&dma_list_mutex);
  91. chan = dev_to_dma_chan(dev);
  92. if (chan) {
  93. for_each_possible_cpu(i)
  94. count += per_cpu_ptr(chan->local, i)->memcpy_count;
  95. err = sprintf(buf, "%lu\n", count);
  96. } else
  97. err = -ENODEV;
  98. mutex_unlock(&dma_list_mutex);
  99. return err;
  100. }
  101. static DEVICE_ATTR_RO(memcpy_count);
  102. static ssize_t bytes_transferred_show(struct device *dev,
  103. struct device_attribute *attr, char *buf)
  104. {
  105. struct dma_chan *chan;
  106. unsigned long count = 0;
  107. int i;
  108. int err;
  109. mutex_lock(&dma_list_mutex);
  110. chan = dev_to_dma_chan(dev);
  111. if (chan) {
  112. for_each_possible_cpu(i)
  113. count += per_cpu_ptr(chan->local, i)->bytes_transferred;
  114. err = sprintf(buf, "%lu\n", count);
  115. } else
  116. err = -ENODEV;
  117. mutex_unlock(&dma_list_mutex);
  118. return err;
  119. }
  120. static DEVICE_ATTR_RO(bytes_transferred);
  121. static ssize_t in_use_show(struct device *dev, struct device_attribute *attr,
  122. char *buf)
  123. {
  124. struct dma_chan *chan;
  125. int err;
  126. mutex_lock(&dma_list_mutex);
  127. chan = dev_to_dma_chan(dev);
  128. if (chan)
  129. err = sprintf(buf, "%d\n", chan->client_count);
  130. else
  131. err = -ENODEV;
  132. mutex_unlock(&dma_list_mutex);
  133. return err;
  134. }
  135. static DEVICE_ATTR_RO(in_use);
  136. static struct attribute *dma_dev_attrs[] = {
  137. &dev_attr_memcpy_count.attr,
  138. &dev_attr_bytes_transferred.attr,
  139. &dev_attr_in_use.attr,
  140. NULL,
  141. };
  142. ATTRIBUTE_GROUPS(dma_dev);
  143. static void chan_dev_release(struct device *dev)
  144. {
  145. struct dma_chan_dev *chan_dev;
  146. chan_dev = container_of(dev, typeof(*chan_dev), device);
  147. if (atomic_dec_and_test(chan_dev->idr_ref)) {
  148. mutex_lock(&dma_list_mutex);
  149. idr_remove(&dma_idr, chan_dev->dev_id);
  150. mutex_unlock(&dma_list_mutex);
  151. kfree(chan_dev->idr_ref);
  152. }
  153. kfree(chan_dev);
  154. }
  155. static struct class dma_devclass = {
  156. .name = "dma",
  157. .dev_groups = dma_dev_groups,
  158. .dev_release = chan_dev_release,
  159. };
  160. /* --- client and device registration --- */
  161. #define dma_device_satisfies_mask(device, mask) \
  162. __dma_device_satisfies_mask((device), &(mask))
  163. static int
  164. __dma_device_satisfies_mask(struct dma_device *device,
  165. const dma_cap_mask_t *want)
  166. {
  167. dma_cap_mask_t has;
  168. bitmap_and(has.bits, want->bits, device->cap_mask.bits,
  169. DMA_TX_TYPE_END);
  170. return bitmap_equal(want->bits, has.bits, DMA_TX_TYPE_END);
  171. }
  172. static struct module *dma_chan_to_owner(struct dma_chan *chan)
  173. {
  174. return chan->device->dev->driver->owner;
  175. }
  176. /**
  177. * balance_ref_count - catch up the channel reference count
  178. * @chan - channel to balance ->client_count versus dmaengine_ref_count
  179. *
  180. * balance_ref_count must be called under dma_list_mutex
  181. */
  182. static void balance_ref_count(struct dma_chan *chan)
  183. {
  184. struct module *owner = dma_chan_to_owner(chan);
  185. while (chan->client_count < dmaengine_ref_count) {
  186. __module_get(owner);
  187. chan->client_count++;
  188. }
  189. }
  190. /**
  191. * dma_chan_get - try to grab a dma channel's parent driver module
  192. * @chan - channel to grab
  193. *
  194. * Must be called under dma_list_mutex
  195. */
  196. static int dma_chan_get(struct dma_chan *chan)
  197. {
  198. int err = -ENODEV;
  199. struct module *owner = dma_chan_to_owner(chan);
  200. if (chan->client_count) {
  201. __module_get(owner);
  202. err = 0;
  203. } else if (try_module_get(owner))
  204. err = 0;
  205. if (err == 0)
  206. chan->client_count++;
  207. /* allocate upon first client reference */
  208. if (chan->client_count == 1 && err == 0) {
  209. int desc_cnt = chan->device->device_alloc_chan_resources(chan);
  210. if (desc_cnt < 0) {
  211. err = desc_cnt;
  212. chan->client_count = 0;
  213. module_put(owner);
  214. } else if (!dma_has_cap(DMA_PRIVATE, chan->device->cap_mask))
  215. balance_ref_count(chan);
  216. }
  217. return err;
  218. }
  219. /**
  220. * dma_chan_put - drop a reference to a dma channel's parent driver module
  221. * @chan - channel to release
  222. *
  223. * Must be called under dma_list_mutex
  224. */
  225. static void dma_chan_put(struct dma_chan *chan)
  226. {
  227. if (!chan->client_count)
  228. return; /* this channel failed alloc_chan_resources */
  229. chan->client_count--;
  230. module_put(dma_chan_to_owner(chan));
  231. if (chan->client_count == 0)
  232. chan->device->device_free_chan_resources(chan);
  233. }
  234. enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
  235. {
  236. enum dma_status status;
  237. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  238. dma_async_issue_pending(chan);
  239. do {
  240. status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
  241. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  242. pr_err("%s: timeout!\n", __func__);
  243. return DMA_ERROR;
  244. }
  245. if (status != DMA_IN_PROGRESS)
  246. break;
  247. cpu_relax();
  248. } while (1);
  249. return status;
  250. }
  251. EXPORT_SYMBOL(dma_sync_wait);
  252. /**
  253. * dma_cap_mask_all - enable iteration over all operation types
  254. */
  255. static dma_cap_mask_t dma_cap_mask_all;
  256. /**
  257. * dma_chan_tbl_ent - tracks channel allocations per core/operation
  258. * @chan - associated channel for this entry
  259. */
  260. struct dma_chan_tbl_ent {
  261. struct dma_chan *chan;
  262. };
  263. /**
  264. * channel_table - percpu lookup table for memory-to-memory offload providers
  265. */
  266. static struct dma_chan_tbl_ent __percpu *channel_table[DMA_TX_TYPE_END];
  267. static int __init dma_channel_table_init(void)
  268. {
  269. enum dma_transaction_type cap;
  270. int err = 0;
  271. bitmap_fill(dma_cap_mask_all.bits, DMA_TX_TYPE_END);
  272. /* 'interrupt', 'private', and 'slave' are channel capabilities,
  273. * but are not associated with an operation so they do not need
  274. * an entry in the channel_table
  275. */
  276. clear_bit(DMA_INTERRUPT, dma_cap_mask_all.bits);
  277. clear_bit(DMA_PRIVATE, dma_cap_mask_all.bits);
  278. clear_bit(DMA_SLAVE, dma_cap_mask_all.bits);
  279. for_each_dma_cap_mask(cap, dma_cap_mask_all) {
  280. channel_table[cap] = alloc_percpu(struct dma_chan_tbl_ent);
  281. if (!channel_table[cap]) {
  282. err = -ENOMEM;
  283. break;
  284. }
  285. }
  286. if (err) {
  287. pr_err("initialization failure\n");
  288. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  289. free_percpu(channel_table[cap]);
  290. }
  291. return err;
  292. }
  293. arch_initcall(dma_channel_table_init);
  294. /**
  295. * dma_find_channel - find a channel to carry out the operation
  296. * @tx_type: transaction type
  297. */
  298. struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
  299. {
  300. return this_cpu_read(channel_table[tx_type]->chan);
  301. }
  302. EXPORT_SYMBOL(dma_find_channel);
  303. /*
  304. * net_dma_find_channel - find a channel for net_dma
  305. * net_dma has alignment requirements
  306. */
  307. struct dma_chan *net_dma_find_channel(void)
  308. {
  309. struct dma_chan *chan = dma_find_channel(DMA_MEMCPY);
  310. if (chan && !is_dma_copy_aligned(chan->device, 1, 1, 1))
  311. return NULL;
  312. return chan;
  313. }
  314. EXPORT_SYMBOL(net_dma_find_channel);
  315. /**
  316. * dma_issue_pending_all - flush all pending operations across all channels
  317. */
  318. void dma_issue_pending_all(void)
  319. {
  320. struct dma_device *device;
  321. struct dma_chan *chan;
  322. rcu_read_lock();
  323. list_for_each_entry_rcu(device, &dma_device_list, global_node) {
  324. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  325. continue;
  326. list_for_each_entry(chan, &device->channels, device_node)
  327. if (chan->client_count)
  328. device->device_issue_pending(chan);
  329. }
  330. rcu_read_unlock();
  331. }
  332. EXPORT_SYMBOL(dma_issue_pending_all);
  333. /**
  334. * dma_chan_is_local - returns true if the channel is in the same numa-node as the cpu
  335. */
  336. static bool dma_chan_is_local(struct dma_chan *chan, int cpu)
  337. {
  338. int node = dev_to_node(chan->device->dev);
  339. return node == -1 || cpumask_test_cpu(cpu, cpumask_of_node(node));
  340. }
  341. /**
  342. * min_chan - returns the channel with min count and in the same numa-node as the cpu
  343. * @cap: capability to match
  344. * @cpu: cpu index which the channel should be close to
  345. *
  346. * If some channels are close to the given cpu, the one with the lowest
  347. * reference count is returned. Otherwise, cpu is ignored and only the
  348. * reference count is taken into account.
  349. * Must be called under dma_list_mutex.
  350. */
  351. static struct dma_chan *min_chan(enum dma_transaction_type cap, int cpu)
  352. {
  353. struct dma_device *device;
  354. struct dma_chan *chan;
  355. struct dma_chan *min = NULL;
  356. struct dma_chan *localmin = NULL;
  357. list_for_each_entry(device, &dma_device_list, global_node) {
  358. if (!dma_has_cap(cap, device->cap_mask) ||
  359. dma_has_cap(DMA_PRIVATE, device->cap_mask))
  360. continue;
  361. list_for_each_entry(chan, &device->channels, device_node) {
  362. if (!chan->client_count)
  363. continue;
  364. if (!min || chan->table_count < min->table_count)
  365. min = chan;
  366. if (dma_chan_is_local(chan, cpu))
  367. if (!localmin ||
  368. chan->table_count < localmin->table_count)
  369. localmin = chan;
  370. }
  371. }
  372. chan = localmin ? localmin : min;
  373. if (chan)
  374. chan->table_count++;
  375. return chan;
  376. }
  377. /**
  378. * dma_channel_rebalance - redistribute the available channels
  379. *
  380. * Optimize for cpu isolation (each cpu gets a dedicated channel for an
  381. * operation type) in the SMP case, and operation isolation (avoid
  382. * multi-tasking channels) in the non-SMP case. Must be called under
  383. * dma_list_mutex.
  384. */
  385. static void dma_channel_rebalance(void)
  386. {
  387. struct dma_chan *chan;
  388. struct dma_device *device;
  389. int cpu;
  390. int cap;
  391. /* undo the last distribution */
  392. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  393. for_each_possible_cpu(cpu)
  394. per_cpu_ptr(channel_table[cap], cpu)->chan = NULL;
  395. list_for_each_entry(device, &dma_device_list, global_node) {
  396. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  397. continue;
  398. list_for_each_entry(chan, &device->channels, device_node)
  399. chan->table_count = 0;
  400. }
  401. /* don't populate the channel_table if no clients are available */
  402. if (!dmaengine_ref_count)
  403. return;
  404. /* redistribute available channels */
  405. for_each_dma_cap_mask(cap, dma_cap_mask_all)
  406. for_each_online_cpu(cpu) {
  407. chan = min_chan(cap, cpu);
  408. per_cpu_ptr(channel_table[cap], cpu)->chan = chan;
  409. }
  410. }
  411. static struct dma_chan *private_candidate(const dma_cap_mask_t *mask,
  412. struct dma_device *dev,
  413. dma_filter_fn fn, void *fn_param)
  414. {
  415. struct dma_chan *chan;
  416. if (!__dma_device_satisfies_mask(dev, mask)) {
  417. pr_debug("%s: wrong capabilities\n", __func__);
  418. return NULL;
  419. }
  420. /* devices with multiple channels need special handling as we need to
  421. * ensure that all channels are either private or public.
  422. */
  423. if (dev->chancnt > 1 && !dma_has_cap(DMA_PRIVATE, dev->cap_mask))
  424. list_for_each_entry(chan, &dev->channels, device_node) {
  425. /* some channels are already publicly allocated */
  426. if (chan->client_count)
  427. return NULL;
  428. }
  429. list_for_each_entry(chan, &dev->channels, device_node) {
  430. if (chan->client_count) {
  431. pr_debug("%s: %s busy\n",
  432. __func__, dma_chan_name(chan));
  433. continue;
  434. }
  435. if (fn && !fn(chan, fn_param)) {
  436. pr_debug("%s: %s filter said false\n",
  437. __func__, dma_chan_name(chan));
  438. continue;
  439. }
  440. return chan;
  441. }
  442. return NULL;
  443. }
  444. /**
  445. * dma_request_slave_channel - try to get specific channel exclusively
  446. * @chan: target channel
  447. */
  448. struct dma_chan *dma_get_slave_channel(struct dma_chan *chan)
  449. {
  450. int err = -EBUSY;
  451. /* lock against __dma_request_channel */
  452. mutex_lock(&dma_list_mutex);
  453. if (chan->client_count == 0) {
  454. err = dma_chan_get(chan);
  455. if (err)
  456. pr_debug("%s: failed to get %s: (%d)\n",
  457. __func__, dma_chan_name(chan), err);
  458. } else
  459. chan = NULL;
  460. mutex_unlock(&dma_list_mutex);
  461. return chan;
  462. }
  463. EXPORT_SYMBOL_GPL(dma_get_slave_channel);
  464. struct dma_chan *dma_get_any_slave_channel(struct dma_device *device)
  465. {
  466. dma_cap_mask_t mask;
  467. struct dma_chan *chan;
  468. int err;
  469. dma_cap_zero(mask);
  470. dma_cap_set(DMA_SLAVE, mask);
  471. /* lock against __dma_request_channel */
  472. mutex_lock(&dma_list_mutex);
  473. chan = private_candidate(&mask, device, NULL, NULL);
  474. if (chan) {
  475. err = dma_chan_get(chan);
  476. if (err) {
  477. pr_debug("%s: failed to get %s: (%d)\n",
  478. __func__, dma_chan_name(chan), err);
  479. chan = NULL;
  480. }
  481. }
  482. mutex_unlock(&dma_list_mutex);
  483. return chan;
  484. }
  485. EXPORT_SYMBOL_GPL(dma_get_any_slave_channel);
  486. /**
  487. * __dma_request_channel - try to allocate an exclusive channel
  488. * @mask: capabilities that the channel must satisfy
  489. * @fn: optional callback to disposition available channels
  490. * @fn_param: opaque parameter to pass to dma_filter_fn
  491. *
  492. * Returns pointer to appropriate DMA channel on success or NULL.
  493. */
  494. struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
  495. dma_filter_fn fn, void *fn_param)
  496. {
  497. struct dma_device *device, *_d;
  498. struct dma_chan *chan = NULL;
  499. int err;
  500. /* Find a channel */
  501. mutex_lock(&dma_list_mutex);
  502. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  503. chan = private_candidate(mask, device, fn, fn_param);
  504. if (chan) {
  505. /* Found a suitable channel, try to grab, prep, and
  506. * return it. We first set DMA_PRIVATE to disable
  507. * balance_ref_count as this channel will not be
  508. * published in the general-purpose allocator
  509. */
  510. dma_cap_set(DMA_PRIVATE, device->cap_mask);
  511. device->privatecnt++;
  512. err = dma_chan_get(chan);
  513. if (err == -ENODEV) {
  514. pr_debug("%s: %s module removed\n",
  515. __func__, dma_chan_name(chan));
  516. list_del_rcu(&device->global_node);
  517. } else if (err)
  518. pr_debug("%s: failed to get %s: (%d)\n",
  519. __func__, dma_chan_name(chan), err);
  520. else
  521. break;
  522. if (--device->privatecnt == 0)
  523. dma_cap_clear(DMA_PRIVATE, device->cap_mask);
  524. chan = NULL;
  525. }
  526. }
  527. mutex_unlock(&dma_list_mutex);
  528. pr_debug("%s: %s (%s)\n",
  529. __func__,
  530. chan ? "success" : "fail",
  531. chan ? dma_chan_name(chan) : NULL);
  532. return chan;
  533. }
  534. EXPORT_SYMBOL_GPL(__dma_request_channel);
  535. /**
  536. * dma_request_slave_channel - try to allocate an exclusive slave channel
  537. * @dev: pointer to client device structure
  538. * @name: slave channel name
  539. *
  540. * Returns pointer to appropriate DMA channel on success or an error pointer.
  541. */
  542. struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
  543. const char *name)
  544. {
  545. /* If device-tree is present get slave info from here */
  546. if (dev->of_node)
  547. return of_dma_request_slave_channel(dev->of_node, name);
  548. /* If device was enumerated by ACPI get slave info from here */
  549. if (ACPI_HANDLE(dev))
  550. return acpi_dma_request_slave_chan_by_name(dev, name);
  551. return ERR_PTR(-ENODEV);
  552. }
  553. EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
  554. /**
  555. * dma_request_slave_channel - try to allocate an exclusive slave channel
  556. * @dev: pointer to client device structure
  557. * @name: slave channel name
  558. *
  559. * Returns pointer to appropriate DMA channel on success or NULL.
  560. */
  561. struct dma_chan *dma_request_slave_channel(struct device *dev,
  562. const char *name)
  563. {
  564. struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
  565. if (IS_ERR(ch))
  566. return NULL;
  567. return ch;
  568. }
  569. EXPORT_SYMBOL_GPL(dma_request_slave_channel);
  570. void dma_release_channel(struct dma_chan *chan)
  571. {
  572. mutex_lock(&dma_list_mutex);
  573. WARN_ONCE(chan->client_count != 1,
  574. "chan reference count %d != 1\n", chan->client_count);
  575. dma_chan_put(chan);
  576. /* drop PRIVATE cap enabled by __dma_request_channel() */
  577. if (--chan->device->privatecnt == 0)
  578. dma_cap_clear(DMA_PRIVATE, chan->device->cap_mask);
  579. mutex_unlock(&dma_list_mutex);
  580. }
  581. EXPORT_SYMBOL_GPL(dma_release_channel);
  582. /**
  583. * dmaengine_get - register interest in dma_channels
  584. */
  585. void dmaengine_get(void)
  586. {
  587. struct dma_device *device, *_d;
  588. struct dma_chan *chan;
  589. int err;
  590. mutex_lock(&dma_list_mutex);
  591. dmaengine_ref_count++;
  592. /* try to grab channels */
  593. list_for_each_entry_safe(device, _d, &dma_device_list, global_node) {
  594. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  595. continue;
  596. list_for_each_entry(chan, &device->channels, device_node) {
  597. err = dma_chan_get(chan);
  598. if (err == -ENODEV) {
  599. /* module removed before we could use it */
  600. list_del_rcu(&device->global_node);
  601. break;
  602. } else if (err)
  603. pr_debug("%s: failed to get %s: (%d)\n",
  604. __func__, dma_chan_name(chan), err);
  605. }
  606. }
  607. /* if this is the first reference and there were channels
  608. * waiting we need to rebalance to get those channels
  609. * incorporated into the channel table
  610. */
  611. if (dmaengine_ref_count == 1)
  612. dma_channel_rebalance();
  613. mutex_unlock(&dma_list_mutex);
  614. }
  615. EXPORT_SYMBOL(dmaengine_get);
  616. /**
  617. * dmaengine_put - let dma drivers be removed when ref_count == 0
  618. */
  619. void dmaengine_put(void)
  620. {
  621. struct dma_device *device;
  622. struct dma_chan *chan;
  623. mutex_lock(&dma_list_mutex);
  624. dmaengine_ref_count--;
  625. BUG_ON(dmaengine_ref_count < 0);
  626. /* drop channel references */
  627. list_for_each_entry(device, &dma_device_list, global_node) {
  628. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  629. continue;
  630. list_for_each_entry(chan, &device->channels, device_node)
  631. dma_chan_put(chan);
  632. }
  633. mutex_unlock(&dma_list_mutex);
  634. }
  635. EXPORT_SYMBOL(dmaengine_put);
  636. static bool device_has_all_tx_types(struct dma_device *device)
  637. {
  638. /* A device that satisfies this test has channels that will never cause
  639. * an async_tx channel switch event as all possible operation types can
  640. * be handled.
  641. */
  642. #ifdef CONFIG_ASYNC_TX_DMA
  643. if (!dma_has_cap(DMA_INTERRUPT, device->cap_mask))
  644. return false;
  645. #endif
  646. #if defined(CONFIG_ASYNC_MEMCPY) || defined(CONFIG_ASYNC_MEMCPY_MODULE)
  647. if (!dma_has_cap(DMA_MEMCPY, device->cap_mask))
  648. return false;
  649. #endif
  650. #if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)
  651. if (!dma_has_cap(DMA_XOR, device->cap_mask))
  652. return false;
  653. #ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
  654. if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))
  655. return false;
  656. #endif
  657. #endif
  658. #if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)
  659. if (!dma_has_cap(DMA_PQ, device->cap_mask))
  660. return false;
  661. #ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
  662. if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))
  663. return false;
  664. #endif
  665. #endif
  666. return true;
  667. }
  668. static int get_dma_id(struct dma_device *device)
  669. {
  670. int rc;
  671. mutex_lock(&dma_list_mutex);
  672. rc = idr_alloc(&dma_idr, NULL, 0, 0, GFP_KERNEL);
  673. if (rc >= 0)
  674. device->dev_id = rc;
  675. mutex_unlock(&dma_list_mutex);
  676. return rc < 0 ? rc : 0;
  677. }
  678. /**
  679. * dma_async_device_register - registers DMA devices found
  680. * @device: &dma_device
  681. */
  682. int dma_async_device_register(struct dma_device *device)
  683. {
  684. int chancnt = 0, rc;
  685. struct dma_chan* chan;
  686. atomic_t *idr_ref;
  687. if (!device)
  688. return -ENODEV;
  689. /* validate device routines */
  690. BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
  691. !device->device_prep_dma_memcpy);
  692. BUG_ON(dma_has_cap(DMA_XOR, device->cap_mask) &&
  693. !device->device_prep_dma_xor);
  694. BUG_ON(dma_has_cap(DMA_XOR_VAL, device->cap_mask) &&
  695. !device->device_prep_dma_xor_val);
  696. BUG_ON(dma_has_cap(DMA_PQ, device->cap_mask) &&
  697. !device->device_prep_dma_pq);
  698. BUG_ON(dma_has_cap(DMA_PQ_VAL, device->cap_mask) &&
  699. !device->device_prep_dma_pq_val);
  700. BUG_ON(dma_has_cap(DMA_INTERRUPT, device->cap_mask) &&
  701. !device->device_prep_dma_interrupt);
  702. BUG_ON(dma_has_cap(DMA_SG, device->cap_mask) &&
  703. !device->device_prep_dma_sg);
  704. BUG_ON(dma_has_cap(DMA_CYCLIC, device->cap_mask) &&
  705. !device->device_prep_dma_cyclic);
  706. BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
  707. !device->device_control);
  708. BUG_ON(dma_has_cap(DMA_INTERLEAVE, device->cap_mask) &&
  709. !device->device_prep_interleaved_dma);
  710. BUG_ON(!device->device_alloc_chan_resources);
  711. BUG_ON(!device->device_free_chan_resources);
  712. BUG_ON(!device->device_tx_status);
  713. BUG_ON(!device->device_issue_pending);
  714. BUG_ON(!device->dev);
  715. /* note: this only matters in the
  716. * CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=n case
  717. */
  718. if (device_has_all_tx_types(device))
  719. dma_cap_set(DMA_ASYNC_TX, device->cap_mask);
  720. idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL);
  721. if (!idr_ref)
  722. return -ENOMEM;
  723. rc = get_dma_id(device);
  724. if (rc != 0) {
  725. kfree(idr_ref);
  726. return rc;
  727. }
  728. atomic_set(idr_ref, 0);
  729. /* represent channels in sysfs. Probably want devs too */
  730. list_for_each_entry(chan, &device->channels, device_node) {
  731. rc = -ENOMEM;
  732. chan->local = alloc_percpu(typeof(*chan->local));
  733. if (chan->local == NULL)
  734. goto err_out;
  735. chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL);
  736. if (chan->dev == NULL) {
  737. free_percpu(chan->local);
  738. chan->local = NULL;
  739. goto err_out;
  740. }
  741. chan->chan_id = chancnt++;
  742. chan->dev->device.class = &dma_devclass;
  743. chan->dev->device.parent = device->dev;
  744. chan->dev->chan = chan;
  745. chan->dev->idr_ref = idr_ref;
  746. chan->dev->dev_id = device->dev_id;
  747. atomic_inc(idr_ref);
  748. dev_set_name(&chan->dev->device, "dma%dchan%d",
  749. device->dev_id, chan->chan_id);
  750. rc = device_register(&chan->dev->device);
  751. if (rc) {
  752. free_percpu(chan->local);
  753. chan->local = NULL;
  754. kfree(chan->dev);
  755. atomic_dec(idr_ref);
  756. goto err_out;
  757. }
  758. chan->client_count = 0;
  759. }
  760. device->chancnt = chancnt;
  761. mutex_lock(&dma_list_mutex);
  762. /* take references on public channels */
  763. if (dmaengine_ref_count && !dma_has_cap(DMA_PRIVATE, device->cap_mask))
  764. list_for_each_entry(chan, &device->channels, device_node) {
  765. /* if clients are already waiting for channels we need
  766. * to take references on their behalf
  767. */
  768. if (dma_chan_get(chan) == -ENODEV) {
  769. /* note we can only get here for the first
  770. * channel as the remaining channels are
  771. * guaranteed to get a reference
  772. */
  773. rc = -ENODEV;
  774. mutex_unlock(&dma_list_mutex);
  775. goto err_out;
  776. }
  777. }
  778. list_add_tail_rcu(&device->global_node, &dma_device_list);
  779. if (dma_has_cap(DMA_PRIVATE, device->cap_mask))
  780. device->privatecnt++; /* Always private */
  781. dma_channel_rebalance();
  782. mutex_unlock(&dma_list_mutex);
  783. return 0;
  784. err_out:
  785. /* if we never registered a channel just release the idr */
  786. if (atomic_read(idr_ref) == 0) {
  787. mutex_lock(&dma_list_mutex);
  788. idr_remove(&dma_idr, device->dev_id);
  789. mutex_unlock(&dma_list_mutex);
  790. kfree(idr_ref);
  791. return rc;
  792. }
  793. list_for_each_entry(chan, &device->channels, device_node) {
  794. if (chan->local == NULL)
  795. continue;
  796. mutex_lock(&dma_list_mutex);
  797. chan->dev->chan = NULL;
  798. mutex_unlock(&dma_list_mutex);
  799. device_unregister(&chan->dev->device);
  800. free_percpu(chan->local);
  801. }
  802. return rc;
  803. }
  804. EXPORT_SYMBOL(dma_async_device_register);
  805. /**
  806. * dma_async_device_unregister - unregister a DMA device
  807. * @device: &dma_device
  808. *
  809. * This routine is called by dma driver exit routines, dmaengine holds module
  810. * references to prevent it being called while channels are in use.
  811. */
  812. void dma_async_device_unregister(struct dma_device *device)
  813. {
  814. struct dma_chan *chan;
  815. mutex_lock(&dma_list_mutex);
  816. list_del_rcu(&device->global_node);
  817. dma_channel_rebalance();
  818. mutex_unlock(&dma_list_mutex);
  819. list_for_each_entry(chan, &device->channels, device_node) {
  820. WARN_ONCE(chan->client_count,
  821. "%s called while %d clients hold a reference\n",
  822. __func__, chan->client_count);
  823. mutex_lock(&dma_list_mutex);
  824. chan->dev->chan = NULL;
  825. mutex_unlock(&dma_list_mutex);
  826. device_unregister(&chan->dev->device);
  827. free_percpu(chan->local);
  828. }
  829. }
  830. EXPORT_SYMBOL(dma_async_device_unregister);
  831. struct dmaengine_unmap_pool {
  832. struct kmem_cache *cache;
  833. const char *name;
  834. mempool_t *pool;
  835. size_t size;
  836. };
  837. #define __UNMAP_POOL(x) { .size = x, .name = "dmaengine-unmap-" __stringify(x) }
  838. static struct dmaengine_unmap_pool unmap_pool[] = {
  839. __UNMAP_POOL(2),
  840. #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
  841. __UNMAP_POOL(16),
  842. __UNMAP_POOL(128),
  843. __UNMAP_POOL(256),
  844. #endif
  845. };
  846. static struct dmaengine_unmap_pool *__get_unmap_pool(int nr)
  847. {
  848. int order = get_count_order(nr);
  849. switch (order) {
  850. case 0 ... 1:
  851. return &unmap_pool[0];
  852. case 2 ... 4:
  853. return &unmap_pool[1];
  854. case 5 ... 7:
  855. return &unmap_pool[2];
  856. case 8:
  857. return &unmap_pool[3];
  858. default:
  859. BUG();
  860. return NULL;
  861. }
  862. }
  863. static void dmaengine_unmap(struct kref *kref)
  864. {
  865. struct dmaengine_unmap_data *unmap = container_of(kref, typeof(*unmap), kref);
  866. struct device *dev = unmap->dev;
  867. int cnt, i;
  868. cnt = unmap->to_cnt;
  869. for (i = 0; i < cnt; i++)
  870. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  871. DMA_TO_DEVICE);
  872. cnt += unmap->from_cnt;
  873. for (; i < cnt; i++)
  874. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  875. DMA_FROM_DEVICE);
  876. cnt += unmap->bidi_cnt;
  877. for (; i < cnt; i++) {
  878. if (unmap->addr[i] == 0)
  879. continue;
  880. dma_unmap_page(dev, unmap->addr[i], unmap->len,
  881. DMA_BIDIRECTIONAL);
  882. }
  883. cnt = unmap->map_cnt;
  884. mempool_free(unmap, __get_unmap_pool(cnt)->pool);
  885. }
  886. void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
  887. {
  888. if (unmap)
  889. kref_put(&unmap->kref, dmaengine_unmap);
  890. }
  891. EXPORT_SYMBOL_GPL(dmaengine_unmap_put);
  892. static void dmaengine_destroy_unmap_pool(void)
  893. {
  894. int i;
  895. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  896. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  897. if (p->pool)
  898. mempool_destroy(p->pool);
  899. p->pool = NULL;
  900. if (p->cache)
  901. kmem_cache_destroy(p->cache);
  902. p->cache = NULL;
  903. }
  904. }
  905. static int __init dmaengine_init_unmap_pool(void)
  906. {
  907. int i;
  908. for (i = 0; i < ARRAY_SIZE(unmap_pool); i++) {
  909. struct dmaengine_unmap_pool *p = &unmap_pool[i];
  910. size_t size;
  911. size = sizeof(struct dmaengine_unmap_data) +
  912. sizeof(dma_addr_t) * p->size;
  913. p->cache = kmem_cache_create(p->name, size, 0,
  914. SLAB_HWCACHE_ALIGN, NULL);
  915. if (!p->cache)
  916. break;
  917. p->pool = mempool_create_slab_pool(1, p->cache);
  918. if (!p->pool)
  919. break;
  920. }
  921. if (i == ARRAY_SIZE(unmap_pool))
  922. return 0;
  923. dmaengine_destroy_unmap_pool();
  924. return -ENOMEM;
  925. }
  926. struct dmaengine_unmap_data *
  927. dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
  928. {
  929. struct dmaengine_unmap_data *unmap;
  930. unmap = mempool_alloc(__get_unmap_pool(nr)->pool, flags);
  931. if (!unmap)
  932. return NULL;
  933. memset(unmap, 0, sizeof(*unmap));
  934. kref_init(&unmap->kref);
  935. unmap->dev = dev;
  936. unmap->map_cnt = nr;
  937. return unmap;
  938. }
  939. EXPORT_SYMBOL(dmaengine_get_unmap_data);
  940. void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
  941. struct dma_chan *chan)
  942. {
  943. tx->chan = chan;
  944. #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
  945. spin_lock_init(&tx->lock);
  946. #endif
  947. }
  948. EXPORT_SYMBOL(dma_async_tx_descriptor_init);
  949. /* dma_wait_for_async_tx - spin wait for a transaction to complete
  950. * @tx: in-flight transaction to wait on
  951. */
  952. enum dma_status
  953. dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
  954. {
  955. unsigned long dma_sync_wait_timeout = jiffies + msecs_to_jiffies(5000);
  956. if (!tx)
  957. return DMA_COMPLETE;
  958. while (tx->cookie == -EBUSY) {
  959. if (time_after_eq(jiffies, dma_sync_wait_timeout)) {
  960. pr_err("%s timeout waiting for descriptor submission\n",
  961. __func__);
  962. return DMA_ERROR;
  963. }
  964. cpu_relax();
  965. }
  966. return dma_sync_wait(tx->chan, tx->cookie);
  967. }
  968. EXPORT_SYMBOL_GPL(dma_wait_for_async_tx);
  969. /* dma_run_dependencies - helper routine for dma drivers to process
  970. * (start) dependent operations on their target channel
  971. * @tx: transaction with dependencies
  972. */
  973. void dma_run_dependencies(struct dma_async_tx_descriptor *tx)
  974. {
  975. struct dma_async_tx_descriptor *dep = txd_next(tx);
  976. struct dma_async_tx_descriptor *dep_next;
  977. struct dma_chan *chan;
  978. if (!dep)
  979. return;
  980. /* we'll submit tx->next now, so clear the link */
  981. txd_clear_next(tx);
  982. chan = dep->chan;
  983. /* keep submitting up until a channel switch is detected
  984. * in that case we will be called again as a result of
  985. * processing the interrupt from async_tx_channel_switch
  986. */
  987. for (; dep; dep = dep_next) {
  988. txd_lock(dep);
  989. txd_clear_parent(dep);
  990. dep_next = txd_next(dep);
  991. if (dep_next && dep_next->chan == chan)
  992. txd_clear_next(dep); /* ->next will be submitted */
  993. else
  994. dep_next = NULL; /* submit current dep and terminate */
  995. txd_unlock(dep);
  996. dep->tx_submit(dep);
  997. }
  998. chan->device->device_issue_pending(chan);
  999. }
  1000. EXPORT_SYMBOL_GPL(dma_run_dependencies);
  1001. static int __init dma_bus_init(void)
  1002. {
  1003. int err = dmaengine_init_unmap_pool();
  1004. if (err)
  1005. return err;
  1006. return class_register(&dma_devclass);
  1007. }
  1008. arch_initcall(dma_bus_init);