ccp-dev.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656
  1. /*
  2. * AMD Cryptographic Coprocessor (CCP) driver
  3. *
  4. * Copyright (C) 2013 Advanced Micro Devices, Inc.
  5. *
  6. * Author: Tom Lendacky <thomas.lendacky@amd.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/kthread.h>
  15. #include <linux/sched.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/mutex.h>
  19. #include <linux/delay.h>
  20. #include <linux/hw_random.h>
  21. #include <linux/cpu.h>
  22. #ifdef CONFIG_X86
  23. #include <asm/cpu_device_id.h>
  24. #endif
  25. #include <linux/ccp.h>
  26. #include "ccp-dev.h"
  27. MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
  28. MODULE_LICENSE("GPL");
  29. MODULE_VERSION("1.0.0");
  30. MODULE_DESCRIPTION("AMD Cryptographic Coprocessor driver");
  31. struct ccp_tasklet_data {
  32. struct completion completion;
  33. struct ccp_cmd *cmd;
  34. };
  35. static struct ccp_device *ccp_dev;
  36. static inline struct ccp_device *ccp_get_device(void)
  37. {
  38. return ccp_dev;
  39. }
  40. static inline void ccp_add_device(struct ccp_device *ccp)
  41. {
  42. ccp_dev = ccp;
  43. }
  44. static inline void ccp_del_device(struct ccp_device *ccp)
  45. {
  46. ccp_dev = NULL;
  47. }
  48. /**
  49. * ccp_present - check if a CCP device is present
  50. *
  51. * Returns zero if a CCP device is present, -ENODEV otherwise.
  52. */
  53. int ccp_present(void)
  54. {
  55. if (ccp_get_device())
  56. return 0;
  57. return -ENODEV;
  58. }
  59. EXPORT_SYMBOL_GPL(ccp_present);
  60. /**
  61. * ccp_enqueue_cmd - queue an operation for processing by the CCP
  62. *
  63. * @cmd: ccp_cmd struct to be processed
  64. *
  65. * Queue a cmd to be processed by the CCP. If queueing the cmd
  66. * would exceed the defined length of the cmd queue the cmd will
  67. * only be queued if the CCP_CMD_MAY_BACKLOG flag is set and will
  68. * result in a return code of -EBUSY.
  69. *
  70. * The callback routine specified in the ccp_cmd struct will be
  71. * called to notify the caller of completion (if the cmd was not
  72. * backlogged) or advancement out of the backlog. If the cmd has
  73. * advanced out of the backlog the "err" value of the callback
  74. * will be -EINPROGRESS. Any other "err" value during callback is
  75. * the result of the operation.
  76. *
  77. * The cmd has been successfully queued if:
  78. * the return code is -EINPROGRESS or
  79. * the return code is -EBUSY and CCP_CMD_MAY_BACKLOG flag is set
  80. */
  81. int ccp_enqueue_cmd(struct ccp_cmd *cmd)
  82. {
  83. struct ccp_device *ccp = ccp_get_device();
  84. unsigned long flags;
  85. unsigned int i;
  86. int ret;
  87. if (!ccp)
  88. return -ENODEV;
  89. /* Caller must supply a callback routine */
  90. if (!cmd->callback)
  91. return -EINVAL;
  92. cmd->ccp = ccp;
  93. spin_lock_irqsave(&ccp->cmd_lock, flags);
  94. i = ccp->cmd_q_count;
  95. if (ccp->cmd_count >= MAX_CMD_QLEN) {
  96. ret = -EBUSY;
  97. if (cmd->flags & CCP_CMD_MAY_BACKLOG)
  98. list_add_tail(&cmd->entry, &ccp->backlog);
  99. } else {
  100. ret = -EINPROGRESS;
  101. ccp->cmd_count++;
  102. list_add_tail(&cmd->entry, &ccp->cmd);
  103. /* Find an idle queue */
  104. if (!ccp->suspending) {
  105. for (i = 0; i < ccp->cmd_q_count; i++) {
  106. if (ccp->cmd_q[i].active)
  107. continue;
  108. break;
  109. }
  110. }
  111. }
  112. spin_unlock_irqrestore(&ccp->cmd_lock, flags);
  113. /* If we found an idle queue, wake it up */
  114. if (i < ccp->cmd_q_count)
  115. wake_up_process(ccp->cmd_q[i].kthread);
  116. return ret;
  117. }
  118. EXPORT_SYMBOL_GPL(ccp_enqueue_cmd);
  119. static void ccp_do_cmd_backlog(struct work_struct *work)
  120. {
  121. struct ccp_cmd *cmd = container_of(work, struct ccp_cmd, work);
  122. struct ccp_device *ccp = cmd->ccp;
  123. unsigned long flags;
  124. unsigned int i;
  125. cmd->callback(cmd->data, -EINPROGRESS);
  126. spin_lock_irqsave(&ccp->cmd_lock, flags);
  127. ccp->cmd_count++;
  128. list_add_tail(&cmd->entry, &ccp->cmd);
  129. /* Find an idle queue */
  130. for (i = 0; i < ccp->cmd_q_count; i++) {
  131. if (ccp->cmd_q[i].active)
  132. continue;
  133. break;
  134. }
  135. spin_unlock_irqrestore(&ccp->cmd_lock, flags);
  136. /* If we found an idle queue, wake it up */
  137. if (i < ccp->cmd_q_count)
  138. wake_up_process(ccp->cmd_q[i].kthread);
  139. }
  140. static struct ccp_cmd *ccp_dequeue_cmd(struct ccp_cmd_queue *cmd_q)
  141. {
  142. struct ccp_device *ccp = cmd_q->ccp;
  143. struct ccp_cmd *cmd = NULL;
  144. struct ccp_cmd *backlog = NULL;
  145. unsigned long flags;
  146. spin_lock_irqsave(&ccp->cmd_lock, flags);
  147. cmd_q->active = 0;
  148. if (ccp->suspending) {
  149. cmd_q->suspended = 1;
  150. spin_unlock_irqrestore(&ccp->cmd_lock, flags);
  151. wake_up_interruptible(&ccp->suspend_queue);
  152. return NULL;
  153. }
  154. if (ccp->cmd_count) {
  155. cmd_q->active = 1;
  156. cmd = list_first_entry(&ccp->cmd, struct ccp_cmd, entry);
  157. list_del(&cmd->entry);
  158. ccp->cmd_count--;
  159. }
  160. if (!list_empty(&ccp->backlog)) {
  161. backlog = list_first_entry(&ccp->backlog, struct ccp_cmd,
  162. entry);
  163. list_del(&backlog->entry);
  164. }
  165. spin_unlock_irqrestore(&ccp->cmd_lock, flags);
  166. if (backlog) {
  167. INIT_WORK(&backlog->work, ccp_do_cmd_backlog);
  168. schedule_work(&backlog->work);
  169. }
  170. return cmd;
  171. }
  172. static void ccp_do_cmd_complete(unsigned long data)
  173. {
  174. struct ccp_tasklet_data *tdata = (struct ccp_tasklet_data *)data;
  175. struct ccp_cmd *cmd = tdata->cmd;
  176. cmd->callback(cmd->data, cmd->ret);
  177. complete(&tdata->completion);
  178. }
  179. static int ccp_cmd_queue_thread(void *data)
  180. {
  181. struct ccp_cmd_queue *cmd_q = (struct ccp_cmd_queue *)data;
  182. struct ccp_cmd *cmd;
  183. struct ccp_tasklet_data tdata;
  184. struct tasklet_struct tasklet;
  185. tasklet_init(&tasklet, ccp_do_cmd_complete, (unsigned long)&tdata);
  186. set_current_state(TASK_INTERRUPTIBLE);
  187. while (!kthread_should_stop()) {
  188. schedule();
  189. set_current_state(TASK_INTERRUPTIBLE);
  190. cmd = ccp_dequeue_cmd(cmd_q);
  191. if (!cmd)
  192. continue;
  193. __set_current_state(TASK_RUNNING);
  194. /* Execute the command */
  195. cmd->ret = ccp_run_cmd(cmd_q, cmd);
  196. /* Schedule the completion callback */
  197. tdata.cmd = cmd;
  198. init_completion(&tdata.completion);
  199. tasklet_schedule(&tasklet);
  200. wait_for_completion(&tdata.completion);
  201. }
  202. __set_current_state(TASK_RUNNING);
  203. return 0;
  204. }
  205. static int ccp_trng_read(struct hwrng *rng, void *data, size_t max, bool wait)
  206. {
  207. struct ccp_device *ccp = container_of(rng, struct ccp_device, hwrng);
  208. u32 trng_value;
  209. int len = min_t(int, sizeof(trng_value), max);
  210. /*
  211. * Locking is provided by the caller so we can update device
  212. * hwrng-related fields safely
  213. */
  214. trng_value = ioread32(ccp->io_regs + TRNG_OUT_REG);
  215. if (!trng_value) {
  216. /* Zero is returned if not data is available or if a
  217. * bad-entropy error is present. Assume an error if
  218. * we exceed TRNG_RETRIES reads of zero.
  219. */
  220. if (ccp->hwrng_retries++ > TRNG_RETRIES)
  221. return -EIO;
  222. return 0;
  223. }
  224. /* Reset the counter and save the rng value */
  225. ccp->hwrng_retries = 0;
  226. memcpy(data, &trng_value, len);
  227. return len;
  228. }
  229. /**
  230. * ccp_alloc_struct - allocate and initialize the ccp_device struct
  231. *
  232. * @dev: device struct of the CCP
  233. */
  234. struct ccp_device *ccp_alloc_struct(struct device *dev)
  235. {
  236. struct ccp_device *ccp;
  237. ccp = kzalloc(sizeof(*ccp), GFP_KERNEL);
  238. if (ccp == NULL) {
  239. dev_err(dev, "unable to allocate device struct\n");
  240. return NULL;
  241. }
  242. ccp->dev = dev;
  243. INIT_LIST_HEAD(&ccp->cmd);
  244. INIT_LIST_HEAD(&ccp->backlog);
  245. spin_lock_init(&ccp->cmd_lock);
  246. mutex_init(&ccp->req_mutex);
  247. mutex_init(&ccp->ksb_mutex);
  248. ccp->ksb_count = KSB_COUNT;
  249. ccp->ksb_start = 0;
  250. return ccp;
  251. }
  252. /**
  253. * ccp_init - initialize the CCP device
  254. *
  255. * @ccp: ccp_device struct
  256. */
  257. int ccp_init(struct ccp_device *ccp)
  258. {
  259. struct device *dev = ccp->dev;
  260. struct ccp_cmd_queue *cmd_q;
  261. struct dma_pool *dma_pool;
  262. char dma_pool_name[MAX_DMAPOOL_NAME_LEN];
  263. unsigned int qmr, qim, i;
  264. int ret;
  265. /* Find available queues */
  266. qim = 0;
  267. qmr = ioread32(ccp->io_regs + Q_MASK_REG);
  268. for (i = 0; i < MAX_HW_QUEUES; i++) {
  269. if (!(qmr & (1 << i)))
  270. continue;
  271. /* Allocate a dma pool for this queue */
  272. snprintf(dma_pool_name, sizeof(dma_pool_name), "ccp_q%d", i);
  273. dma_pool = dma_pool_create(dma_pool_name, dev,
  274. CCP_DMAPOOL_MAX_SIZE,
  275. CCP_DMAPOOL_ALIGN, 0);
  276. if (!dma_pool) {
  277. dev_err(dev, "unable to allocate dma pool\n");
  278. ret = -ENOMEM;
  279. goto e_pool;
  280. }
  281. cmd_q = &ccp->cmd_q[ccp->cmd_q_count];
  282. ccp->cmd_q_count++;
  283. cmd_q->ccp = ccp;
  284. cmd_q->id = i;
  285. cmd_q->dma_pool = dma_pool;
  286. /* Reserve 2 KSB regions for the queue */
  287. cmd_q->ksb_key = KSB_START + ccp->ksb_start++;
  288. cmd_q->ksb_ctx = KSB_START + ccp->ksb_start++;
  289. ccp->ksb_count -= 2;
  290. /* Preset some register values and masks that are queue
  291. * number dependent
  292. */
  293. cmd_q->reg_status = ccp->io_regs + CMD_Q_STATUS_BASE +
  294. (CMD_Q_STATUS_INCR * i);
  295. cmd_q->reg_int_status = ccp->io_regs + CMD_Q_INT_STATUS_BASE +
  296. (CMD_Q_STATUS_INCR * i);
  297. cmd_q->int_ok = 1 << (i * 2);
  298. cmd_q->int_err = 1 << ((i * 2) + 1);
  299. cmd_q->free_slots = CMD_Q_DEPTH(ioread32(cmd_q->reg_status));
  300. init_waitqueue_head(&cmd_q->int_queue);
  301. /* Build queue interrupt mask (two interrupts per queue) */
  302. qim |= cmd_q->int_ok | cmd_q->int_err;
  303. #ifdef CONFIG_ARM64
  304. /* For arm64 set the recommended queue cache settings */
  305. iowrite32(ccp->axcache, ccp->io_regs + CMD_Q_CACHE_BASE +
  306. (CMD_Q_CACHE_INC * i));
  307. #endif
  308. dev_dbg(dev, "queue #%u available\n", i);
  309. }
  310. if (ccp->cmd_q_count == 0) {
  311. dev_notice(dev, "no command queues available\n");
  312. ret = -EIO;
  313. goto e_pool;
  314. }
  315. dev_notice(dev, "%u command queues available\n", ccp->cmd_q_count);
  316. /* Disable and clear interrupts until ready */
  317. iowrite32(0x00, ccp->io_regs + IRQ_MASK_REG);
  318. for (i = 0; i < ccp->cmd_q_count; i++) {
  319. cmd_q = &ccp->cmd_q[i];
  320. ioread32(cmd_q->reg_int_status);
  321. ioread32(cmd_q->reg_status);
  322. }
  323. iowrite32(qim, ccp->io_regs + IRQ_STATUS_REG);
  324. /* Request an irq */
  325. ret = ccp->get_irq(ccp);
  326. if (ret) {
  327. dev_err(dev, "unable to allocate an IRQ\n");
  328. goto e_pool;
  329. }
  330. /* Initialize the queues used to wait for KSB space and suspend */
  331. init_waitqueue_head(&ccp->ksb_queue);
  332. init_waitqueue_head(&ccp->suspend_queue);
  333. /* Create a kthread for each queue */
  334. for (i = 0; i < ccp->cmd_q_count; i++) {
  335. struct task_struct *kthread;
  336. cmd_q = &ccp->cmd_q[i];
  337. kthread = kthread_create(ccp_cmd_queue_thread, cmd_q,
  338. "ccp-q%u", cmd_q->id);
  339. if (IS_ERR(kthread)) {
  340. dev_err(dev, "error creating queue thread (%ld)\n",
  341. PTR_ERR(kthread));
  342. ret = PTR_ERR(kthread);
  343. goto e_kthread;
  344. }
  345. cmd_q->kthread = kthread;
  346. wake_up_process(kthread);
  347. }
  348. /* Register the RNG */
  349. ccp->hwrng.name = "ccp-rng";
  350. ccp->hwrng.read = ccp_trng_read;
  351. ret = hwrng_register(&ccp->hwrng);
  352. if (ret) {
  353. dev_err(dev, "error registering hwrng (%d)\n", ret);
  354. goto e_kthread;
  355. }
  356. /* Make the device struct available before enabling interrupts */
  357. ccp_add_device(ccp);
  358. /* Enable interrupts */
  359. iowrite32(qim, ccp->io_regs + IRQ_MASK_REG);
  360. return 0;
  361. e_kthread:
  362. for (i = 0; i < ccp->cmd_q_count; i++)
  363. if (ccp->cmd_q[i].kthread)
  364. kthread_stop(ccp->cmd_q[i].kthread);
  365. ccp->free_irq(ccp);
  366. e_pool:
  367. for (i = 0; i < ccp->cmd_q_count; i++)
  368. dma_pool_destroy(ccp->cmd_q[i].dma_pool);
  369. return ret;
  370. }
  371. /**
  372. * ccp_destroy - tear down the CCP device
  373. *
  374. * @ccp: ccp_device struct
  375. */
  376. void ccp_destroy(struct ccp_device *ccp)
  377. {
  378. struct ccp_cmd_queue *cmd_q;
  379. struct ccp_cmd *cmd;
  380. unsigned int qim, i;
  381. /* Remove general access to the device struct */
  382. ccp_del_device(ccp);
  383. /* Unregister the RNG */
  384. hwrng_unregister(&ccp->hwrng);
  385. /* Stop the queue kthreads */
  386. for (i = 0; i < ccp->cmd_q_count; i++)
  387. if (ccp->cmd_q[i].kthread)
  388. kthread_stop(ccp->cmd_q[i].kthread);
  389. /* Build queue interrupt mask (two interrupt masks per queue) */
  390. qim = 0;
  391. for (i = 0; i < ccp->cmd_q_count; i++) {
  392. cmd_q = &ccp->cmd_q[i];
  393. qim |= cmd_q->int_ok | cmd_q->int_err;
  394. }
  395. /* Disable and clear interrupts */
  396. iowrite32(0x00, ccp->io_regs + IRQ_MASK_REG);
  397. for (i = 0; i < ccp->cmd_q_count; i++) {
  398. cmd_q = &ccp->cmd_q[i];
  399. ioread32(cmd_q->reg_int_status);
  400. ioread32(cmd_q->reg_status);
  401. }
  402. iowrite32(qim, ccp->io_regs + IRQ_STATUS_REG);
  403. ccp->free_irq(ccp);
  404. for (i = 0; i < ccp->cmd_q_count; i++)
  405. dma_pool_destroy(ccp->cmd_q[i].dma_pool);
  406. /* Flush the cmd and backlog queue */
  407. while (!list_empty(&ccp->cmd)) {
  408. /* Invoke the callback directly with an error code */
  409. cmd = list_first_entry(&ccp->cmd, struct ccp_cmd, entry);
  410. list_del(&cmd->entry);
  411. cmd->callback(cmd->data, -ENODEV);
  412. }
  413. while (!list_empty(&ccp->backlog)) {
  414. /* Invoke the callback directly with an error code */
  415. cmd = list_first_entry(&ccp->backlog, struct ccp_cmd, entry);
  416. list_del(&cmd->entry);
  417. cmd->callback(cmd->data, -ENODEV);
  418. }
  419. }
  420. /**
  421. * ccp_irq_handler - handle interrupts generated by the CCP device
  422. *
  423. * @irq: the irq associated with the interrupt
  424. * @data: the data value supplied when the irq was created
  425. */
  426. irqreturn_t ccp_irq_handler(int irq, void *data)
  427. {
  428. struct device *dev = data;
  429. struct ccp_device *ccp = dev_get_drvdata(dev);
  430. struct ccp_cmd_queue *cmd_q;
  431. u32 q_int, status;
  432. unsigned int i;
  433. status = ioread32(ccp->io_regs + IRQ_STATUS_REG);
  434. for (i = 0; i < ccp->cmd_q_count; i++) {
  435. cmd_q = &ccp->cmd_q[i];
  436. q_int = status & (cmd_q->int_ok | cmd_q->int_err);
  437. if (q_int) {
  438. cmd_q->int_status = status;
  439. cmd_q->q_status = ioread32(cmd_q->reg_status);
  440. cmd_q->q_int_status = ioread32(cmd_q->reg_int_status);
  441. /* On error, only save the first error value */
  442. if ((q_int & cmd_q->int_err) && !cmd_q->cmd_error)
  443. cmd_q->cmd_error = CMD_Q_ERROR(cmd_q->q_status);
  444. cmd_q->int_rcvd = 1;
  445. /* Acknowledge the interrupt and wake the kthread */
  446. iowrite32(q_int, ccp->io_regs + IRQ_STATUS_REG);
  447. wake_up_interruptible(&cmd_q->int_queue);
  448. }
  449. }
  450. return IRQ_HANDLED;
  451. }
  452. #ifdef CONFIG_PM
  453. bool ccp_queues_suspended(struct ccp_device *ccp)
  454. {
  455. unsigned int suspended = 0;
  456. unsigned long flags;
  457. unsigned int i;
  458. spin_lock_irqsave(&ccp->cmd_lock, flags);
  459. for (i = 0; i < ccp->cmd_q_count; i++)
  460. if (ccp->cmd_q[i].suspended)
  461. suspended++;
  462. spin_unlock_irqrestore(&ccp->cmd_lock, flags);
  463. return ccp->cmd_q_count == suspended;
  464. }
  465. #endif
  466. #ifdef CONFIG_X86
  467. static const struct x86_cpu_id ccp_support[] = {
  468. { X86_VENDOR_AMD, 22, },
  469. };
  470. #endif
  471. static int __init ccp_mod_init(void)
  472. {
  473. #ifdef CONFIG_X86
  474. struct cpuinfo_x86 *cpuinfo = &boot_cpu_data;
  475. int ret;
  476. if (!x86_match_cpu(ccp_support))
  477. return -ENODEV;
  478. switch (cpuinfo->x86) {
  479. case 22:
  480. if ((cpuinfo->x86_model < 48) || (cpuinfo->x86_model > 63))
  481. return -ENODEV;
  482. ret = ccp_pci_init();
  483. if (ret)
  484. return ret;
  485. /* Don't leave the driver loaded if init failed */
  486. if (!ccp_get_device()) {
  487. ccp_pci_exit();
  488. return -ENODEV;
  489. }
  490. return 0;
  491. break;
  492. }
  493. #endif
  494. #ifdef CONFIG_ARM64
  495. int ret;
  496. ret = ccp_platform_init();
  497. if (ret)
  498. return ret;
  499. /* Don't leave the driver loaded if init failed */
  500. if (!ccp_get_device()) {
  501. ccp_platform_exit();
  502. return -ENODEV;
  503. }
  504. return 0;
  505. #endif
  506. return -ENODEV;
  507. }
  508. static void __exit ccp_mod_exit(void)
  509. {
  510. #ifdef CONFIG_X86
  511. struct cpuinfo_x86 *cpuinfo = &boot_cpu_data;
  512. switch (cpuinfo->x86) {
  513. case 22:
  514. ccp_pci_exit();
  515. break;
  516. }
  517. #endif
  518. #ifdef CONFIG_ARM64
  519. ccp_platform_exit();
  520. #endif
  521. }
  522. module_init(ccp_mod_init);
  523. module_exit(ccp_mod_exit);