hdmi5.c 18 KB

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  1. /*
  2. * HDMI driver for OMAP5
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. *
  6. * Authors:
  7. * Yong Zhi
  8. * Mythri pk
  9. * Archit Taneja <archit@ti.com>
  10. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License version 2 as published by
  14. * the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program. If not, see <http://www.gnu.org/licenses/>.
  23. */
  24. #define DSS_SUBSYS_NAME "HDMI"
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/err.h>
  28. #include <linux/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/string.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/clk.h>
  36. #include <linux/gpio.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/component.h>
  39. #include <linux/of.h>
  40. #include <linux/of_graph.h>
  41. #include <sound/omap-hdmi-audio.h>
  42. #include "omapdss.h"
  43. #include "hdmi5_core.h"
  44. #include "dss.h"
  45. #include "dss_features.h"
  46. static struct omap_hdmi hdmi;
  47. static int hdmi_runtime_get(void)
  48. {
  49. int r;
  50. DSSDBG("hdmi_runtime_get\n");
  51. r = pm_runtime_get_sync(&hdmi.pdev->dev);
  52. WARN_ON(r < 0);
  53. if (r < 0)
  54. return r;
  55. return 0;
  56. }
  57. static void hdmi_runtime_put(void)
  58. {
  59. int r;
  60. DSSDBG("hdmi_runtime_put\n");
  61. r = pm_runtime_put_sync(&hdmi.pdev->dev);
  62. WARN_ON(r < 0 && r != -ENOSYS);
  63. }
  64. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  65. {
  66. struct hdmi_wp_data *wp = data;
  67. u32 irqstatus;
  68. irqstatus = hdmi_wp_get_irqstatus(wp);
  69. hdmi_wp_set_irqstatus(wp, irqstatus);
  70. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  71. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  72. u32 v;
  73. /*
  74. * If we get both connect and disconnect interrupts at the same
  75. * time, turn off the PHY, clear interrupts, and restart, which
  76. * raises connect interrupt if a cable is connected, or nothing
  77. * if cable is not connected.
  78. */
  79. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  80. /*
  81. * We always get bogus CONNECT & DISCONNECT interrupts when
  82. * setting the PHY to LDOON. To ignore those, we force the RXDET
  83. * line to 0 until the PHY power state has been changed.
  84. */
  85. v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  86. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  87. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  88. hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  89. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  90. HDMI_IRQ_LINK_DISCONNECT);
  91. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  92. REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  93. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  94. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  95. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  96. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  97. }
  98. return IRQ_HANDLED;
  99. }
  100. static int hdmi_init_regulator(void)
  101. {
  102. struct regulator *reg;
  103. if (hdmi.vdda_reg != NULL)
  104. return 0;
  105. reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
  106. if (IS_ERR(reg)) {
  107. DSSERR("can't get VDDA regulator\n");
  108. return PTR_ERR(reg);
  109. }
  110. hdmi.vdda_reg = reg;
  111. return 0;
  112. }
  113. static int hdmi_power_on_core(struct omap_dss_device *dssdev)
  114. {
  115. int r;
  116. r = regulator_enable(hdmi.vdda_reg);
  117. if (r)
  118. return r;
  119. r = hdmi_runtime_get();
  120. if (r)
  121. goto err_runtime_get;
  122. /* Make selection of HDMI in DSS */
  123. dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
  124. hdmi.core_enabled = true;
  125. return 0;
  126. err_runtime_get:
  127. regulator_disable(hdmi.vdda_reg);
  128. return r;
  129. }
  130. static void hdmi_power_off_core(struct omap_dss_device *dssdev)
  131. {
  132. hdmi.core_enabled = false;
  133. hdmi_runtime_put();
  134. regulator_disable(hdmi.vdda_reg);
  135. }
  136. static int hdmi_power_on_full(struct omap_dss_device *dssdev)
  137. {
  138. int r;
  139. struct videomode *vm;
  140. enum omap_channel channel = dssdev->dispc_channel;
  141. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  142. unsigned pc;
  143. r = hdmi_power_on_core(dssdev);
  144. if (r)
  145. return r;
  146. vm = &hdmi.cfg.vm;
  147. DSSDBG("hdmi_power_on hactive= %d vactive = %d\n", vm->hactive,
  148. vm->vactive);
  149. pc = vm->pixelclock;
  150. if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
  151. pc *= 2;
  152. /* DSS_HDMI_TCLK is bitclk / 10 */
  153. pc *= 10;
  154. dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin),
  155. pc, &hdmi_cinfo);
  156. /* disable and clear irqs */
  157. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  158. hdmi_wp_set_irqstatus(&hdmi.wp,
  159. hdmi_wp_get_irqstatus(&hdmi.wp));
  160. r = dss_pll_enable(&hdmi.pll.pll);
  161. if (r) {
  162. DSSERR("Failed to enable PLL\n");
  163. goto err_pll_enable;
  164. }
  165. r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
  166. if (r) {
  167. DSSERR("Failed to configure PLL\n");
  168. goto err_pll_cfg;
  169. }
  170. r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
  171. hdmi_cinfo.clkout[0]);
  172. if (r) {
  173. DSSDBG("Failed to start PHY\n");
  174. goto err_phy_cfg;
  175. }
  176. r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
  177. if (r)
  178. goto err_phy_pwr;
  179. hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
  180. /* tv size */
  181. dss_mgr_set_timings(channel, vm);
  182. r = dss_mgr_enable(channel);
  183. if (r)
  184. goto err_mgr_enable;
  185. r = hdmi_wp_video_start(&hdmi.wp);
  186. if (r)
  187. goto err_vid_enable;
  188. hdmi_wp_set_irqenable(&hdmi.wp,
  189. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  190. return 0;
  191. err_vid_enable:
  192. dss_mgr_disable(channel);
  193. err_mgr_enable:
  194. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  195. err_phy_pwr:
  196. err_phy_cfg:
  197. err_pll_cfg:
  198. dss_pll_disable(&hdmi.pll.pll);
  199. err_pll_enable:
  200. hdmi_power_off_core(dssdev);
  201. return -EIO;
  202. }
  203. static void hdmi_power_off_full(struct omap_dss_device *dssdev)
  204. {
  205. enum omap_channel channel = dssdev->dispc_channel;
  206. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  207. hdmi_wp_video_stop(&hdmi.wp);
  208. dss_mgr_disable(channel);
  209. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  210. dss_pll_disable(&hdmi.pll.pll);
  211. hdmi_power_off_core(dssdev);
  212. }
  213. static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
  214. struct videomode *vm)
  215. {
  216. if (!dispc_mgr_timings_ok(dssdev->dispc_channel, vm))
  217. return -EINVAL;
  218. return 0;
  219. }
  220. static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
  221. struct videomode *vm)
  222. {
  223. mutex_lock(&hdmi.lock);
  224. hdmi.cfg.vm = *vm;
  225. dispc_set_tv_pclk(vm->pixelclock);
  226. mutex_unlock(&hdmi.lock);
  227. }
  228. static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
  229. struct videomode *vm)
  230. {
  231. *vm = hdmi.cfg.vm;
  232. }
  233. static void hdmi_dump_regs(struct seq_file *s)
  234. {
  235. mutex_lock(&hdmi.lock);
  236. if (hdmi_runtime_get()) {
  237. mutex_unlock(&hdmi.lock);
  238. return;
  239. }
  240. hdmi_wp_dump(&hdmi.wp, s);
  241. hdmi_pll_dump(&hdmi.pll, s);
  242. hdmi_phy_dump(&hdmi.phy, s);
  243. hdmi5_core_dump(&hdmi.core, s);
  244. hdmi_runtime_put();
  245. mutex_unlock(&hdmi.lock);
  246. }
  247. static int read_edid(u8 *buf, int len)
  248. {
  249. int r;
  250. int idlemode;
  251. mutex_lock(&hdmi.lock);
  252. r = hdmi_runtime_get();
  253. BUG_ON(r);
  254. idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  255. /* No-idle mode */
  256. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  257. r = hdmi5_read_edid(&hdmi.core, buf, len);
  258. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  259. hdmi_runtime_put();
  260. mutex_unlock(&hdmi.lock);
  261. return r;
  262. }
  263. static void hdmi_start_audio_stream(struct omap_hdmi *hd)
  264. {
  265. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  266. hdmi_wp_audio_enable(&hd->wp, true);
  267. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  268. }
  269. static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
  270. {
  271. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  272. hdmi_wp_audio_enable(&hd->wp, false);
  273. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  274. }
  275. static int hdmi_display_enable(struct omap_dss_device *dssdev)
  276. {
  277. struct omap_dss_device *out = &hdmi.output;
  278. unsigned long flags;
  279. int r = 0;
  280. DSSDBG("ENTER hdmi_display_enable\n");
  281. mutex_lock(&hdmi.lock);
  282. if (!out->dispc_channel_connected) {
  283. DSSERR("failed to enable display: no output/manager\n");
  284. r = -ENODEV;
  285. goto err0;
  286. }
  287. r = hdmi_power_on_full(dssdev);
  288. if (r) {
  289. DSSERR("failed to power on device\n");
  290. goto err0;
  291. }
  292. if (hdmi.audio_configured) {
  293. r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
  294. hdmi.cfg.vm.pixelclock);
  295. if (r) {
  296. DSSERR("Error restoring audio configuration: %d", r);
  297. hdmi.audio_abort_cb(&hdmi.pdev->dev);
  298. hdmi.audio_configured = false;
  299. }
  300. }
  301. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  302. if (hdmi.audio_configured && hdmi.audio_playing)
  303. hdmi_start_audio_stream(&hdmi);
  304. hdmi.display_enabled = true;
  305. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  306. mutex_unlock(&hdmi.lock);
  307. return 0;
  308. err0:
  309. mutex_unlock(&hdmi.lock);
  310. return r;
  311. }
  312. static void hdmi_display_disable(struct omap_dss_device *dssdev)
  313. {
  314. unsigned long flags;
  315. DSSDBG("Enter hdmi_display_disable\n");
  316. mutex_lock(&hdmi.lock);
  317. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  318. hdmi_stop_audio_stream(&hdmi);
  319. hdmi.display_enabled = false;
  320. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  321. hdmi_power_off_full(dssdev);
  322. mutex_unlock(&hdmi.lock);
  323. }
  324. static int hdmi_core_enable(struct omap_dss_device *dssdev)
  325. {
  326. int r = 0;
  327. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  328. mutex_lock(&hdmi.lock);
  329. r = hdmi_power_on_core(dssdev);
  330. if (r) {
  331. DSSERR("failed to power on device\n");
  332. goto err0;
  333. }
  334. mutex_unlock(&hdmi.lock);
  335. return 0;
  336. err0:
  337. mutex_unlock(&hdmi.lock);
  338. return r;
  339. }
  340. static void hdmi_core_disable(struct omap_dss_device *dssdev)
  341. {
  342. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  343. mutex_lock(&hdmi.lock);
  344. hdmi_power_off_core(dssdev);
  345. mutex_unlock(&hdmi.lock);
  346. }
  347. static int hdmi_connect(struct omap_dss_device *dssdev,
  348. struct omap_dss_device *dst)
  349. {
  350. enum omap_channel channel = dssdev->dispc_channel;
  351. int r;
  352. r = hdmi_init_regulator();
  353. if (r)
  354. return r;
  355. r = dss_mgr_connect(channel, dssdev);
  356. if (r)
  357. return r;
  358. r = omapdss_output_set_device(dssdev, dst);
  359. if (r) {
  360. DSSERR("failed to connect output to new device: %s\n",
  361. dst->name);
  362. dss_mgr_disconnect(channel, dssdev);
  363. return r;
  364. }
  365. return 0;
  366. }
  367. static void hdmi_disconnect(struct omap_dss_device *dssdev,
  368. struct omap_dss_device *dst)
  369. {
  370. enum omap_channel channel = dssdev->dispc_channel;
  371. WARN_ON(dst != dssdev->dst);
  372. if (dst != dssdev->dst)
  373. return;
  374. omapdss_output_unset_device(dssdev);
  375. dss_mgr_disconnect(channel, dssdev);
  376. }
  377. static int hdmi_read_edid(struct omap_dss_device *dssdev,
  378. u8 *edid, int len)
  379. {
  380. bool need_enable;
  381. int r;
  382. need_enable = hdmi.core_enabled == false;
  383. if (need_enable) {
  384. r = hdmi_core_enable(dssdev);
  385. if (r)
  386. return r;
  387. }
  388. r = read_edid(edid, len);
  389. if (need_enable)
  390. hdmi_core_disable(dssdev);
  391. return r;
  392. }
  393. static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
  394. const struct hdmi_avi_infoframe *avi)
  395. {
  396. hdmi.cfg.infoframe = *avi;
  397. return 0;
  398. }
  399. static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
  400. bool hdmi_mode)
  401. {
  402. hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
  403. return 0;
  404. }
  405. static const struct omapdss_hdmi_ops hdmi_ops = {
  406. .connect = hdmi_connect,
  407. .disconnect = hdmi_disconnect,
  408. .enable = hdmi_display_enable,
  409. .disable = hdmi_display_disable,
  410. .check_timings = hdmi_display_check_timing,
  411. .set_timings = hdmi_display_set_timing,
  412. .get_timings = hdmi_display_get_timings,
  413. .read_edid = hdmi_read_edid,
  414. .set_infoframe = hdmi_set_infoframe,
  415. .set_hdmi_mode = hdmi_set_hdmi_mode,
  416. };
  417. static void hdmi_init_output(struct platform_device *pdev)
  418. {
  419. struct omap_dss_device *out = &hdmi.output;
  420. out->dev = &pdev->dev;
  421. out->id = OMAP_DSS_OUTPUT_HDMI;
  422. out->output_type = OMAP_DISPLAY_TYPE_HDMI;
  423. out->name = "hdmi.0";
  424. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  425. out->ops.hdmi = &hdmi_ops;
  426. out->owner = THIS_MODULE;
  427. omapdss_register_output(out);
  428. }
  429. static void hdmi_uninit_output(struct platform_device *pdev)
  430. {
  431. struct omap_dss_device *out = &hdmi.output;
  432. omapdss_unregister_output(out);
  433. }
  434. static int hdmi_probe_of(struct platform_device *pdev)
  435. {
  436. struct device_node *node = pdev->dev.of_node;
  437. struct device_node *ep;
  438. int r;
  439. ep = of_graph_get_endpoint_by_regs(node, 0, 0);
  440. if (!ep)
  441. return 0;
  442. r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
  443. if (r)
  444. goto err;
  445. of_node_put(ep);
  446. return 0;
  447. err:
  448. of_node_put(ep);
  449. return r;
  450. }
  451. /* Audio callbacks */
  452. static int hdmi_audio_startup(struct device *dev,
  453. void (*abort_cb)(struct device *dev))
  454. {
  455. struct omap_hdmi *hd = dev_get_drvdata(dev);
  456. int ret = 0;
  457. mutex_lock(&hd->lock);
  458. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  459. ret = -EPERM;
  460. goto out;
  461. }
  462. hd->audio_abort_cb = abort_cb;
  463. out:
  464. mutex_unlock(&hd->lock);
  465. return ret;
  466. }
  467. static int hdmi_audio_shutdown(struct device *dev)
  468. {
  469. struct omap_hdmi *hd = dev_get_drvdata(dev);
  470. mutex_lock(&hd->lock);
  471. hd->audio_abort_cb = NULL;
  472. hd->audio_configured = false;
  473. hd->audio_playing = false;
  474. mutex_unlock(&hd->lock);
  475. return 0;
  476. }
  477. static int hdmi_audio_start(struct device *dev)
  478. {
  479. struct omap_hdmi *hd = dev_get_drvdata(dev);
  480. unsigned long flags;
  481. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  482. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  483. if (hd->display_enabled)
  484. hdmi_start_audio_stream(hd);
  485. hd->audio_playing = true;
  486. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  487. return 0;
  488. }
  489. static void hdmi_audio_stop(struct device *dev)
  490. {
  491. struct omap_hdmi *hd = dev_get_drvdata(dev);
  492. unsigned long flags;
  493. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  494. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  495. if (hd->display_enabled)
  496. hdmi_stop_audio_stream(hd);
  497. hd->audio_playing = false;
  498. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  499. }
  500. static int hdmi_audio_config(struct device *dev,
  501. struct omap_dss_audio *dss_audio)
  502. {
  503. struct omap_hdmi *hd = dev_get_drvdata(dev);
  504. int ret;
  505. mutex_lock(&hd->lock);
  506. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  507. ret = -EPERM;
  508. goto out;
  509. }
  510. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  511. hd->cfg.vm.pixelclock);
  512. if (!ret) {
  513. hd->audio_configured = true;
  514. hd->audio_config = *dss_audio;
  515. }
  516. out:
  517. mutex_unlock(&hd->lock);
  518. return ret;
  519. }
  520. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  521. .audio_startup = hdmi_audio_startup,
  522. .audio_shutdown = hdmi_audio_shutdown,
  523. .audio_start = hdmi_audio_start,
  524. .audio_stop = hdmi_audio_stop,
  525. .audio_config = hdmi_audio_config,
  526. };
  527. static int hdmi_audio_register(struct device *dev)
  528. {
  529. struct omap_hdmi_audio_pdata pdata = {
  530. .dev = dev,
  531. .dss_version = omapdss_get_version(),
  532. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
  533. .ops = &hdmi_audio_ops,
  534. };
  535. hdmi.audio_pdev = platform_device_register_data(
  536. dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  537. &pdata, sizeof(pdata));
  538. if (IS_ERR(hdmi.audio_pdev))
  539. return PTR_ERR(hdmi.audio_pdev);
  540. hdmi_runtime_get();
  541. hdmi.wp_idlemode =
  542. REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  543. hdmi_runtime_put();
  544. return 0;
  545. }
  546. /* HDMI HW IP initialisation */
  547. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  548. {
  549. struct platform_device *pdev = to_platform_device(dev);
  550. int r;
  551. int irq;
  552. hdmi.pdev = pdev;
  553. dev_set_drvdata(&pdev->dev, &hdmi);
  554. mutex_init(&hdmi.lock);
  555. spin_lock_init(&hdmi.audio_playing_lock);
  556. r = hdmi_probe_of(pdev);
  557. if (r)
  558. return r;
  559. r = hdmi_wp_init(pdev, &hdmi.wp);
  560. if (r)
  561. return r;
  562. r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
  563. if (r)
  564. return r;
  565. r = hdmi_phy_init(pdev, &hdmi.phy);
  566. if (r)
  567. goto err;
  568. r = hdmi5_core_init(pdev, &hdmi.core);
  569. if (r)
  570. goto err;
  571. irq = platform_get_irq(pdev, 0);
  572. if (irq < 0) {
  573. DSSERR("platform_get_irq failed\n");
  574. r = -ENODEV;
  575. goto err;
  576. }
  577. r = devm_request_threaded_irq(&pdev->dev, irq,
  578. NULL, hdmi_irq_handler,
  579. IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
  580. if (r) {
  581. DSSERR("HDMI IRQ request failed\n");
  582. goto err;
  583. }
  584. pm_runtime_enable(&pdev->dev);
  585. hdmi_init_output(pdev);
  586. r = hdmi_audio_register(&pdev->dev);
  587. if (r) {
  588. DSSERR("Registering HDMI audio failed %d\n", r);
  589. hdmi_uninit_output(pdev);
  590. pm_runtime_disable(&pdev->dev);
  591. return r;
  592. }
  593. dss_debugfs_create_file("hdmi", hdmi_dump_regs);
  594. return 0;
  595. err:
  596. hdmi_pll_uninit(&hdmi.pll);
  597. return r;
  598. }
  599. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  600. {
  601. struct platform_device *pdev = to_platform_device(dev);
  602. if (hdmi.audio_pdev)
  603. platform_device_unregister(hdmi.audio_pdev);
  604. hdmi_uninit_output(pdev);
  605. hdmi_pll_uninit(&hdmi.pll);
  606. pm_runtime_disable(&pdev->dev);
  607. }
  608. static const struct component_ops hdmi5_component_ops = {
  609. .bind = hdmi5_bind,
  610. .unbind = hdmi5_unbind,
  611. };
  612. static int hdmi5_probe(struct platform_device *pdev)
  613. {
  614. return component_add(&pdev->dev, &hdmi5_component_ops);
  615. }
  616. static int hdmi5_remove(struct platform_device *pdev)
  617. {
  618. component_del(&pdev->dev, &hdmi5_component_ops);
  619. return 0;
  620. }
  621. static int hdmi_runtime_suspend(struct device *dev)
  622. {
  623. dispc_runtime_put();
  624. return 0;
  625. }
  626. static int hdmi_runtime_resume(struct device *dev)
  627. {
  628. int r;
  629. r = dispc_runtime_get();
  630. if (r < 0)
  631. return r;
  632. return 0;
  633. }
  634. static const struct dev_pm_ops hdmi_pm_ops = {
  635. .runtime_suspend = hdmi_runtime_suspend,
  636. .runtime_resume = hdmi_runtime_resume,
  637. };
  638. static const struct of_device_id hdmi_of_match[] = {
  639. { .compatible = "ti,omap5-hdmi", },
  640. { .compatible = "ti,dra7-hdmi", },
  641. {},
  642. };
  643. static struct platform_driver omapdss_hdmihw_driver = {
  644. .probe = hdmi5_probe,
  645. .remove = hdmi5_remove,
  646. .driver = {
  647. .name = "omapdss_hdmi5",
  648. .pm = &hdmi_pm_ops,
  649. .of_match_table = hdmi_of_match,
  650. .suppress_bind_attrs = true,
  651. },
  652. };
  653. int __init hdmi5_init_platform_driver(void)
  654. {
  655. return platform_driver_register(&omapdss_hdmihw_driver);
  656. }
  657. void hdmi5_uninit_platform_driver(void)
  658. {
  659. platform_driver_unregister(&omapdss_hdmihw_driver);
  660. }