intel_pmc_ipc.c 18 KB

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  1. /*
  2. * intel_pmc_ipc.c: Driver for the Intel PMC IPC mechanism
  3. *
  4. * (C) Copyright 2014-2015 Intel Corporation
  5. *
  6. * This driver is based on Intel SCU IPC driver(intel_scu_opc.c) by
  7. * Sreedhara DS <sreedhara.ds@intel.com>
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; version 2
  12. * of the License.
  13. *
  14. * PMC running in ARC processor communicates with other entity running in IA
  15. * core through IPC mechanism which in turn messaging between IA core ad PMC.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/delay.h>
  19. #include <linux/errno.h>
  20. #include <linux/init.h>
  21. #include <linux/device.h>
  22. #include <linux/pm.h>
  23. #include <linux/pci.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pm_qos.h>
  27. #include <linux/kernel.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include <linux/atomic.h>
  31. #include <linux/notifier.h>
  32. #include <linux/suspend.h>
  33. #include <linux/acpi.h>
  34. #include <asm/intel_pmc_ipc.h>
  35. #include <linux/platform_data/itco_wdt.h>
  36. /*
  37. * IPC registers
  38. * The IA write to IPC_CMD command register triggers an interrupt to the ARC,
  39. * The ARC handles the interrupt and services it, writing optional data to
  40. * the IPC1 registers, updates the IPC_STS response register with the status.
  41. */
  42. #define IPC_CMD 0x0
  43. #define IPC_CMD_MSI 0x100
  44. #define IPC_CMD_SIZE 16
  45. #define IPC_CMD_SUBCMD 12
  46. #define IPC_STATUS 0x04
  47. #define IPC_STATUS_IRQ 0x4
  48. #define IPC_STATUS_ERR 0x2
  49. #define IPC_STATUS_BUSY 0x1
  50. #define IPC_SPTR 0x08
  51. #define IPC_DPTR 0x0C
  52. #define IPC_WRITE_BUFFER 0x80
  53. #define IPC_READ_BUFFER 0x90
  54. /*
  55. * 16-byte buffer for sending data associated with IPC command.
  56. */
  57. #define IPC_DATA_BUFFER_SIZE 16
  58. #define IPC_LOOP_CNT 3000000
  59. #define IPC_MAX_SEC 3
  60. #define IPC_TRIGGER_MODE_IRQ true
  61. /* exported resources from IFWI */
  62. #define PLAT_RESOURCE_IPC_INDEX 0
  63. #define PLAT_RESOURCE_IPC_SIZE 0x1000
  64. #define PLAT_RESOURCE_GCR_SIZE 0x1000
  65. #define PLAT_RESOURCE_PUNIT_DATA_INDEX 1
  66. #define PLAT_RESOURCE_PUNIT_INTER_INDEX 2
  67. #define PLAT_RESOURCE_ACPI_IO_INDEX 0
  68. /*
  69. * BIOS does not create an ACPI device for each PMC function,
  70. * but exports multiple resources from one ACPI device(IPC) for
  71. * multiple functions. This driver is responsible to create a
  72. * platform device and to export resources for those functions.
  73. */
  74. #define TCO_DEVICE_NAME "iTCO_wdt"
  75. #define SMI_EN_OFFSET 0x30
  76. #define SMI_EN_SIZE 4
  77. #define TCO_BASE_OFFSET 0x60
  78. #define TCO_REGS_SIZE 16
  79. #define PUNIT_DEVICE_NAME "intel_punit_ipc"
  80. static const int iTCO_version = 3;
  81. static struct intel_pmc_ipc_dev {
  82. struct device *dev;
  83. void __iomem *ipc_base;
  84. bool irq_mode;
  85. int irq;
  86. int cmd;
  87. struct completion cmd_complete;
  88. /* The following PMC BARs share the same ACPI device with the IPC */
  89. void *acpi_io_base;
  90. int acpi_io_size;
  91. struct platform_device *tco_dev;
  92. /* gcr */
  93. void *gcr_base;
  94. int gcr_size;
  95. /* punit */
  96. void *punit_base;
  97. int punit_size;
  98. void *punit_base2;
  99. int punit_size2;
  100. struct platform_device *punit_dev;
  101. } ipcdev;
  102. static char *ipc_err_sources[] = {
  103. [IPC_ERR_NONE] =
  104. "no error",
  105. [IPC_ERR_CMD_NOT_SUPPORTED] =
  106. "command not supported",
  107. [IPC_ERR_CMD_NOT_SERVICED] =
  108. "command not serviced",
  109. [IPC_ERR_UNABLE_TO_SERVICE] =
  110. "unable to service",
  111. [IPC_ERR_CMD_INVALID] =
  112. "command invalid",
  113. [IPC_ERR_CMD_FAILED] =
  114. "command failed",
  115. [IPC_ERR_EMSECURITY] =
  116. "Invalid Battery",
  117. [IPC_ERR_UNSIGNEDKERNEL] =
  118. "Unsigned kernel",
  119. };
  120. /* Prevent concurrent calls to the PMC */
  121. static DEFINE_MUTEX(ipclock);
  122. static inline void ipc_send_command(u32 cmd)
  123. {
  124. ipcdev.cmd = cmd;
  125. if (ipcdev.irq_mode) {
  126. reinit_completion(&ipcdev.cmd_complete);
  127. cmd |= IPC_CMD_MSI;
  128. }
  129. writel(cmd, ipcdev.ipc_base + IPC_CMD);
  130. }
  131. static inline u32 ipc_read_status(void)
  132. {
  133. return readl(ipcdev.ipc_base + IPC_STATUS);
  134. }
  135. static inline void ipc_data_writel(u32 data, u32 offset)
  136. {
  137. writel(data, ipcdev.ipc_base + IPC_WRITE_BUFFER + offset);
  138. }
  139. static inline u8 ipc_data_readb(u32 offset)
  140. {
  141. return readb(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  142. }
  143. static inline u32 ipc_data_readl(u32 offset)
  144. {
  145. return readl(ipcdev.ipc_base + IPC_READ_BUFFER + offset);
  146. }
  147. static int intel_pmc_ipc_check_status(void)
  148. {
  149. int status;
  150. int ret = 0;
  151. if (ipcdev.irq_mode) {
  152. if (0 == wait_for_completion_timeout(
  153. &ipcdev.cmd_complete, IPC_MAX_SEC * HZ))
  154. ret = -ETIMEDOUT;
  155. } else {
  156. int loop_count = IPC_LOOP_CNT;
  157. while ((ipc_read_status() & IPC_STATUS_BUSY) && --loop_count)
  158. udelay(1);
  159. if (loop_count == 0)
  160. ret = -ETIMEDOUT;
  161. }
  162. status = ipc_read_status();
  163. if (ret == -ETIMEDOUT) {
  164. dev_err(ipcdev.dev,
  165. "IPC timed out, TS=0x%x, CMD=0x%x\n",
  166. status, ipcdev.cmd);
  167. return ret;
  168. }
  169. if (status & IPC_STATUS_ERR) {
  170. int i;
  171. ret = -EIO;
  172. i = (status >> IPC_CMD_SIZE) & 0xFF;
  173. if (i < ARRAY_SIZE(ipc_err_sources))
  174. dev_err(ipcdev.dev,
  175. "IPC failed: %s, STS=0x%x, CMD=0x%x\n",
  176. ipc_err_sources[i], status, ipcdev.cmd);
  177. else
  178. dev_err(ipcdev.dev,
  179. "IPC failed: unknown, STS=0x%x, CMD=0x%x\n",
  180. status, ipcdev.cmd);
  181. if ((i == IPC_ERR_UNSIGNEDKERNEL) || (i == IPC_ERR_EMSECURITY))
  182. ret = -EACCES;
  183. }
  184. return ret;
  185. }
  186. /*
  187. * intel_pmc_ipc_simple_command
  188. * @cmd: command
  189. * @sub: sub type
  190. */
  191. int intel_pmc_ipc_simple_command(int cmd, int sub)
  192. {
  193. int ret;
  194. mutex_lock(&ipclock);
  195. if (ipcdev.dev == NULL) {
  196. mutex_unlock(&ipclock);
  197. return -ENODEV;
  198. }
  199. ipc_send_command(sub << IPC_CMD_SUBCMD | cmd);
  200. ret = intel_pmc_ipc_check_status();
  201. mutex_unlock(&ipclock);
  202. return ret;
  203. }
  204. EXPORT_SYMBOL_GPL(intel_pmc_ipc_simple_command);
  205. /*
  206. * intel_pmc_ipc_raw_cmd
  207. * @cmd: command
  208. * @sub: sub type
  209. * @in: input data
  210. * @inlen: input length in bytes
  211. * @out: output data
  212. * @outlen: output length in dwords
  213. * @sptr: data writing to SPTR register
  214. * @dptr: data writing to DPTR register
  215. */
  216. int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out,
  217. u32 outlen, u32 dptr, u32 sptr)
  218. {
  219. u32 wbuf[4] = { 0 };
  220. int ret;
  221. int i;
  222. if (inlen > IPC_DATA_BUFFER_SIZE || outlen > IPC_DATA_BUFFER_SIZE / 4)
  223. return -EINVAL;
  224. mutex_lock(&ipclock);
  225. if (ipcdev.dev == NULL) {
  226. mutex_unlock(&ipclock);
  227. return -ENODEV;
  228. }
  229. memcpy(wbuf, in, inlen);
  230. writel(dptr, ipcdev.ipc_base + IPC_DPTR);
  231. writel(sptr, ipcdev.ipc_base + IPC_SPTR);
  232. /* The input data register is 32bit register and inlen is in Byte */
  233. for (i = 0; i < ((inlen + 3) / 4); i++)
  234. ipc_data_writel(wbuf[i], 4 * i);
  235. ipc_send_command((inlen << IPC_CMD_SIZE) |
  236. (sub << IPC_CMD_SUBCMD) | cmd);
  237. ret = intel_pmc_ipc_check_status();
  238. if (!ret) {
  239. /* out is read from 32bit register and outlen is in 32bit */
  240. for (i = 0; i < outlen; i++)
  241. *out++ = ipc_data_readl(4 * i);
  242. }
  243. mutex_unlock(&ipclock);
  244. return ret;
  245. }
  246. EXPORT_SYMBOL_GPL(intel_pmc_ipc_raw_cmd);
  247. /*
  248. * intel_pmc_ipc_command
  249. * @cmd: command
  250. * @sub: sub type
  251. * @in: input data
  252. * @inlen: input length in bytes
  253. * @out: output data
  254. * @outlen: output length in dwords
  255. */
  256. int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen,
  257. u32 *out, u32 outlen)
  258. {
  259. return intel_pmc_ipc_raw_cmd(cmd, sub, in, inlen, out, outlen, 0, 0);
  260. }
  261. EXPORT_SYMBOL_GPL(intel_pmc_ipc_command);
  262. static irqreturn_t ioc(int irq, void *dev_id)
  263. {
  264. int status;
  265. if (ipcdev.irq_mode) {
  266. status = ipc_read_status();
  267. writel(status | IPC_STATUS_IRQ, ipcdev.ipc_base + IPC_STATUS);
  268. }
  269. complete(&ipcdev.cmd_complete);
  270. return IRQ_HANDLED;
  271. }
  272. static int ipc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  273. {
  274. resource_size_t pci_resource;
  275. int ret;
  276. int len;
  277. ipcdev.dev = &pci_dev_get(pdev)->dev;
  278. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  279. ret = pci_enable_device(pdev);
  280. if (ret)
  281. return ret;
  282. ret = pci_request_regions(pdev, "intel_pmc_ipc");
  283. if (ret)
  284. return ret;
  285. pci_resource = pci_resource_start(pdev, 0);
  286. len = pci_resource_len(pdev, 0);
  287. if (!pci_resource || !len) {
  288. dev_err(&pdev->dev, "Failed to get resource\n");
  289. return -ENOMEM;
  290. }
  291. init_completion(&ipcdev.cmd_complete);
  292. if (request_irq(pdev->irq, ioc, 0, "intel_pmc_ipc", &ipcdev)) {
  293. dev_err(&pdev->dev, "Failed to request irq\n");
  294. return -EBUSY;
  295. }
  296. ipcdev.ipc_base = ioremap_nocache(pci_resource, len);
  297. if (!ipcdev.ipc_base) {
  298. dev_err(&pdev->dev, "Failed to ioremap ipc base\n");
  299. free_irq(pdev->irq, &ipcdev);
  300. ret = -ENOMEM;
  301. }
  302. return ret;
  303. }
  304. static void ipc_pci_remove(struct pci_dev *pdev)
  305. {
  306. free_irq(pdev->irq, &ipcdev);
  307. pci_release_regions(pdev);
  308. pci_dev_put(pdev);
  309. iounmap(ipcdev.ipc_base);
  310. ipcdev.dev = NULL;
  311. }
  312. static const struct pci_device_id ipc_pci_ids[] = {
  313. {PCI_VDEVICE(INTEL, 0x0a94), 0},
  314. {PCI_VDEVICE(INTEL, 0x1a94), 0},
  315. { 0,}
  316. };
  317. MODULE_DEVICE_TABLE(pci, ipc_pci_ids);
  318. static struct pci_driver ipc_pci_driver = {
  319. .name = "intel_pmc_ipc",
  320. .id_table = ipc_pci_ids,
  321. .probe = ipc_pci_probe,
  322. .remove = ipc_pci_remove,
  323. };
  324. static ssize_t intel_pmc_ipc_simple_cmd_store(struct device *dev,
  325. struct device_attribute *attr,
  326. const char *buf, size_t count)
  327. {
  328. int subcmd;
  329. int cmd;
  330. int ret;
  331. ret = sscanf(buf, "%d %d", &cmd, &subcmd);
  332. if (ret != 2) {
  333. dev_err(dev, "Error args\n");
  334. return -EINVAL;
  335. }
  336. ret = intel_pmc_ipc_simple_command(cmd, subcmd);
  337. if (ret) {
  338. dev_err(dev, "command %d error with %d\n", cmd, ret);
  339. return ret;
  340. }
  341. return (ssize_t)count;
  342. }
  343. static ssize_t intel_pmc_ipc_northpeak_store(struct device *dev,
  344. struct device_attribute *attr,
  345. const char *buf, size_t count)
  346. {
  347. unsigned long val;
  348. int subcmd;
  349. int ret;
  350. if (kstrtoul(buf, 0, &val))
  351. return -EINVAL;
  352. if (val)
  353. subcmd = 1;
  354. else
  355. subcmd = 0;
  356. ret = intel_pmc_ipc_simple_command(PMC_IPC_NORTHPEAK_CTRL, subcmd);
  357. if (ret) {
  358. dev_err(dev, "command north %d error with %d\n", subcmd, ret);
  359. return ret;
  360. }
  361. return (ssize_t)count;
  362. }
  363. static DEVICE_ATTR(simplecmd, S_IWUSR,
  364. NULL, intel_pmc_ipc_simple_cmd_store);
  365. static DEVICE_ATTR(northpeak, S_IWUSR,
  366. NULL, intel_pmc_ipc_northpeak_store);
  367. static struct attribute *intel_ipc_attrs[] = {
  368. &dev_attr_northpeak.attr,
  369. &dev_attr_simplecmd.attr,
  370. NULL
  371. };
  372. static const struct attribute_group intel_ipc_group = {
  373. .attrs = intel_ipc_attrs,
  374. };
  375. #define PUNIT_RESOURCE_INTER 1
  376. static struct resource punit_res[] = {
  377. /* Punit */
  378. {
  379. .flags = IORESOURCE_MEM,
  380. },
  381. {
  382. .flags = IORESOURCE_MEM,
  383. },
  384. };
  385. #define TCO_RESOURCE_ACPI_IO 0
  386. #define TCO_RESOURCE_SMI_EN_IO 1
  387. #define TCO_RESOURCE_GCR_MEM 2
  388. static struct resource tco_res[] = {
  389. /* ACPI - TCO */
  390. {
  391. .flags = IORESOURCE_IO,
  392. },
  393. /* ACPI - SMI */
  394. {
  395. .flags = IORESOURCE_IO,
  396. },
  397. /* GCS */
  398. {
  399. .flags = IORESOURCE_MEM,
  400. },
  401. };
  402. static struct itco_wdt_platform_data tco_info = {
  403. .name = "Apollo Lake SoC",
  404. .version = 3,
  405. };
  406. static int ipc_create_punit_device(void)
  407. {
  408. struct platform_device *pdev;
  409. struct resource *res;
  410. int ret;
  411. pdev = platform_device_alloc(PUNIT_DEVICE_NAME, -1);
  412. if (!pdev) {
  413. dev_err(ipcdev.dev, "Failed to alloc punit platform device\n");
  414. return -ENOMEM;
  415. }
  416. pdev->dev.parent = ipcdev.dev;
  417. res = punit_res;
  418. res->start = (resource_size_t)ipcdev.punit_base;
  419. res->end = res->start + ipcdev.punit_size - 1;
  420. res = punit_res + PUNIT_RESOURCE_INTER;
  421. res->start = (resource_size_t)ipcdev.punit_base2;
  422. res->end = res->start + ipcdev.punit_size2 - 1;
  423. ret = platform_device_add_resources(pdev, punit_res,
  424. ARRAY_SIZE(punit_res));
  425. if (ret) {
  426. dev_err(ipcdev.dev, "Failed to add platform punit resources\n");
  427. goto err;
  428. }
  429. ret = platform_device_add(pdev);
  430. if (ret) {
  431. dev_err(ipcdev.dev, "Failed to add punit platform device\n");
  432. goto err;
  433. }
  434. ipcdev.punit_dev = pdev;
  435. return 0;
  436. err:
  437. platform_device_put(pdev);
  438. return ret;
  439. }
  440. static int ipc_create_tco_device(void)
  441. {
  442. struct platform_device *pdev;
  443. struct resource *res;
  444. int ret;
  445. pdev = platform_device_alloc(TCO_DEVICE_NAME, -1);
  446. if (!pdev) {
  447. dev_err(ipcdev.dev, "Failed to alloc tco platform device\n");
  448. return -ENOMEM;
  449. }
  450. pdev->dev.parent = ipcdev.dev;
  451. res = tco_res + TCO_RESOURCE_ACPI_IO;
  452. res->start = (resource_size_t)ipcdev.acpi_io_base + TCO_BASE_OFFSET;
  453. res->end = res->start + TCO_REGS_SIZE - 1;
  454. res = tco_res + TCO_RESOURCE_SMI_EN_IO;
  455. res->start = (resource_size_t)ipcdev.acpi_io_base + SMI_EN_OFFSET;
  456. res->end = res->start + SMI_EN_SIZE - 1;
  457. res = tco_res + TCO_RESOURCE_GCR_MEM;
  458. res->start = (resource_size_t)ipcdev.gcr_base;
  459. res->end = res->start + ipcdev.gcr_size - 1;
  460. ret = platform_device_add_resources(pdev, tco_res, ARRAY_SIZE(tco_res));
  461. if (ret) {
  462. dev_err(ipcdev.dev, "Failed to add tco platform resources\n");
  463. goto err;
  464. }
  465. ret = platform_device_add_data(pdev, &tco_info, sizeof(tco_info));
  466. if (ret) {
  467. dev_err(ipcdev.dev, "Failed to add tco platform data\n");
  468. goto err;
  469. }
  470. ret = platform_device_add(pdev);
  471. if (ret) {
  472. dev_err(ipcdev.dev, "Failed to add tco platform device\n");
  473. goto err;
  474. }
  475. ipcdev.tco_dev = pdev;
  476. return 0;
  477. err:
  478. platform_device_put(pdev);
  479. return ret;
  480. }
  481. static int ipc_create_pmc_devices(void)
  482. {
  483. int ret;
  484. ret = ipc_create_tco_device();
  485. if (ret) {
  486. dev_err(ipcdev.dev, "Failed to add tco platform device\n");
  487. return ret;
  488. }
  489. ret = ipc_create_punit_device();
  490. if (ret) {
  491. dev_err(ipcdev.dev, "Failed to add punit platform device\n");
  492. platform_device_unregister(ipcdev.tco_dev);
  493. }
  494. return ret;
  495. }
  496. static int ipc_plat_get_res(struct platform_device *pdev)
  497. {
  498. struct resource *res;
  499. void __iomem *addr;
  500. int size;
  501. res = platform_get_resource(pdev, IORESOURCE_IO,
  502. PLAT_RESOURCE_ACPI_IO_INDEX);
  503. if (!res) {
  504. dev_err(&pdev->dev, "Failed to get io resource\n");
  505. return -ENXIO;
  506. }
  507. size = resource_size(res);
  508. ipcdev.acpi_io_base = (void *)res->start;
  509. ipcdev.acpi_io_size = size;
  510. dev_info(&pdev->dev, "io res: %llx %x\n",
  511. (long long)res->start, (int)resource_size(res));
  512. res = platform_get_resource(pdev, IORESOURCE_MEM,
  513. PLAT_RESOURCE_PUNIT_DATA_INDEX);
  514. if (!res) {
  515. dev_err(&pdev->dev, "Failed to get punit resource\n");
  516. return -ENXIO;
  517. }
  518. size = resource_size(res);
  519. ipcdev.punit_base = (void *)res->start;
  520. ipcdev.punit_size = size;
  521. dev_info(&pdev->dev, "punit data res: %llx %x\n",
  522. (long long)res->start, (int)resource_size(res));
  523. res = platform_get_resource(pdev, IORESOURCE_MEM,
  524. PLAT_RESOURCE_PUNIT_INTER_INDEX);
  525. if (!res) {
  526. dev_err(&pdev->dev, "Failed to get punit inter resource\n");
  527. return -ENXIO;
  528. }
  529. size = resource_size(res);
  530. ipcdev.punit_base2 = (void *)res->start;
  531. ipcdev.punit_size2 = size;
  532. dev_info(&pdev->dev, "punit interface res: %llx %x\n",
  533. (long long)res->start, (int)resource_size(res));
  534. res = platform_get_resource(pdev, IORESOURCE_MEM,
  535. PLAT_RESOURCE_IPC_INDEX);
  536. if (!res) {
  537. dev_err(&pdev->dev, "Failed to get ipc resource\n");
  538. return -ENXIO;
  539. }
  540. size = PLAT_RESOURCE_IPC_SIZE;
  541. if (!request_mem_region(res->start, size, pdev->name)) {
  542. dev_err(&pdev->dev, "Failed to request ipc resource\n");
  543. return -EBUSY;
  544. }
  545. addr = ioremap_nocache(res->start, size);
  546. if (!addr) {
  547. dev_err(&pdev->dev, "I/O memory remapping failed\n");
  548. release_mem_region(res->start, size);
  549. return -ENOMEM;
  550. }
  551. ipcdev.ipc_base = addr;
  552. ipcdev.gcr_base = (void *)(res->start + size);
  553. ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE;
  554. dev_info(&pdev->dev, "ipc res: %llx %x\n",
  555. (long long)res->start, (int)resource_size(res));
  556. return 0;
  557. }
  558. #ifdef CONFIG_ACPI
  559. static const struct acpi_device_id ipc_acpi_ids[] = {
  560. { "INT34D2", 0},
  561. { }
  562. };
  563. MODULE_DEVICE_TABLE(acpi, ipc_acpi_ids);
  564. #endif
  565. static int ipc_plat_probe(struct platform_device *pdev)
  566. {
  567. struct resource *res;
  568. int ret;
  569. ipcdev.dev = &pdev->dev;
  570. ipcdev.irq_mode = IPC_TRIGGER_MODE_IRQ;
  571. init_completion(&ipcdev.cmd_complete);
  572. ipcdev.irq = platform_get_irq(pdev, 0);
  573. if (ipcdev.irq < 0) {
  574. dev_err(&pdev->dev, "Failed to get irq\n");
  575. return -EINVAL;
  576. }
  577. ret = ipc_plat_get_res(pdev);
  578. if (ret) {
  579. dev_err(&pdev->dev, "Failed to request resource\n");
  580. return ret;
  581. }
  582. ret = ipc_create_pmc_devices();
  583. if (ret) {
  584. dev_err(&pdev->dev, "Failed to create pmc devices\n");
  585. goto err_device;
  586. }
  587. if (request_irq(ipcdev.irq, ioc, 0, "intel_pmc_ipc", &ipcdev)) {
  588. dev_err(&pdev->dev, "Failed to request irq\n");
  589. ret = -EBUSY;
  590. goto err_irq;
  591. }
  592. ret = sysfs_create_group(&pdev->dev.kobj, &intel_ipc_group);
  593. if (ret) {
  594. dev_err(&pdev->dev, "Failed to create sysfs group %d\n",
  595. ret);
  596. goto err_sys;
  597. }
  598. return 0;
  599. err_sys:
  600. free_irq(ipcdev.irq, &ipcdev);
  601. err_irq:
  602. platform_device_unregister(ipcdev.tco_dev);
  603. platform_device_unregister(ipcdev.punit_dev);
  604. err_device:
  605. iounmap(ipcdev.ipc_base);
  606. res = platform_get_resource(pdev, IORESOURCE_MEM,
  607. PLAT_RESOURCE_IPC_INDEX);
  608. if (res)
  609. release_mem_region(res->start, PLAT_RESOURCE_IPC_SIZE);
  610. return ret;
  611. }
  612. static int ipc_plat_remove(struct platform_device *pdev)
  613. {
  614. struct resource *res;
  615. sysfs_remove_group(&pdev->dev.kobj, &intel_ipc_group);
  616. free_irq(ipcdev.irq, &ipcdev);
  617. platform_device_unregister(ipcdev.tco_dev);
  618. platform_device_unregister(ipcdev.punit_dev);
  619. iounmap(ipcdev.ipc_base);
  620. res = platform_get_resource(pdev, IORESOURCE_MEM,
  621. PLAT_RESOURCE_IPC_INDEX);
  622. if (res)
  623. release_mem_region(res->start, PLAT_RESOURCE_IPC_SIZE);
  624. ipcdev.dev = NULL;
  625. return 0;
  626. }
  627. static struct platform_driver ipc_plat_driver = {
  628. .remove = ipc_plat_remove,
  629. .probe = ipc_plat_probe,
  630. .driver = {
  631. .name = "pmc-ipc-plat",
  632. .acpi_match_table = ACPI_PTR(ipc_acpi_ids),
  633. },
  634. };
  635. static int __init intel_pmc_ipc_init(void)
  636. {
  637. int ret;
  638. ret = platform_driver_register(&ipc_plat_driver);
  639. if (ret) {
  640. pr_err("Failed to register PMC ipc platform driver\n");
  641. return ret;
  642. }
  643. ret = pci_register_driver(&ipc_pci_driver);
  644. if (ret) {
  645. pr_err("Failed to register PMC ipc pci driver\n");
  646. platform_driver_unregister(&ipc_plat_driver);
  647. return ret;
  648. }
  649. return ret;
  650. }
  651. static void __exit intel_pmc_ipc_exit(void)
  652. {
  653. pci_unregister_driver(&ipc_pci_driver);
  654. platform_driver_unregister(&ipc_plat_driver);
  655. }
  656. MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>");
  657. MODULE_DESCRIPTION("Intel PMC IPC driver");
  658. MODULE_LICENSE("GPL");
  659. /* Some modules are dependent on this, so init earlier */
  660. fs_initcall(intel_pmc_ipc_init);
  661. module_exit(intel_pmc_ipc_exit);