kfd_device_queue_manager.c 41 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/ratelimit.h>
  24. #include <linux/printk.h>
  25. #include <linux/slab.h>
  26. #include <linux/list.h>
  27. #include <linux/types.h>
  28. #include <linux/bitops.h>
  29. #include <linux/sched.h>
  30. #include "kfd_priv.h"
  31. #include "kfd_device_queue_manager.h"
  32. #include "kfd_mqd_manager.h"
  33. #include "cik_regs.h"
  34. #include "kfd_kernel_queue.h"
  35. /* Size of the per-pipe EOP queue */
  36. #define CIK_HPD_EOP_BYTES_LOG2 11
  37. #define CIK_HPD_EOP_BYTES (1U << CIK_HPD_EOP_BYTES_LOG2)
  38. static int set_pasid_vmid_mapping(struct device_queue_manager *dqm,
  39. unsigned int pasid, unsigned int vmid);
  40. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  41. struct queue *q,
  42. struct qcm_process_device *qpd);
  43. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  44. enum kfd_unmap_queues_filter filter,
  45. uint32_t filter_param);
  46. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  47. enum kfd_unmap_queues_filter filter,
  48. uint32_t filter_param);
  49. static int map_queues_cpsch(struct device_queue_manager *dqm);
  50. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  51. struct queue *q,
  52. struct qcm_process_device *qpd);
  53. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  54. unsigned int sdma_queue_id);
  55. static inline
  56. enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
  57. {
  58. if (type == KFD_QUEUE_TYPE_SDMA)
  59. return KFD_MQD_TYPE_SDMA;
  60. return KFD_MQD_TYPE_CP;
  61. }
  62. static bool is_pipe_enabled(struct device_queue_manager *dqm, int mec, int pipe)
  63. {
  64. int i;
  65. int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec
  66. + pipe * dqm->dev->shared_resources.num_queue_per_pipe;
  67. /* queue is available for KFD usage if bit is 1 */
  68. for (i = 0; i < dqm->dev->shared_resources.num_queue_per_pipe; ++i)
  69. if (test_bit(pipe_offset + i,
  70. dqm->dev->shared_resources.queue_bitmap))
  71. return true;
  72. return false;
  73. }
  74. unsigned int get_queues_num(struct device_queue_manager *dqm)
  75. {
  76. return bitmap_weight(dqm->dev->shared_resources.queue_bitmap,
  77. KGD_MAX_QUEUES);
  78. }
  79. unsigned int get_queues_per_pipe(struct device_queue_manager *dqm)
  80. {
  81. return dqm->dev->shared_resources.num_queue_per_pipe;
  82. }
  83. unsigned int get_pipes_per_mec(struct device_queue_manager *dqm)
  84. {
  85. return dqm->dev->shared_resources.num_pipe_per_mec;
  86. }
  87. void program_sh_mem_settings(struct device_queue_manager *dqm,
  88. struct qcm_process_device *qpd)
  89. {
  90. return dqm->dev->kfd2kgd->program_sh_mem_settings(
  91. dqm->dev->kgd, qpd->vmid,
  92. qpd->sh_mem_config,
  93. qpd->sh_mem_ape1_base,
  94. qpd->sh_mem_ape1_limit,
  95. qpd->sh_mem_bases);
  96. }
  97. static int allocate_vmid(struct device_queue_manager *dqm,
  98. struct qcm_process_device *qpd,
  99. struct queue *q)
  100. {
  101. int bit, allocated_vmid;
  102. if (dqm->vmid_bitmap == 0)
  103. return -ENOMEM;
  104. bit = ffs(dqm->vmid_bitmap) - 1;
  105. dqm->vmid_bitmap &= ~(1 << bit);
  106. allocated_vmid = bit + dqm->dev->vm_info.first_vmid_kfd;
  107. pr_debug("vmid allocation %d\n", allocated_vmid);
  108. qpd->vmid = allocated_vmid;
  109. q->properties.vmid = allocated_vmid;
  110. set_pasid_vmid_mapping(dqm, q->process->pasid, q->properties.vmid);
  111. program_sh_mem_settings(dqm, qpd);
  112. /* qpd->page_table_base is set earlier when register_process()
  113. * is called, i.e. when the first queue is created.
  114. */
  115. dqm->dev->kfd2kgd->set_vm_context_page_table_base(dqm->dev->kgd,
  116. qpd->vmid,
  117. qpd->page_table_base);
  118. /* invalidate the VM context after pasid and vmid mapping is set up */
  119. kfd_flush_tlb(qpd_to_pdd(qpd));
  120. return 0;
  121. }
  122. static void deallocate_vmid(struct device_queue_manager *dqm,
  123. struct qcm_process_device *qpd,
  124. struct queue *q)
  125. {
  126. int bit = qpd->vmid - dqm->dev->vm_info.first_vmid_kfd;
  127. kfd_flush_tlb(qpd_to_pdd(qpd));
  128. /* Release the vmid mapping */
  129. set_pasid_vmid_mapping(dqm, 0, qpd->vmid);
  130. dqm->vmid_bitmap |= (1 << bit);
  131. qpd->vmid = 0;
  132. q->properties.vmid = 0;
  133. }
  134. static int create_queue_nocpsch(struct device_queue_manager *dqm,
  135. struct queue *q,
  136. struct qcm_process_device *qpd)
  137. {
  138. int retval;
  139. print_queue(q);
  140. mutex_lock(&dqm->lock);
  141. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  142. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  143. dqm->total_queue_count);
  144. retval = -EPERM;
  145. goto out_unlock;
  146. }
  147. if (list_empty(&qpd->queues_list)) {
  148. retval = allocate_vmid(dqm, qpd, q);
  149. if (retval)
  150. goto out_unlock;
  151. }
  152. q->properties.vmid = qpd->vmid;
  153. /*
  154. * Eviction state logic: we only mark active queues as evicted
  155. * to avoid the overhead of restoring inactive queues later
  156. */
  157. if (qpd->evicted)
  158. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  159. q->properties.queue_percent > 0 &&
  160. q->properties.queue_address != 0);
  161. q->properties.tba_addr = qpd->tba_addr;
  162. q->properties.tma_addr = qpd->tma_addr;
  163. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE)
  164. retval = create_compute_queue_nocpsch(dqm, q, qpd);
  165. else if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  166. retval = create_sdma_queue_nocpsch(dqm, q, qpd);
  167. else
  168. retval = -EINVAL;
  169. if (retval) {
  170. if (list_empty(&qpd->queues_list))
  171. deallocate_vmid(dqm, qpd, q);
  172. goto out_unlock;
  173. }
  174. list_add(&q->list, &qpd->queues_list);
  175. qpd->queue_count++;
  176. if (q->properties.is_active)
  177. dqm->queue_count++;
  178. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  179. dqm->sdma_queue_count++;
  180. /*
  181. * Unconditionally increment this counter, regardless of the queue's
  182. * type or whether the queue is active.
  183. */
  184. dqm->total_queue_count++;
  185. pr_debug("Total of %d queues are accountable so far\n",
  186. dqm->total_queue_count);
  187. out_unlock:
  188. mutex_unlock(&dqm->lock);
  189. return retval;
  190. }
  191. static int allocate_hqd(struct device_queue_manager *dqm, struct queue *q)
  192. {
  193. bool set;
  194. int pipe, bit, i;
  195. set = false;
  196. for (pipe = dqm->next_pipe_to_allocate, i = 0;
  197. i < get_pipes_per_mec(dqm);
  198. pipe = ((pipe + 1) % get_pipes_per_mec(dqm)), ++i) {
  199. if (!is_pipe_enabled(dqm, 0, pipe))
  200. continue;
  201. if (dqm->allocated_queues[pipe] != 0) {
  202. bit = ffs(dqm->allocated_queues[pipe]) - 1;
  203. dqm->allocated_queues[pipe] &= ~(1 << bit);
  204. q->pipe = pipe;
  205. q->queue = bit;
  206. set = true;
  207. break;
  208. }
  209. }
  210. if (!set)
  211. return -EBUSY;
  212. pr_debug("hqd slot - pipe %d, queue %d\n", q->pipe, q->queue);
  213. /* horizontal hqd allocation */
  214. dqm->next_pipe_to_allocate = (pipe + 1) % get_pipes_per_mec(dqm);
  215. return 0;
  216. }
  217. static inline void deallocate_hqd(struct device_queue_manager *dqm,
  218. struct queue *q)
  219. {
  220. dqm->allocated_queues[q->pipe] |= (1 << q->queue);
  221. }
  222. static int create_compute_queue_nocpsch(struct device_queue_manager *dqm,
  223. struct queue *q,
  224. struct qcm_process_device *qpd)
  225. {
  226. int retval;
  227. struct mqd_manager *mqd;
  228. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_COMPUTE);
  229. if (!mqd)
  230. return -ENOMEM;
  231. retval = allocate_hqd(dqm, q);
  232. if (retval)
  233. return retval;
  234. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  235. &q->gart_mqd_addr, &q->properties);
  236. if (retval)
  237. goto out_deallocate_hqd;
  238. pr_debug("Loading mqd to hqd on pipe %d, queue %d\n",
  239. q->pipe, q->queue);
  240. dqm->dev->kfd2kgd->set_scratch_backing_va(
  241. dqm->dev->kgd, qpd->sh_hidden_private_base, qpd->vmid);
  242. if (!q->properties.is_active)
  243. return 0;
  244. retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue, &q->properties,
  245. q->process->mm);
  246. if (retval)
  247. goto out_uninit_mqd;
  248. return 0;
  249. out_uninit_mqd:
  250. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  251. out_deallocate_hqd:
  252. deallocate_hqd(dqm, q);
  253. return retval;
  254. }
  255. /* Access to DQM has to be locked before calling destroy_queue_nocpsch_locked
  256. * to avoid asynchronized access
  257. */
  258. static int destroy_queue_nocpsch_locked(struct device_queue_manager *dqm,
  259. struct qcm_process_device *qpd,
  260. struct queue *q)
  261. {
  262. int retval;
  263. struct mqd_manager *mqd;
  264. mqd = dqm->ops.get_mqd_manager(dqm,
  265. get_mqd_type_from_queue_type(q->properties.type));
  266. if (!mqd)
  267. return -ENOMEM;
  268. if (q->properties.type == KFD_QUEUE_TYPE_COMPUTE) {
  269. deallocate_hqd(dqm, q);
  270. } else if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  271. dqm->sdma_queue_count--;
  272. deallocate_sdma_queue(dqm, q->sdma_id);
  273. } else {
  274. pr_debug("q->properties.type %d is invalid\n",
  275. q->properties.type);
  276. return -EINVAL;
  277. }
  278. dqm->total_queue_count--;
  279. retval = mqd->destroy_mqd(mqd, q->mqd,
  280. KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
  281. KFD_UNMAP_LATENCY_MS,
  282. q->pipe, q->queue);
  283. if (retval == -ETIME)
  284. qpd->reset_wavefronts = true;
  285. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  286. list_del(&q->list);
  287. if (list_empty(&qpd->queues_list)) {
  288. if (qpd->reset_wavefronts) {
  289. pr_warn("Resetting wave fronts (nocpsch) on dev %p\n",
  290. dqm->dev);
  291. /* dbgdev_wave_reset_wavefronts has to be called before
  292. * deallocate_vmid(), i.e. when vmid is still in use.
  293. */
  294. dbgdev_wave_reset_wavefronts(dqm->dev,
  295. qpd->pqm->process);
  296. qpd->reset_wavefronts = false;
  297. }
  298. deallocate_vmid(dqm, qpd, q);
  299. }
  300. qpd->queue_count--;
  301. if (q->properties.is_active)
  302. dqm->queue_count--;
  303. return retval;
  304. }
  305. static int destroy_queue_nocpsch(struct device_queue_manager *dqm,
  306. struct qcm_process_device *qpd,
  307. struct queue *q)
  308. {
  309. int retval;
  310. mutex_lock(&dqm->lock);
  311. retval = destroy_queue_nocpsch_locked(dqm, qpd, q);
  312. mutex_unlock(&dqm->lock);
  313. return retval;
  314. }
  315. static int update_queue(struct device_queue_manager *dqm, struct queue *q)
  316. {
  317. int retval;
  318. struct mqd_manager *mqd;
  319. struct kfd_process_device *pdd;
  320. bool prev_active = false;
  321. mutex_lock(&dqm->lock);
  322. pdd = kfd_get_process_device_data(q->device, q->process);
  323. if (!pdd) {
  324. retval = -ENODEV;
  325. goto out_unlock;
  326. }
  327. mqd = dqm->ops.get_mqd_manager(dqm,
  328. get_mqd_type_from_queue_type(q->properties.type));
  329. if (!mqd) {
  330. retval = -ENOMEM;
  331. goto out_unlock;
  332. }
  333. /*
  334. * Eviction state logic: we only mark active queues as evicted
  335. * to avoid the overhead of restoring inactive queues later
  336. */
  337. if (pdd->qpd.evicted)
  338. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  339. q->properties.queue_percent > 0 &&
  340. q->properties.queue_address != 0);
  341. /* Save previous activity state for counters */
  342. prev_active = q->properties.is_active;
  343. /* Make sure the queue is unmapped before updating the MQD */
  344. if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS) {
  345. retval = unmap_queues_cpsch(dqm,
  346. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  347. if (retval) {
  348. pr_err("unmap queue failed\n");
  349. goto out_unlock;
  350. }
  351. } else if (prev_active &&
  352. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  353. q->properties.type == KFD_QUEUE_TYPE_SDMA)) {
  354. retval = mqd->destroy_mqd(mqd, q->mqd,
  355. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  356. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  357. if (retval) {
  358. pr_err("destroy mqd failed\n");
  359. goto out_unlock;
  360. }
  361. }
  362. retval = mqd->update_mqd(mqd, q->mqd, &q->properties);
  363. /*
  364. * check active state vs. the previous state and modify
  365. * counter accordingly. map_queues_cpsch uses the
  366. * dqm->queue_count to determine whether a new runlist must be
  367. * uploaded.
  368. */
  369. if (q->properties.is_active && !prev_active)
  370. dqm->queue_count++;
  371. else if (!q->properties.is_active && prev_active)
  372. dqm->queue_count--;
  373. if (dqm->sched_policy != KFD_SCHED_POLICY_NO_HWS)
  374. retval = map_queues_cpsch(dqm);
  375. else if (q->properties.is_active &&
  376. (q->properties.type == KFD_QUEUE_TYPE_COMPUTE ||
  377. q->properties.type == KFD_QUEUE_TYPE_SDMA))
  378. retval = mqd->load_mqd(mqd, q->mqd, q->pipe, q->queue,
  379. &q->properties, q->process->mm);
  380. out_unlock:
  381. mutex_unlock(&dqm->lock);
  382. return retval;
  383. }
  384. static struct mqd_manager *get_mqd_manager(
  385. struct device_queue_manager *dqm, enum KFD_MQD_TYPE type)
  386. {
  387. struct mqd_manager *mqd;
  388. if (WARN_ON(type >= KFD_MQD_TYPE_MAX))
  389. return NULL;
  390. pr_debug("mqd type %d\n", type);
  391. mqd = dqm->mqds[type];
  392. if (!mqd) {
  393. mqd = mqd_manager_init(type, dqm->dev);
  394. if (!mqd)
  395. pr_err("mqd manager is NULL");
  396. dqm->mqds[type] = mqd;
  397. }
  398. return mqd;
  399. }
  400. static int evict_process_queues_nocpsch(struct device_queue_manager *dqm,
  401. struct qcm_process_device *qpd)
  402. {
  403. struct queue *q;
  404. struct mqd_manager *mqd;
  405. struct kfd_process_device *pdd;
  406. int retval = 0;
  407. mutex_lock(&dqm->lock);
  408. if (qpd->evicted++ > 0) /* already evicted, do nothing */
  409. goto out;
  410. pdd = qpd_to_pdd(qpd);
  411. pr_info_ratelimited("Evicting PASID %u queues\n",
  412. pdd->process->pasid);
  413. /* unactivate all active queues on the qpd */
  414. list_for_each_entry(q, &qpd->queues_list, list) {
  415. if (!q->properties.is_active)
  416. continue;
  417. mqd = dqm->ops.get_mqd_manager(dqm,
  418. get_mqd_type_from_queue_type(q->properties.type));
  419. if (!mqd) { /* should not be here */
  420. pr_err("Cannot evict queue, mqd mgr is NULL\n");
  421. retval = -ENOMEM;
  422. goto out;
  423. }
  424. q->properties.is_evicted = true;
  425. q->properties.is_active = false;
  426. retval = mqd->destroy_mqd(mqd, q->mqd,
  427. KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN,
  428. KFD_UNMAP_LATENCY_MS, q->pipe, q->queue);
  429. if (retval)
  430. goto out;
  431. dqm->queue_count--;
  432. }
  433. out:
  434. mutex_unlock(&dqm->lock);
  435. return retval;
  436. }
  437. static int evict_process_queues_cpsch(struct device_queue_manager *dqm,
  438. struct qcm_process_device *qpd)
  439. {
  440. struct queue *q;
  441. struct kfd_process_device *pdd;
  442. int retval = 0;
  443. mutex_lock(&dqm->lock);
  444. if (qpd->evicted++ > 0) /* already evicted, do nothing */
  445. goto out;
  446. pdd = qpd_to_pdd(qpd);
  447. pr_info_ratelimited("Evicting PASID %u queues\n",
  448. pdd->process->pasid);
  449. /* unactivate all active queues on the qpd */
  450. list_for_each_entry(q, &qpd->queues_list, list) {
  451. if (!q->properties.is_active)
  452. continue;
  453. q->properties.is_evicted = true;
  454. q->properties.is_active = false;
  455. dqm->queue_count--;
  456. }
  457. retval = execute_queues_cpsch(dqm,
  458. qpd->is_debug ?
  459. KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES :
  460. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  461. out:
  462. mutex_unlock(&dqm->lock);
  463. return retval;
  464. }
  465. static int restore_process_queues_nocpsch(struct device_queue_manager *dqm,
  466. struct qcm_process_device *qpd)
  467. {
  468. struct queue *q;
  469. struct mqd_manager *mqd;
  470. struct kfd_process_device *pdd;
  471. uint32_t pd_base;
  472. int retval = 0;
  473. pdd = qpd_to_pdd(qpd);
  474. /* Retrieve PD base */
  475. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  476. mutex_lock(&dqm->lock);
  477. if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
  478. goto out;
  479. if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
  480. qpd->evicted--;
  481. goto out;
  482. }
  483. pr_info_ratelimited("Restoring PASID %u queues\n",
  484. pdd->process->pasid);
  485. /* Update PD Base in QPD */
  486. qpd->page_table_base = pd_base;
  487. pr_debug("Updated PD address to 0x%08x\n", pd_base);
  488. if (!list_empty(&qpd->queues_list)) {
  489. dqm->dev->kfd2kgd->set_vm_context_page_table_base(
  490. dqm->dev->kgd,
  491. qpd->vmid,
  492. qpd->page_table_base);
  493. kfd_flush_tlb(pdd);
  494. }
  495. /* activate all active queues on the qpd */
  496. list_for_each_entry(q, &qpd->queues_list, list) {
  497. if (!q->properties.is_evicted)
  498. continue;
  499. mqd = dqm->ops.get_mqd_manager(dqm,
  500. get_mqd_type_from_queue_type(q->properties.type));
  501. if (!mqd) { /* should not be here */
  502. pr_err("Cannot restore queue, mqd mgr is NULL\n");
  503. retval = -ENOMEM;
  504. goto out;
  505. }
  506. q->properties.is_evicted = false;
  507. q->properties.is_active = true;
  508. retval = mqd->load_mqd(mqd, q->mqd, q->pipe,
  509. q->queue, &q->properties,
  510. q->process->mm);
  511. if (retval)
  512. goto out;
  513. dqm->queue_count++;
  514. }
  515. qpd->evicted = 0;
  516. out:
  517. mutex_unlock(&dqm->lock);
  518. return retval;
  519. }
  520. static int restore_process_queues_cpsch(struct device_queue_manager *dqm,
  521. struct qcm_process_device *qpd)
  522. {
  523. struct queue *q;
  524. struct kfd_process_device *pdd;
  525. uint32_t pd_base;
  526. int retval = 0;
  527. pdd = qpd_to_pdd(qpd);
  528. /* Retrieve PD base */
  529. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  530. mutex_lock(&dqm->lock);
  531. if (WARN_ON_ONCE(!qpd->evicted)) /* already restored, do nothing */
  532. goto out;
  533. if (qpd->evicted > 1) { /* ref count still > 0, decrement & quit */
  534. qpd->evicted--;
  535. goto out;
  536. }
  537. pr_info_ratelimited("Restoring PASID %u queues\n",
  538. pdd->process->pasid);
  539. /* Update PD Base in QPD */
  540. qpd->page_table_base = pd_base;
  541. pr_debug("Updated PD address to 0x%08x\n", pd_base);
  542. /* activate all active queues on the qpd */
  543. list_for_each_entry(q, &qpd->queues_list, list) {
  544. if (!q->properties.is_evicted)
  545. continue;
  546. q->properties.is_evicted = false;
  547. q->properties.is_active = true;
  548. dqm->queue_count++;
  549. }
  550. retval = execute_queues_cpsch(dqm,
  551. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  552. if (!retval)
  553. qpd->evicted = 0;
  554. out:
  555. mutex_unlock(&dqm->lock);
  556. return retval;
  557. }
  558. static int register_process(struct device_queue_manager *dqm,
  559. struct qcm_process_device *qpd)
  560. {
  561. struct device_process_node *n;
  562. struct kfd_process_device *pdd;
  563. uint32_t pd_base;
  564. int retval;
  565. n = kzalloc(sizeof(*n), GFP_KERNEL);
  566. if (!n)
  567. return -ENOMEM;
  568. n->qpd = qpd;
  569. pdd = qpd_to_pdd(qpd);
  570. /* Retrieve PD base */
  571. pd_base = dqm->dev->kfd2kgd->get_process_page_dir(pdd->vm);
  572. mutex_lock(&dqm->lock);
  573. list_add(&n->list, &dqm->queues);
  574. /* Update PD Base in QPD */
  575. qpd->page_table_base = pd_base;
  576. retval = dqm->asic_ops.update_qpd(dqm, qpd);
  577. dqm->processes_count++;
  578. mutex_unlock(&dqm->lock);
  579. return retval;
  580. }
  581. static int unregister_process(struct device_queue_manager *dqm,
  582. struct qcm_process_device *qpd)
  583. {
  584. int retval;
  585. struct device_process_node *cur, *next;
  586. pr_debug("qpd->queues_list is %s\n",
  587. list_empty(&qpd->queues_list) ? "empty" : "not empty");
  588. retval = 0;
  589. mutex_lock(&dqm->lock);
  590. list_for_each_entry_safe(cur, next, &dqm->queues, list) {
  591. if (qpd == cur->qpd) {
  592. list_del(&cur->list);
  593. kfree(cur);
  594. dqm->processes_count--;
  595. goto out;
  596. }
  597. }
  598. /* qpd not found in dqm list */
  599. retval = 1;
  600. out:
  601. mutex_unlock(&dqm->lock);
  602. return retval;
  603. }
  604. static int
  605. set_pasid_vmid_mapping(struct device_queue_manager *dqm, unsigned int pasid,
  606. unsigned int vmid)
  607. {
  608. uint32_t pasid_mapping;
  609. pasid_mapping = (pasid == 0) ? 0 :
  610. (uint32_t)pasid |
  611. ATC_VMID_PASID_MAPPING_VALID;
  612. return dqm->dev->kfd2kgd->set_pasid_vmid_mapping(
  613. dqm->dev->kgd, pasid_mapping,
  614. vmid);
  615. }
  616. static void init_interrupts(struct device_queue_manager *dqm)
  617. {
  618. unsigned int i;
  619. for (i = 0 ; i < get_pipes_per_mec(dqm) ; i++)
  620. if (is_pipe_enabled(dqm, 0, i))
  621. dqm->dev->kfd2kgd->init_interrupts(dqm->dev->kgd, i);
  622. }
  623. static int initialize_nocpsch(struct device_queue_manager *dqm)
  624. {
  625. int pipe, queue;
  626. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  627. dqm->allocated_queues = kcalloc(get_pipes_per_mec(dqm),
  628. sizeof(unsigned int), GFP_KERNEL);
  629. if (!dqm->allocated_queues)
  630. return -ENOMEM;
  631. mutex_init(&dqm->lock);
  632. INIT_LIST_HEAD(&dqm->queues);
  633. dqm->queue_count = dqm->next_pipe_to_allocate = 0;
  634. dqm->sdma_queue_count = 0;
  635. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  636. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  637. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++)
  638. if (test_bit(pipe_offset + queue,
  639. dqm->dev->shared_resources.queue_bitmap))
  640. dqm->allocated_queues[pipe] |= 1 << queue;
  641. }
  642. dqm->vmid_bitmap = (1 << dqm->dev->vm_info.vmid_num_kfd) - 1;
  643. dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
  644. return 0;
  645. }
  646. static void uninitialize(struct device_queue_manager *dqm)
  647. {
  648. int i;
  649. WARN_ON(dqm->queue_count > 0 || dqm->processes_count > 0);
  650. kfree(dqm->allocated_queues);
  651. for (i = 0 ; i < KFD_MQD_TYPE_MAX ; i++)
  652. kfree(dqm->mqds[i]);
  653. mutex_destroy(&dqm->lock);
  654. kfd_gtt_sa_free(dqm->dev, dqm->pipeline_mem);
  655. }
  656. static int start_nocpsch(struct device_queue_manager *dqm)
  657. {
  658. init_interrupts(dqm);
  659. return 0;
  660. }
  661. static int stop_nocpsch(struct device_queue_manager *dqm)
  662. {
  663. return 0;
  664. }
  665. static int allocate_sdma_queue(struct device_queue_manager *dqm,
  666. unsigned int *sdma_queue_id)
  667. {
  668. int bit;
  669. if (dqm->sdma_bitmap == 0)
  670. return -ENOMEM;
  671. bit = ffs(dqm->sdma_bitmap) - 1;
  672. dqm->sdma_bitmap &= ~(1 << bit);
  673. *sdma_queue_id = bit;
  674. return 0;
  675. }
  676. static void deallocate_sdma_queue(struct device_queue_manager *dqm,
  677. unsigned int sdma_queue_id)
  678. {
  679. if (sdma_queue_id >= CIK_SDMA_QUEUES)
  680. return;
  681. dqm->sdma_bitmap |= (1 << sdma_queue_id);
  682. }
  683. static int create_sdma_queue_nocpsch(struct device_queue_manager *dqm,
  684. struct queue *q,
  685. struct qcm_process_device *qpd)
  686. {
  687. struct mqd_manager *mqd;
  688. int retval;
  689. mqd = dqm->ops.get_mqd_manager(dqm, KFD_MQD_TYPE_SDMA);
  690. if (!mqd)
  691. return -ENOMEM;
  692. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  693. if (retval)
  694. return retval;
  695. q->properties.sdma_queue_id = q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
  696. q->properties.sdma_engine_id = q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
  697. pr_debug("SDMA id is: %d\n", q->sdma_id);
  698. pr_debug("SDMA queue id: %d\n", q->properties.sdma_queue_id);
  699. pr_debug("SDMA engine id: %d\n", q->properties.sdma_engine_id);
  700. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  701. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  702. &q->gart_mqd_addr, &q->properties);
  703. if (retval)
  704. goto out_deallocate_sdma_queue;
  705. retval = mqd->load_mqd(mqd, q->mqd, 0, 0, &q->properties, NULL);
  706. if (retval)
  707. goto out_uninit_mqd;
  708. return 0;
  709. out_uninit_mqd:
  710. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  711. out_deallocate_sdma_queue:
  712. deallocate_sdma_queue(dqm, q->sdma_id);
  713. return retval;
  714. }
  715. /*
  716. * Device Queue Manager implementation for cp scheduler
  717. */
  718. static int set_sched_resources(struct device_queue_manager *dqm)
  719. {
  720. int i, mec;
  721. struct scheduling_resources res;
  722. res.vmid_mask = dqm->dev->shared_resources.compute_vmid_bitmap;
  723. res.queue_mask = 0;
  724. for (i = 0; i < KGD_MAX_QUEUES; ++i) {
  725. mec = (i / dqm->dev->shared_resources.num_queue_per_pipe)
  726. / dqm->dev->shared_resources.num_pipe_per_mec;
  727. if (!test_bit(i, dqm->dev->shared_resources.queue_bitmap))
  728. continue;
  729. /* only acquire queues from the first MEC */
  730. if (mec > 0)
  731. continue;
  732. /* This situation may be hit in the future if a new HW
  733. * generation exposes more than 64 queues. If so, the
  734. * definition of res.queue_mask needs updating
  735. */
  736. if (WARN_ON(i >= (sizeof(res.queue_mask)*8))) {
  737. pr_err("Invalid queue enabled by amdgpu: %d\n", i);
  738. break;
  739. }
  740. res.queue_mask |= (1ull << i);
  741. }
  742. res.gws_mask = res.oac_mask = res.gds_heap_base =
  743. res.gds_heap_size = 0;
  744. pr_debug("Scheduling resources:\n"
  745. "vmid mask: 0x%8X\n"
  746. "queue mask: 0x%8llX\n",
  747. res.vmid_mask, res.queue_mask);
  748. return pm_send_set_resources(&dqm->packets, &res);
  749. }
  750. static int initialize_cpsch(struct device_queue_manager *dqm)
  751. {
  752. pr_debug("num of pipes: %d\n", get_pipes_per_mec(dqm));
  753. mutex_init(&dqm->lock);
  754. INIT_LIST_HEAD(&dqm->queues);
  755. dqm->queue_count = dqm->processes_count = 0;
  756. dqm->sdma_queue_count = 0;
  757. dqm->active_runlist = false;
  758. dqm->sdma_bitmap = (1 << CIK_SDMA_QUEUES) - 1;
  759. return 0;
  760. }
  761. static int start_cpsch(struct device_queue_manager *dqm)
  762. {
  763. int retval;
  764. retval = 0;
  765. retval = pm_init(&dqm->packets, dqm);
  766. if (retval)
  767. goto fail_packet_manager_init;
  768. retval = set_sched_resources(dqm);
  769. if (retval)
  770. goto fail_set_sched_resources;
  771. pr_debug("Allocating fence memory\n");
  772. /* allocate fence memory on the gart */
  773. retval = kfd_gtt_sa_allocate(dqm->dev, sizeof(*dqm->fence_addr),
  774. &dqm->fence_mem);
  775. if (retval)
  776. goto fail_allocate_vidmem;
  777. dqm->fence_addr = dqm->fence_mem->cpu_ptr;
  778. dqm->fence_gpu_addr = dqm->fence_mem->gpu_addr;
  779. init_interrupts(dqm);
  780. mutex_lock(&dqm->lock);
  781. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  782. mutex_unlock(&dqm->lock);
  783. return 0;
  784. fail_allocate_vidmem:
  785. fail_set_sched_resources:
  786. pm_uninit(&dqm->packets);
  787. fail_packet_manager_init:
  788. return retval;
  789. }
  790. static int stop_cpsch(struct device_queue_manager *dqm)
  791. {
  792. mutex_lock(&dqm->lock);
  793. unmap_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  794. mutex_unlock(&dqm->lock);
  795. kfd_gtt_sa_free(dqm->dev, dqm->fence_mem);
  796. pm_uninit(&dqm->packets);
  797. return 0;
  798. }
  799. static int create_kernel_queue_cpsch(struct device_queue_manager *dqm,
  800. struct kernel_queue *kq,
  801. struct qcm_process_device *qpd)
  802. {
  803. mutex_lock(&dqm->lock);
  804. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  805. pr_warn("Can't create new kernel queue because %d queues were already created\n",
  806. dqm->total_queue_count);
  807. mutex_unlock(&dqm->lock);
  808. return -EPERM;
  809. }
  810. /*
  811. * Unconditionally increment this counter, regardless of the queue's
  812. * type or whether the queue is active.
  813. */
  814. dqm->total_queue_count++;
  815. pr_debug("Total of %d queues are accountable so far\n",
  816. dqm->total_queue_count);
  817. list_add(&kq->list, &qpd->priv_queue_list);
  818. dqm->queue_count++;
  819. qpd->is_debug = true;
  820. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  821. mutex_unlock(&dqm->lock);
  822. return 0;
  823. }
  824. static void destroy_kernel_queue_cpsch(struct device_queue_manager *dqm,
  825. struct kernel_queue *kq,
  826. struct qcm_process_device *qpd)
  827. {
  828. mutex_lock(&dqm->lock);
  829. list_del(&kq->list);
  830. dqm->queue_count--;
  831. qpd->is_debug = false;
  832. execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0);
  833. /*
  834. * Unconditionally decrement this counter, regardless of the queue's
  835. * type.
  836. */
  837. dqm->total_queue_count--;
  838. pr_debug("Total of %d queues are accountable so far\n",
  839. dqm->total_queue_count);
  840. mutex_unlock(&dqm->lock);
  841. }
  842. static int create_queue_cpsch(struct device_queue_manager *dqm, struct queue *q,
  843. struct qcm_process_device *qpd)
  844. {
  845. int retval;
  846. struct mqd_manager *mqd;
  847. retval = 0;
  848. mutex_lock(&dqm->lock);
  849. if (dqm->total_queue_count >= max_num_of_queues_per_device) {
  850. pr_warn("Can't create new usermode queue because %d queues were already created\n",
  851. dqm->total_queue_count);
  852. retval = -EPERM;
  853. goto out;
  854. }
  855. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  856. retval = allocate_sdma_queue(dqm, &q->sdma_id);
  857. if (retval)
  858. goto out;
  859. q->properties.sdma_queue_id =
  860. q->sdma_id / CIK_SDMA_QUEUES_PER_ENGINE;
  861. q->properties.sdma_engine_id =
  862. q->sdma_id % CIK_SDMA_QUEUES_PER_ENGINE;
  863. }
  864. mqd = dqm->ops.get_mqd_manager(dqm,
  865. get_mqd_type_from_queue_type(q->properties.type));
  866. if (!mqd) {
  867. retval = -ENOMEM;
  868. goto out;
  869. }
  870. /*
  871. * Eviction state logic: we only mark active queues as evicted
  872. * to avoid the overhead of restoring inactive queues later
  873. */
  874. if (qpd->evicted)
  875. q->properties.is_evicted = (q->properties.queue_size > 0 &&
  876. q->properties.queue_percent > 0 &&
  877. q->properties.queue_address != 0);
  878. dqm->asic_ops.init_sdma_vm(dqm, q, qpd);
  879. q->properties.tba_addr = qpd->tba_addr;
  880. q->properties.tma_addr = qpd->tma_addr;
  881. retval = mqd->init_mqd(mqd, &q->mqd, &q->mqd_mem_obj,
  882. &q->gart_mqd_addr, &q->properties);
  883. if (retval)
  884. goto out;
  885. list_add(&q->list, &qpd->queues_list);
  886. qpd->queue_count++;
  887. if (q->properties.is_active) {
  888. dqm->queue_count++;
  889. retval = execute_queues_cpsch(dqm,
  890. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  891. }
  892. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  893. dqm->sdma_queue_count++;
  894. /*
  895. * Unconditionally increment this counter, regardless of the queue's
  896. * type or whether the queue is active.
  897. */
  898. dqm->total_queue_count++;
  899. pr_debug("Total of %d queues are accountable so far\n",
  900. dqm->total_queue_count);
  901. out:
  902. mutex_unlock(&dqm->lock);
  903. return retval;
  904. }
  905. int amdkfd_fence_wait_timeout(unsigned int *fence_addr,
  906. unsigned int fence_value,
  907. unsigned int timeout_ms)
  908. {
  909. unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies;
  910. while (*fence_addr != fence_value) {
  911. if (time_after(jiffies, end_jiffies)) {
  912. pr_err("qcm fence wait loop timeout expired\n");
  913. return -ETIME;
  914. }
  915. schedule();
  916. }
  917. return 0;
  918. }
  919. static int unmap_sdma_queues(struct device_queue_manager *dqm,
  920. unsigned int sdma_engine)
  921. {
  922. return pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_SDMA,
  923. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, false,
  924. sdma_engine);
  925. }
  926. /* dqm->lock mutex has to be locked before calling this function */
  927. static int map_queues_cpsch(struct device_queue_manager *dqm)
  928. {
  929. int retval;
  930. if (dqm->queue_count <= 0 || dqm->processes_count <= 0)
  931. return 0;
  932. if (dqm->active_runlist)
  933. return 0;
  934. retval = pm_send_runlist(&dqm->packets, &dqm->queues);
  935. if (retval) {
  936. pr_err("failed to execute runlist\n");
  937. return retval;
  938. }
  939. dqm->active_runlist = true;
  940. return retval;
  941. }
  942. /* dqm->lock mutex has to be locked before calling this function */
  943. static int unmap_queues_cpsch(struct device_queue_manager *dqm,
  944. enum kfd_unmap_queues_filter filter,
  945. uint32_t filter_param)
  946. {
  947. int retval = 0;
  948. if (!dqm->active_runlist)
  949. return retval;
  950. pr_debug("Before destroying queues, sdma queue count is : %u\n",
  951. dqm->sdma_queue_count);
  952. if (dqm->sdma_queue_count > 0) {
  953. unmap_sdma_queues(dqm, 0);
  954. unmap_sdma_queues(dqm, 1);
  955. }
  956. retval = pm_send_unmap_queue(&dqm->packets, KFD_QUEUE_TYPE_COMPUTE,
  957. filter, filter_param, false, 0);
  958. if (retval)
  959. return retval;
  960. *dqm->fence_addr = KFD_FENCE_INIT;
  961. pm_send_query_status(&dqm->packets, dqm->fence_gpu_addr,
  962. KFD_FENCE_COMPLETED);
  963. /* should be timed out */
  964. retval = amdkfd_fence_wait_timeout(dqm->fence_addr, KFD_FENCE_COMPLETED,
  965. QUEUE_PREEMPT_DEFAULT_TIMEOUT_MS);
  966. if (retval)
  967. return retval;
  968. pm_release_ib(&dqm->packets);
  969. dqm->active_runlist = false;
  970. return retval;
  971. }
  972. /* dqm->lock mutex has to be locked before calling this function */
  973. static int execute_queues_cpsch(struct device_queue_manager *dqm,
  974. enum kfd_unmap_queues_filter filter,
  975. uint32_t filter_param)
  976. {
  977. int retval;
  978. retval = unmap_queues_cpsch(dqm, filter, filter_param);
  979. if (retval) {
  980. pr_err("The cp might be in an unrecoverable state due to an unsuccessful queues preemption\n");
  981. return retval;
  982. }
  983. return map_queues_cpsch(dqm);
  984. }
  985. static int destroy_queue_cpsch(struct device_queue_manager *dqm,
  986. struct qcm_process_device *qpd,
  987. struct queue *q)
  988. {
  989. int retval;
  990. struct mqd_manager *mqd;
  991. bool preempt_all_queues;
  992. preempt_all_queues = false;
  993. retval = 0;
  994. /* remove queue from list to prevent rescheduling after preemption */
  995. mutex_lock(&dqm->lock);
  996. if (qpd->is_debug) {
  997. /*
  998. * error, currently we do not allow to destroy a queue
  999. * of a currently debugged process
  1000. */
  1001. retval = -EBUSY;
  1002. goto failed_try_destroy_debugged_queue;
  1003. }
  1004. mqd = dqm->ops.get_mqd_manager(dqm,
  1005. get_mqd_type_from_queue_type(q->properties.type));
  1006. if (!mqd) {
  1007. retval = -ENOMEM;
  1008. goto failed;
  1009. }
  1010. if (q->properties.type == KFD_QUEUE_TYPE_SDMA) {
  1011. dqm->sdma_queue_count--;
  1012. deallocate_sdma_queue(dqm, q->sdma_id);
  1013. }
  1014. list_del(&q->list);
  1015. qpd->queue_count--;
  1016. if (q->properties.is_active) {
  1017. dqm->queue_count--;
  1018. retval = execute_queues_cpsch(dqm,
  1019. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0);
  1020. if (retval == -ETIME)
  1021. qpd->reset_wavefronts = true;
  1022. }
  1023. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  1024. /*
  1025. * Unconditionally decrement this counter, regardless of the queue's
  1026. * type
  1027. */
  1028. dqm->total_queue_count--;
  1029. pr_debug("Total of %d queues are accountable so far\n",
  1030. dqm->total_queue_count);
  1031. mutex_unlock(&dqm->lock);
  1032. return retval;
  1033. failed:
  1034. failed_try_destroy_debugged_queue:
  1035. mutex_unlock(&dqm->lock);
  1036. return retval;
  1037. }
  1038. /*
  1039. * Low bits must be 0000/FFFF as required by HW, high bits must be 0 to
  1040. * stay in user mode.
  1041. */
  1042. #define APE1_FIXED_BITS_MASK 0xFFFF80000000FFFFULL
  1043. /* APE1 limit is inclusive and 64K aligned. */
  1044. #define APE1_LIMIT_ALIGNMENT 0xFFFF
  1045. static bool set_cache_memory_policy(struct device_queue_manager *dqm,
  1046. struct qcm_process_device *qpd,
  1047. enum cache_policy default_policy,
  1048. enum cache_policy alternate_policy,
  1049. void __user *alternate_aperture_base,
  1050. uint64_t alternate_aperture_size)
  1051. {
  1052. bool retval;
  1053. mutex_lock(&dqm->lock);
  1054. if (alternate_aperture_size == 0) {
  1055. /* base > limit disables APE1 */
  1056. qpd->sh_mem_ape1_base = 1;
  1057. qpd->sh_mem_ape1_limit = 0;
  1058. } else {
  1059. /*
  1060. * In FSA64, APE1_Base[63:0] = { 16{SH_MEM_APE1_BASE[31]},
  1061. * SH_MEM_APE1_BASE[31:0], 0x0000 }
  1062. * APE1_Limit[63:0] = { 16{SH_MEM_APE1_LIMIT[31]},
  1063. * SH_MEM_APE1_LIMIT[31:0], 0xFFFF }
  1064. * Verify that the base and size parameters can be
  1065. * represented in this format and convert them.
  1066. * Additionally restrict APE1 to user-mode addresses.
  1067. */
  1068. uint64_t base = (uintptr_t)alternate_aperture_base;
  1069. uint64_t limit = base + alternate_aperture_size - 1;
  1070. if (limit <= base || (base & APE1_FIXED_BITS_MASK) != 0 ||
  1071. (limit & APE1_FIXED_BITS_MASK) != APE1_LIMIT_ALIGNMENT) {
  1072. retval = false;
  1073. goto out;
  1074. }
  1075. qpd->sh_mem_ape1_base = base >> 16;
  1076. qpd->sh_mem_ape1_limit = limit >> 16;
  1077. }
  1078. retval = dqm->asic_ops.set_cache_memory_policy(
  1079. dqm,
  1080. qpd,
  1081. default_policy,
  1082. alternate_policy,
  1083. alternate_aperture_base,
  1084. alternate_aperture_size);
  1085. if ((dqm->sched_policy == KFD_SCHED_POLICY_NO_HWS) && (qpd->vmid != 0))
  1086. program_sh_mem_settings(dqm, qpd);
  1087. pr_debug("sh_mem_config: 0x%x, ape1_base: 0x%x, ape1_limit: 0x%x\n",
  1088. qpd->sh_mem_config, qpd->sh_mem_ape1_base,
  1089. qpd->sh_mem_ape1_limit);
  1090. out:
  1091. mutex_unlock(&dqm->lock);
  1092. return retval;
  1093. }
  1094. static int set_trap_handler(struct device_queue_manager *dqm,
  1095. struct qcm_process_device *qpd,
  1096. uint64_t tba_addr,
  1097. uint64_t tma_addr)
  1098. {
  1099. uint64_t *tma;
  1100. if (dqm->dev->cwsr_enabled) {
  1101. /* Jump from CWSR trap handler to user trap */
  1102. tma = (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET);
  1103. tma[0] = tba_addr;
  1104. tma[1] = tma_addr;
  1105. } else {
  1106. qpd->tba_addr = tba_addr;
  1107. qpd->tma_addr = tma_addr;
  1108. }
  1109. return 0;
  1110. }
  1111. static int process_termination_nocpsch(struct device_queue_manager *dqm,
  1112. struct qcm_process_device *qpd)
  1113. {
  1114. struct queue *q, *next;
  1115. struct device_process_node *cur, *next_dpn;
  1116. int retval = 0;
  1117. mutex_lock(&dqm->lock);
  1118. /* Clear all user mode queues */
  1119. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  1120. int ret;
  1121. ret = destroy_queue_nocpsch_locked(dqm, qpd, q);
  1122. if (ret)
  1123. retval = ret;
  1124. }
  1125. /* Unregister process */
  1126. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  1127. if (qpd == cur->qpd) {
  1128. list_del(&cur->list);
  1129. kfree(cur);
  1130. dqm->processes_count--;
  1131. break;
  1132. }
  1133. }
  1134. mutex_unlock(&dqm->lock);
  1135. return retval;
  1136. }
  1137. static int process_termination_cpsch(struct device_queue_manager *dqm,
  1138. struct qcm_process_device *qpd)
  1139. {
  1140. int retval;
  1141. struct queue *q, *next;
  1142. struct kernel_queue *kq, *kq_next;
  1143. struct mqd_manager *mqd;
  1144. struct device_process_node *cur, *next_dpn;
  1145. enum kfd_unmap_queues_filter filter =
  1146. KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES;
  1147. retval = 0;
  1148. mutex_lock(&dqm->lock);
  1149. /* Clean all kernel queues */
  1150. list_for_each_entry_safe(kq, kq_next, &qpd->priv_queue_list, list) {
  1151. list_del(&kq->list);
  1152. dqm->queue_count--;
  1153. qpd->is_debug = false;
  1154. dqm->total_queue_count--;
  1155. filter = KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES;
  1156. }
  1157. /* Clear all user mode queues */
  1158. list_for_each_entry(q, &qpd->queues_list, list) {
  1159. if (q->properties.type == KFD_QUEUE_TYPE_SDMA)
  1160. dqm->sdma_queue_count--;
  1161. if (q->properties.is_active)
  1162. dqm->queue_count--;
  1163. dqm->total_queue_count--;
  1164. }
  1165. /* Unregister process */
  1166. list_for_each_entry_safe(cur, next_dpn, &dqm->queues, list) {
  1167. if (qpd == cur->qpd) {
  1168. list_del(&cur->list);
  1169. kfree(cur);
  1170. dqm->processes_count--;
  1171. break;
  1172. }
  1173. }
  1174. retval = execute_queues_cpsch(dqm, filter, 0);
  1175. if (retval || qpd->reset_wavefronts) {
  1176. pr_warn("Resetting wave fronts (cpsch) on dev %p\n", dqm->dev);
  1177. dbgdev_wave_reset_wavefronts(dqm->dev, qpd->pqm->process);
  1178. qpd->reset_wavefronts = false;
  1179. }
  1180. /* lastly, free mqd resources */
  1181. list_for_each_entry_safe(q, next, &qpd->queues_list, list) {
  1182. mqd = dqm->ops.get_mqd_manager(dqm,
  1183. get_mqd_type_from_queue_type(q->properties.type));
  1184. if (!mqd) {
  1185. retval = -ENOMEM;
  1186. goto out;
  1187. }
  1188. list_del(&q->list);
  1189. qpd->queue_count--;
  1190. mqd->uninit_mqd(mqd, q->mqd, q->mqd_mem_obj);
  1191. }
  1192. out:
  1193. mutex_unlock(&dqm->lock);
  1194. return retval;
  1195. }
  1196. struct device_queue_manager *device_queue_manager_init(struct kfd_dev *dev)
  1197. {
  1198. struct device_queue_manager *dqm;
  1199. pr_debug("Loading device queue manager\n");
  1200. dqm = kzalloc(sizeof(*dqm), GFP_KERNEL);
  1201. if (!dqm)
  1202. return NULL;
  1203. switch (dev->device_info->asic_family) {
  1204. /* HWS is not available on Hawaii. */
  1205. case CHIP_HAWAII:
  1206. /* HWS depends on CWSR for timely dequeue. CWSR is not
  1207. * available on Tonga.
  1208. *
  1209. * FIXME: This argument also applies to Kaveri.
  1210. */
  1211. case CHIP_TONGA:
  1212. dqm->sched_policy = KFD_SCHED_POLICY_NO_HWS;
  1213. break;
  1214. default:
  1215. dqm->sched_policy = sched_policy;
  1216. break;
  1217. }
  1218. dqm->dev = dev;
  1219. switch (dqm->sched_policy) {
  1220. case KFD_SCHED_POLICY_HWS:
  1221. case KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION:
  1222. /* initialize dqm for cp scheduling */
  1223. dqm->ops.create_queue = create_queue_cpsch;
  1224. dqm->ops.initialize = initialize_cpsch;
  1225. dqm->ops.start = start_cpsch;
  1226. dqm->ops.stop = stop_cpsch;
  1227. dqm->ops.destroy_queue = destroy_queue_cpsch;
  1228. dqm->ops.update_queue = update_queue;
  1229. dqm->ops.get_mqd_manager = get_mqd_manager;
  1230. dqm->ops.register_process = register_process;
  1231. dqm->ops.unregister_process = unregister_process;
  1232. dqm->ops.uninitialize = uninitialize;
  1233. dqm->ops.create_kernel_queue = create_kernel_queue_cpsch;
  1234. dqm->ops.destroy_kernel_queue = destroy_kernel_queue_cpsch;
  1235. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1236. dqm->ops.set_trap_handler = set_trap_handler;
  1237. dqm->ops.process_termination = process_termination_cpsch;
  1238. dqm->ops.evict_process_queues = evict_process_queues_cpsch;
  1239. dqm->ops.restore_process_queues = restore_process_queues_cpsch;
  1240. break;
  1241. case KFD_SCHED_POLICY_NO_HWS:
  1242. /* initialize dqm for no cp scheduling */
  1243. dqm->ops.start = start_nocpsch;
  1244. dqm->ops.stop = stop_nocpsch;
  1245. dqm->ops.create_queue = create_queue_nocpsch;
  1246. dqm->ops.destroy_queue = destroy_queue_nocpsch;
  1247. dqm->ops.update_queue = update_queue;
  1248. dqm->ops.get_mqd_manager = get_mqd_manager;
  1249. dqm->ops.register_process = register_process;
  1250. dqm->ops.unregister_process = unregister_process;
  1251. dqm->ops.initialize = initialize_nocpsch;
  1252. dqm->ops.uninitialize = uninitialize;
  1253. dqm->ops.set_cache_memory_policy = set_cache_memory_policy;
  1254. dqm->ops.set_trap_handler = set_trap_handler;
  1255. dqm->ops.process_termination = process_termination_nocpsch;
  1256. dqm->ops.evict_process_queues = evict_process_queues_nocpsch;
  1257. dqm->ops.restore_process_queues =
  1258. restore_process_queues_nocpsch;
  1259. break;
  1260. default:
  1261. pr_err("Invalid scheduling policy %d\n", dqm->sched_policy);
  1262. goto out_free;
  1263. }
  1264. switch (dev->device_info->asic_family) {
  1265. case CHIP_CARRIZO:
  1266. device_queue_manager_init_vi(&dqm->asic_ops);
  1267. break;
  1268. case CHIP_KAVERI:
  1269. device_queue_manager_init_cik(&dqm->asic_ops);
  1270. break;
  1271. case CHIP_HAWAII:
  1272. device_queue_manager_init_cik_hawaii(&dqm->asic_ops);
  1273. break;
  1274. case CHIP_TONGA:
  1275. case CHIP_FIJI:
  1276. case CHIP_POLARIS10:
  1277. case CHIP_POLARIS11:
  1278. device_queue_manager_init_vi_tonga(&dqm->asic_ops);
  1279. break;
  1280. default:
  1281. WARN(1, "Unexpected ASIC family %u",
  1282. dev->device_info->asic_family);
  1283. goto out_free;
  1284. }
  1285. if (!dqm->ops.initialize(dqm))
  1286. return dqm;
  1287. out_free:
  1288. kfree(dqm);
  1289. return NULL;
  1290. }
  1291. void device_queue_manager_uninit(struct device_queue_manager *dqm)
  1292. {
  1293. dqm->ops.uninitialize(dqm);
  1294. kfree(dqm);
  1295. }
  1296. #if defined(CONFIG_DEBUG_FS)
  1297. static void seq_reg_dump(struct seq_file *m,
  1298. uint32_t (*dump)[2], uint32_t n_regs)
  1299. {
  1300. uint32_t i, count;
  1301. for (i = 0, count = 0; i < n_regs; i++) {
  1302. if (count == 0 ||
  1303. dump[i-1][0] + sizeof(uint32_t) != dump[i][0]) {
  1304. seq_printf(m, "%s %08x: %08x",
  1305. i ? "\n" : "",
  1306. dump[i][0], dump[i][1]);
  1307. count = 7;
  1308. } else {
  1309. seq_printf(m, " %08x", dump[i][1]);
  1310. count--;
  1311. }
  1312. }
  1313. seq_puts(m, "\n");
  1314. }
  1315. int dqm_debugfs_hqds(struct seq_file *m, void *data)
  1316. {
  1317. struct device_queue_manager *dqm = data;
  1318. uint32_t (*dump)[2], n_regs;
  1319. int pipe, queue;
  1320. int r = 0;
  1321. for (pipe = 0; pipe < get_pipes_per_mec(dqm); pipe++) {
  1322. int pipe_offset = pipe * get_queues_per_pipe(dqm);
  1323. for (queue = 0; queue < get_queues_per_pipe(dqm); queue++) {
  1324. if (!test_bit(pipe_offset + queue,
  1325. dqm->dev->shared_resources.queue_bitmap))
  1326. continue;
  1327. r = dqm->dev->kfd2kgd->hqd_dump(
  1328. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1329. if (r)
  1330. break;
  1331. seq_printf(m, " CP Pipe %d, Queue %d\n",
  1332. pipe, queue);
  1333. seq_reg_dump(m, dump, n_regs);
  1334. kfree(dump);
  1335. }
  1336. }
  1337. for (pipe = 0; pipe < CIK_SDMA_ENGINE_NUM; pipe++) {
  1338. for (queue = 0; queue < CIK_SDMA_QUEUES_PER_ENGINE; queue++) {
  1339. r = dqm->dev->kfd2kgd->hqd_sdma_dump(
  1340. dqm->dev->kgd, pipe, queue, &dump, &n_regs);
  1341. if (r)
  1342. break;
  1343. seq_printf(m, " SDMA Engine %d, RLC %d\n",
  1344. pipe, queue);
  1345. seq_reg_dump(m, dump, n_regs);
  1346. kfree(dump);
  1347. }
  1348. }
  1349. return r;
  1350. }
  1351. #endif