dce_v11_0.c 114 KB

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  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <drm/drmP.h>
  24. #include "amdgpu.h"
  25. #include "amdgpu_pm.h"
  26. #include "amdgpu_i2c.h"
  27. #include "vid.h"
  28. #include "atom.h"
  29. #include "amdgpu_atombios.h"
  30. #include "atombios_crtc.h"
  31. #include "atombios_encoders.h"
  32. #include "amdgpu_pll.h"
  33. #include "amdgpu_connectors.h"
  34. #include "dce_v11_0.h"
  35. #include "dce/dce_11_0_d.h"
  36. #include "dce/dce_11_0_sh_mask.h"
  37. #include "dce/dce_11_0_enum.h"
  38. #include "oss/oss_3_0_d.h"
  39. #include "oss/oss_3_0_sh_mask.h"
  40. #include "gmc/gmc_8_1_d.h"
  41. #include "gmc/gmc_8_1_sh_mask.h"
  42. static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
  43. static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
  44. static const u32 crtc_offsets[] =
  45. {
  46. CRTC0_REGISTER_OFFSET,
  47. CRTC1_REGISTER_OFFSET,
  48. CRTC2_REGISTER_OFFSET,
  49. CRTC3_REGISTER_OFFSET,
  50. CRTC4_REGISTER_OFFSET,
  51. CRTC5_REGISTER_OFFSET,
  52. CRTC6_REGISTER_OFFSET
  53. };
  54. static const u32 hpd_offsets[] =
  55. {
  56. HPD0_REGISTER_OFFSET,
  57. HPD1_REGISTER_OFFSET,
  58. HPD2_REGISTER_OFFSET,
  59. HPD3_REGISTER_OFFSET,
  60. HPD4_REGISTER_OFFSET,
  61. HPD5_REGISTER_OFFSET
  62. };
  63. static const uint32_t dig_offsets[] = {
  64. DIG0_REGISTER_OFFSET,
  65. DIG1_REGISTER_OFFSET,
  66. DIG2_REGISTER_OFFSET,
  67. DIG3_REGISTER_OFFSET,
  68. DIG4_REGISTER_OFFSET,
  69. DIG5_REGISTER_OFFSET,
  70. DIG6_REGISTER_OFFSET,
  71. DIG7_REGISTER_OFFSET,
  72. DIG8_REGISTER_OFFSET
  73. };
  74. static const struct {
  75. uint32_t reg;
  76. uint32_t vblank;
  77. uint32_t vline;
  78. uint32_t hpd;
  79. } interrupt_status_offsets[] = { {
  80. .reg = mmDISP_INTERRUPT_STATUS,
  81. .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
  82. .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
  83. .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
  84. }, {
  85. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
  86. .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
  87. .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
  88. .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
  89. }, {
  90. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
  91. .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
  92. .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
  93. .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
  94. }, {
  95. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
  96. .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
  97. .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
  98. .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
  99. }, {
  100. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
  101. .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
  102. .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
  103. .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
  104. }, {
  105. .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
  106. .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
  107. .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
  108. .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
  109. } };
  110. static const u32 cz_golden_settings_a11[] =
  111. {
  112. mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
  113. mmFBC_MISC, 0x1f311fff, 0x14300000,
  114. };
  115. static const u32 cz_mgcg_cgcg_init[] =
  116. {
  117. mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
  118. mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
  119. };
  120. static const u32 stoney_golden_settings_a11[] =
  121. {
  122. mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
  123. mmFBC_MISC, 0x1f311fff, 0x14302000,
  124. };
  125. static const u32 polaris11_golden_settings_a11[] =
  126. {
  127. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  128. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  129. mmFBC_DEBUG1, 0xffffffff, 0x00000008,
  130. mmFBC_MISC, 0x9f313fff, 0x14302008,
  131. mmHDMI_CONTROL, 0x313f031f, 0x00000011,
  132. };
  133. static const u32 polaris10_golden_settings_a11[] =
  134. {
  135. mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
  136. mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
  137. mmFBC_MISC, 0x9f313fff, 0x14302008,
  138. mmHDMI_CONTROL, 0x313f031f, 0x00000011,
  139. };
  140. static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
  141. {
  142. switch (adev->asic_type) {
  143. case CHIP_CARRIZO:
  144. amdgpu_device_program_register_sequence(adev,
  145. cz_mgcg_cgcg_init,
  146. ARRAY_SIZE(cz_mgcg_cgcg_init));
  147. amdgpu_device_program_register_sequence(adev,
  148. cz_golden_settings_a11,
  149. ARRAY_SIZE(cz_golden_settings_a11));
  150. break;
  151. case CHIP_STONEY:
  152. amdgpu_device_program_register_sequence(adev,
  153. stoney_golden_settings_a11,
  154. ARRAY_SIZE(stoney_golden_settings_a11));
  155. break;
  156. case CHIP_POLARIS11:
  157. case CHIP_POLARIS12:
  158. amdgpu_device_program_register_sequence(adev,
  159. polaris11_golden_settings_a11,
  160. ARRAY_SIZE(polaris11_golden_settings_a11));
  161. break;
  162. case CHIP_POLARIS10:
  163. amdgpu_device_program_register_sequence(adev,
  164. polaris10_golden_settings_a11,
  165. ARRAY_SIZE(polaris10_golden_settings_a11));
  166. break;
  167. default:
  168. break;
  169. }
  170. }
  171. static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
  172. u32 block_offset, u32 reg)
  173. {
  174. unsigned long flags;
  175. u32 r;
  176. spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
  177. WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  178. r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
  179. spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
  180. return r;
  181. }
  182. static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
  183. u32 block_offset, u32 reg, u32 v)
  184. {
  185. unsigned long flags;
  186. spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
  187. WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  188. WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
  189. spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
  190. }
  191. static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  192. {
  193. if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
  194. return 0;
  195. else
  196. return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
  197. }
  198. static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
  199. {
  200. unsigned i;
  201. /* Enable pflip interrupts */
  202. for (i = 0; i < adev->mode_info.num_crtc; i++)
  203. amdgpu_irq_get(adev, &adev->pageflip_irq, i);
  204. }
  205. static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  206. {
  207. unsigned i;
  208. /* Disable pflip interrupts */
  209. for (i = 0; i < adev->mode_info.num_crtc; i++)
  210. amdgpu_irq_put(adev, &adev->pageflip_irq, i);
  211. }
  212. /**
  213. * dce_v11_0_page_flip - pageflip callback.
  214. *
  215. * @adev: amdgpu_device pointer
  216. * @crtc_id: crtc to cleanup pageflip on
  217. * @crtc_base: new address of the crtc (GPU MC address)
  218. *
  219. * Triggers the actual pageflip by updating the primary
  220. * surface base address.
  221. */
  222. static void dce_v11_0_page_flip(struct amdgpu_device *adev,
  223. int crtc_id, u64 crtc_base, bool async)
  224. {
  225. struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
  226. u32 tmp;
  227. /* flip immediate for async, default is vsync */
  228. tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
  229. tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
  230. GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
  231. WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  232. /* update the scanout addresses */
  233. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  234. upper_32_bits(crtc_base));
  235. /* writing to the low address triggers the update */
  236. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  237. lower_32_bits(crtc_base));
  238. /* post the write */
  239. RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
  240. }
  241. static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  242. u32 *vbl, u32 *position)
  243. {
  244. if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
  245. return -EINVAL;
  246. *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
  247. *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
  248. return 0;
  249. }
  250. /**
  251. * dce_v11_0_hpd_sense - hpd sense callback.
  252. *
  253. * @adev: amdgpu_device pointer
  254. * @hpd: hpd (hotplug detect) pin
  255. *
  256. * Checks if a digital monitor is connected (evergreen+).
  257. * Returns true if connected, false if not connected.
  258. */
  259. static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
  260. enum amdgpu_hpd_id hpd)
  261. {
  262. bool connected = false;
  263. if (hpd >= adev->mode_info.num_hpd)
  264. return connected;
  265. if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
  266. DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
  267. connected = true;
  268. return connected;
  269. }
  270. /**
  271. * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
  272. *
  273. * @adev: amdgpu_device pointer
  274. * @hpd: hpd (hotplug detect) pin
  275. *
  276. * Set the polarity of the hpd pin (evergreen+).
  277. */
  278. static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
  279. enum amdgpu_hpd_id hpd)
  280. {
  281. u32 tmp;
  282. bool connected = dce_v11_0_hpd_sense(adev, hpd);
  283. if (hpd >= adev->mode_info.num_hpd)
  284. return;
  285. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  286. if (connected)
  287. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
  288. else
  289. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
  290. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  291. }
  292. /**
  293. * dce_v11_0_hpd_init - hpd setup callback.
  294. *
  295. * @adev: amdgpu_device pointer
  296. *
  297. * Setup the hpd pins used by the card (evergreen+).
  298. * Enable the pin, set the polarity, and enable the hpd interrupts.
  299. */
  300. static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
  301. {
  302. struct drm_device *dev = adev->ddev;
  303. struct drm_connector *connector;
  304. u32 tmp;
  305. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  306. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  307. if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
  308. continue;
  309. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
  310. connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
  311. /* don't try to enable hpd on eDP or LVDS avoid breaking the
  312. * aux dp channel on imac and help (but not completely fix)
  313. * https://bugzilla.redhat.com/show_bug.cgi?id=726143
  314. * also avoid interrupt storms during dpms.
  315. */
  316. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  317. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
  318. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  319. continue;
  320. }
  321. tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  322. tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
  323. WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  324. tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  325. tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
  326. DC_HPD_CONNECT_INT_DELAY,
  327. AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
  328. tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
  329. DC_HPD_DISCONNECT_INT_DELAY,
  330. AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
  331. WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  332. dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
  333. amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
  334. }
  335. }
  336. /**
  337. * dce_v11_0_hpd_fini - hpd tear down callback.
  338. *
  339. * @adev: amdgpu_device pointer
  340. *
  341. * Tear down the hpd pins used by the card (evergreen+).
  342. * Disable the hpd interrupts.
  343. */
  344. static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
  345. {
  346. struct drm_device *dev = adev->ddev;
  347. struct drm_connector *connector;
  348. u32 tmp;
  349. list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
  350. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  351. if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
  352. continue;
  353. tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
  354. tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
  355. WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
  356. amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
  357. }
  358. }
  359. static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
  360. {
  361. return mmDC_GPIO_HPD_A;
  362. }
  363. static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
  364. {
  365. u32 crtc_hung = 0;
  366. u32 crtc_status[6];
  367. u32 i, j, tmp;
  368. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  369. tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
  370. if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
  371. crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
  372. crtc_hung |= (1 << i);
  373. }
  374. }
  375. for (j = 0; j < 10; j++) {
  376. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  377. if (crtc_hung & (1 << i)) {
  378. tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
  379. if (tmp != crtc_status[i])
  380. crtc_hung &= ~(1 << i);
  381. }
  382. }
  383. if (crtc_hung == 0)
  384. return false;
  385. udelay(100);
  386. }
  387. return true;
  388. }
  389. static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
  390. bool render)
  391. {
  392. u32 tmp;
  393. /* Lockout access through VGA aperture*/
  394. tmp = RREG32(mmVGA_HDP_CONTROL);
  395. if (render)
  396. tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
  397. else
  398. tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
  399. WREG32(mmVGA_HDP_CONTROL, tmp);
  400. /* disable VGA render */
  401. tmp = RREG32(mmVGA_RENDER_CONTROL);
  402. if (render)
  403. tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
  404. else
  405. tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
  406. WREG32(mmVGA_RENDER_CONTROL, tmp);
  407. }
  408. static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
  409. {
  410. int num_crtc = 0;
  411. switch (adev->asic_type) {
  412. case CHIP_CARRIZO:
  413. num_crtc = 3;
  414. break;
  415. case CHIP_STONEY:
  416. num_crtc = 2;
  417. break;
  418. case CHIP_POLARIS10:
  419. num_crtc = 6;
  420. break;
  421. case CHIP_POLARIS11:
  422. case CHIP_POLARIS12:
  423. num_crtc = 5;
  424. break;
  425. default:
  426. num_crtc = 0;
  427. }
  428. return num_crtc;
  429. }
  430. void dce_v11_0_disable_dce(struct amdgpu_device *adev)
  431. {
  432. /*Disable VGA render and enabled crtc, if has DCE engine*/
  433. if (amdgpu_atombios_has_dce_engine_info(adev)) {
  434. u32 tmp;
  435. int crtc_enabled, i;
  436. dce_v11_0_set_vga_render_state(adev, false);
  437. /*Disable crtc*/
  438. for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
  439. crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
  440. CRTC_CONTROL, CRTC_MASTER_EN);
  441. if (crtc_enabled) {
  442. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
  443. tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
  444. tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
  445. WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
  446. WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
  447. }
  448. }
  449. }
  450. }
  451. static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
  452. {
  453. struct drm_device *dev = encoder->dev;
  454. struct amdgpu_device *adev = dev->dev_private;
  455. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  456. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
  457. struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
  458. int bpc = 0;
  459. u32 tmp = 0;
  460. enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
  461. if (connector) {
  462. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  463. bpc = amdgpu_connector_get_monitor_bpc(connector);
  464. dither = amdgpu_connector->dither;
  465. }
  466. /* LVDS/eDP FMT is set up by atom */
  467. if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
  468. return;
  469. /* not needed for analog */
  470. if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
  471. (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
  472. return;
  473. if (bpc == 0)
  474. return;
  475. switch (bpc) {
  476. case 6:
  477. if (dither == AMDGPU_FMT_DITHER_ENABLE) {
  478. /* XXX sort out optimal dither settings */
  479. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
  480. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
  481. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
  482. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
  483. } else {
  484. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
  485. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
  486. }
  487. break;
  488. case 8:
  489. if (dither == AMDGPU_FMT_DITHER_ENABLE) {
  490. /* XXX sort out optimal dither settings */
  491. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
  492. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
  493. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
  494. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
  495. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
  496. } else {
  497. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
  498. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
  499. }
  500. break;
  501. case 10:
  502. if (dither == AMDGPU_FMT_DITHER_ENABLE) {
  503. /* XXX sort out optimal dither settings */
  504. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
  505. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
  506. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
  507. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
  508. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
  509. } else {
  510. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
  511. tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
  512. }
  513. break;
  514. default:
  515. /* not needed */
  516. break;
  517. }
  518. WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  519. }
  520. /* display watermark setup */
  521. /**
  522. * dce_v11_0_line_buffer_adjust - Set up the line buffer
  523. *
  524. * @adev: amdgpu_device pointer
  525. * @amdgpu_crtc: the selected display controller
  526. * @mode: the current display mode on the selected display
  527. * controller
  528. *
  529. * Setup up the line buffer allocation for
  530. * the selected display controller (CIK).
  531. * Returns the line buffer size in pixels.
  532. */
  533. static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
  534. struct amdgpu_crtc *amdgpu_crtc,
  535. struct drm_display_mode *mode)
  536. {
  537. u32 tmp, buffer_alloc, i, mem_cfg;
  538. u32 pipe_offset = amdgpu_crtc->crtc_id;
  539. /*
  540. * Line Buffer Setup
  541. * There are 6 line buffers, one for each display controllers.
  542. * There are 3 partitions per LB. Select the number of partitions
  543. * to enable based on the display width. For display widths larger
  544. * than 4096, you need use to use 2 display controllers and combine
  545. * them using the stereo blender.
  546. */
  547. if (amdgpu_crtc->base.enabled && mode) {
  548. if (mode->crtc_hdisplay < 1920) {
  549. mem_cfg = 1;
  550. buffer_alloc = 2;
  551. } else if (mode->crtc_hdisplay < 2560) {
  552. mem_cfg = 2;
  553. buffer_alloc = 2;
  554. } else if (mode->crtc_hdisplay < 4096) {
  555. mem_cfg = 0;
  556. buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
  557. } else {
  558. DRM_DEBUG_KMS("Mode too big for LB!\n");
  559. mem_cfg = 0;
  560. buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
  561. }
  562. } else {
  563. mem_cfg = 1;
  564. buffer_alloc = 0;
  565. }
  566. tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
  567. tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
  568. WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
  569. tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
  570. tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
  571. WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
  572. for (i = 0; i < adev->usec_timeout; i++) {
  573. tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
  574. if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
  575. break;
  576. udelay(1);
  577. }
  578. if (amdgpu_crtc->base.enabled && mode) {
  579. switch (mem_cfg) {
  580. case 0:
  581. default:
  582. return 4096 * 2;
  583. case 1:
  584. return 1920 * 2;
  585. case 2:
  586. return 2560 * 2;
  587. }
  588. }
  589. /* controller not enabled, so no lb used */
  590. return 0;
  591. }
  592. /**
  593. * cik_get_number_of_dram_channels - get the number of dram channels
  594. *
  595. * @adev: amdgpu_device pointer
  596. *
  597. * Look up the number of video ram channels (CIK).
  598. * Used for display watermark bandwidth calculations
  599. * Returns the number of dram channels
  600. */
  601. static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
  602. {
  603. u32 tmp = RREG32(mmMC_SHARED_CHMAP);
  604. switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
  605. case 0:
  606. default:
  607. return 1;
  608. case 1:
  609. return 2;
  610. case 2:
  611. return 4;
  612. case 3:
  613. return 8;
  614. case 4:
  615. return 3;
  616. case 5:
  617. return 6;
  618. case 6:
  619. return 10;
  620. case 7:
  621. return 12;
  622. case 8:
  623. return 16;
  624. }
  625. }
  626. struct dce10_wm_params {
  627. u32 dram_channels; /* number of dram channels */
  628. u32 yclk; /* bandwidth per dram data pin in kHz */
  629. u32 sclk; /* engine clock in kHz */
  630. u32 disp_clk; /* display clock in kHz */
  631. u32 src_width; /* viewport width */
  632. u32 active_time; /* active display time in ns */
  633. u32 blank_time; /* blank time in ns */
  634. bool interlaced; /* mode is interlaced */
  635. fixed20_12 vsc; /* vertical scale ratio */
  636. u32 num_heads; /* number of active crtcs */
  637. u32 bytes_per_pixel; /* bytes per pixel display + overlay */
  638. u32 lb_size; /* line buffer allocated to pipe */
  639. u32 vtaps; /* vertical scaler taps */
  640. };
  641. /**
  642. * dce_v11_0_dram_bandwidth - get the dram bandwidth
  643. *
  644. * @wm: watermark calculation data
  645. *
  646. * Calculate the raw dram bandwidth (CIK).
  647. * Used for display watermark bandwidth calculations
  648. * Returns the dram bandwidth in MBytes/s
  649. */
  650. static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
  651. {
  652. /* Calculate raw DRAM Bandwidth */
  653. fixed20_12 dram_efficiency; /* 0.7 */
  654. fixed20_12 yclk, dram_channels, bandwidth;
  655. fixed20_12 a;
  656. a.full = dfixed_const(1000);
  657. yclk.full = dfixed_const(wm->yclk);
  658. yclk.full = dfixed_div(yclk, a);
  659. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  660. a.full = dfixed_const(10);
  661. dram_efficiency.full = dfixed_const(7);
  662. dram_efficiency.full = dfixed_div(dram_efficiency, a);
  663. bandwidth.full = dfixed_mul(dram_channels, yclk);
  664. bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
  665. return dfixed_trunc(bandwidth);
  666. }
  667. /**
  668. * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
  669. *
  670. * @wm: watermark calculation data
  671. *
  672. * Calculate the dram bandwidth used for display (CIK).
  673. * Used for display watermark bandwidth calculations
  674. * Returns the dram bandwidth for display in MBytes/s
  675. */
  676. static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
  677. {
  678. /* Calculate DRAM Bandwidth and the part allocated to display. */
  679. fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
  680. fixed20_12 yclk, dram_channels, bandwidth;
  681. fixed20_12 a;
  682. a.full = dfixed_const(1000);
  683. yclk.full = dfixed_const(wm->yclk);
  684. yclk.full = dfixed_div(yclk, a);
  685. dram_channels.full = dfixed_const(wm->dram_channels * 4);
  686. a.full = dfixed_const(10);
  687. disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
  688. disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
  689. bandwidth.full = dfixed_mul(dram_channels, yclk);
  690. bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
  691. return dfixed_trunc(bandwidth);
  692. }
  693. /**
  694. * dce_v11_0_data_return_bandwidth - get the data return bandwidth
  695. *
  696. * @wm: watermark calculation data
  697. *
  698. * Calculate the data return bandwidth used for display (CIK).
  699. * Used for display watermark bandwidth calculations
  700. * Returns the data return bandwidth in MBytes/s
  701. */
  702. static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
  703. {
  704. /* Calculate the display Data return Bandwidth */
  705. fixed20_12 return_efficiency; /* 0.8 */
  706. fixed20_12 sclk, bandwidth;
  707. fixed20_12 a;
  708. a.full = dfixed_const(1000);
  709. sclk.full = dfixed_const(wm->sclk);
  710. sclk.full = dfixed_div(sclk, a);
  711. a.full = dfixed_const(10);
  712. return_efficiency.full = dfixed_const(8);
  713. return_efficiency.full = dfixed_div(return_efficiency, a);
  714. a.full = dfixed_const(32);
  715. bandwidth.full = dfixed_mul(a, sclk);
  716. bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
  717. return dfixed_trunc(bandwidth);
  718. }
  719. /**
  720. * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
  721. *
  722. * @wm: watermark calculation data
  723. *
  724. * Calculate the dmif bandwidth used for display (CIK).
  725. * Used for display watermark bandwidth calculations
  726. * Returns the dmif bandwidth in MBytes/s
  727. */
  728. static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
  729. {
  730. /* Calculate the DMIF Request Bandwidth */
  731. fixed20_12 disp_clk_request_efficiency; /* 0.8 */
  732. fixed20_12 disp_clk, bandwidth;
  733. fixed20_12 a, b;
  734. a.full = dfixed_const(1000);
  735. disp_clk.full = dfixed_const(wm->disp_clk);
  736. disp_clk.full = dfixed_div(disp_clk, a);
  737. a.full = dfixed_const(32);
  738. b.full = dfixed_mul(a, disp_clk);
  739. a.full = dfixed_const(10);
  740. disp_clk_request_efficiency.full = dfixed_const(8);
  741. disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
  742. bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
  743. return dfixed_trunc(bandwidth);
  744. }
  745. /**
  746. * dce_v11_0_available_bandwidth - get the min available bandwidth
  747. *
  748. * @wm: watermark calculation data
  749. *
  750. * Calculate the min available bandwidth used for display (CIK).
  751. * Used for display watermark bandwidth calculations
  752. * Returns the min available bandwidth in MBytes/s
  753. */
  754. static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
  755. {
  756. /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
  757. u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
  758. u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
  759. u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
  760. return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
  761. }
  762. /**
  763. * dce_v11_0_average_bandwidth - get the average available bandwidth
  764. *
  765. * @wm: watermark calculation data
  766. *
  767. * Calculate the average available bandwidth used for display (CIK).
  768. * Used for display watermark bandwidth calculations
  769. * Returns the average available bandwidth in MBytes/s
  770. */
  771. static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
  772. {
  773. /* Calculate the display mode Average Bandwidth
  774. * DisplayMode should contain the source and destination dimensions,
  775. * timing, etc.
  776. */
  777. fixed20_12 bpp;
  778. fixed20_12 line_time;
  779. fixed20_12 src_width;
  780. fixed20_12 bandwidth;
  781. fixed20_12 a;
  782. a.full = dfixed_const(1000);
  783. line_time.full = dfixed_const(wm->active_time + wm->blank_time);
  784. line_time.full = dfixed_div(line_time, a);
  785. bpp.full = dfixed_const(wm->bytes_per_pixel);
  786. src_width.full = dfixed_const(wm->src_width);
  787. bandwidth.full = dfixed_mul(src_width, bpp);
  788. bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
  789. bandwidth.full = dfixed_div(bandwidth, line_time);
  790. return dfixed_trunc(bandwidth);
  791. }
  792. /**
  793. * dce_v11_0_latency_watermark - get the latency watermark
  794. *
  795. * @wm: watermark calculation data
  796. *
  797. * Calculate the latency watermark (CIK).
  798. * Used for display watermark bandwidth calculations
  799. * Returns the latency watermark in ns
  800. */
  801. static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
  802. {
  803. /* First calculate the latency in ns */
  804. u32 mc_latency = 2000; /* 2000 ns. */
  805. u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
  806. u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
  807. u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
  808. u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
  809. u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
  810. (wm->num_heads * cursor_line_pair_return_time);
  811. u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
  812. u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
  813. u32 tmp, dmif_size = 12288;
  814. fixed20_12 a, b, c;
  815. if (wm->num_heads == 0)
  816. return 0;
  817. a.full = dfixed_const(2);
  818. b.full = dfixed_const(1);
  819. if ((wm->vsc.full > a.full) ||
  820. ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
  821. (wm->vtaps >= 5) ||
  822. ((wm->vsc.full >= a.full) && wm->interlaced))
  823. max_src_lines_per_dst_line = 4;
  824. else
  825. max_src_lines_per_dst_line = 2;
  826. a.full = dfixed_const(available_bandwidth);
  827. b.full = dfixed_const(wm->num_heads);
  828. a.full = dfixed_div(a, b);
  829. tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
  830. tmp = min(dfixed_trunc(a), tmp);
  831. lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
  832. a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
  833. b.full = dfixed_const(1000);
  834. c.full = dfixed_const(lb_fill_bw);
  835. b.full = dfixed_div(c, b);
  836. a.full = dfixed_div(a, b);
  837. line_fill_time = dfixed_trunc(a);
  838. if (line_fill_time < wm->active_time)
  839. return latency;
  840. else
  841. return latency + (line_fill_time - wm->active_time);
  842. }
  843. /**
  844. * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
  845. * average and available dram bandwidth
  846. *
  847. * @wm: watermark calculation data
  848. *
  849. * Check if the display average bandwidth fits in the display
  850. * dram bandwidth (CIK).
  851. * Used for display watermark bandwidth calculations
  852. * Returns true if the display fits, false if not.
  853. */
  854. static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
  855. {
  856. if (dce_v11_0_average_bandwidth(wm) <=
  857. (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
  858. return true;
  859. else
  860. return false;
  861. }
  862. /**
  863. * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
  864. * average and available bandwidth
  865. *
  866. * @wm: watermark calculation data
  867. *
  868. * Check if the display average bandwidth fits in the display
  869. * available bandwidth (CIK).
  870. * Used for display watermark bandwidth calculations
  871. * Returns true if the display fits, false if not.
  872. */
  873. static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
  874. {
  875. if (dce_v11_0_average_bandwidth(wm) <=
  876. (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
  877. return true;
  878. else
  879. return false;
  880. }
  881. /**
  882. * dce_v11_0_check_latency_hiding - check latency hiding
  883. *
  884. * @wm: watermark calculation data
  885. *
  886. * Check latency hiding (CIK).
  887. * Used for display watermark bandwidth calculations
  888. * Returns true if the display fits, false if not.
  889. */
  890. static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
  891. {
  892. u32 lb_partitions = wm->lb_size / wm->src_width;
  893. u32 line_time = wm->active_time + wm->blank_time;
  894. u32 latency_tolerant_lines;
  895. u32 latency_hiding;
  896. fixed20_12 a;
  897. a.full = dfixed_const(1);
  898. if (wm->vsc.full > a.full)
  899. latency_tolerant_lines = 1;
  900. else {
  901. if (lb_partitions <= (wm->vtaps + 1))
  902. latency_tolerant_lines = 1;
  903. else
  904. latency_tolerant_lines = 2;
  905. }
  906. latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
  907. if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
  908. return true;
  909. else
  910. return false;
  911. }
  912. /**
  913. * dce_v11_0_program_watermarks - program display watermarks
  914. *
  915. * @adev: amdgpu_device pointer
  916. * @amdgpu_crtc: the selected display controller
  917. * @lb_size: line buffer size
  918. * @num_heads: number of display controllers in use
  919. *
  920. * Calculate and program the display watermarks for the
  921. * selected display controller (CIK).
  922. */
  923. static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
  924. struct amdgpu_crtc *amdgpu_crtc,
  925. u32 lb_size, u32 num_heads)
  926. {
  927. struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
  928. struct dce10_wm_params wm_low, wm_high;
  929. u32 active_time;
  930. u32 line_time = 0;
  931. u32 latency_watermark_a = 0, latency_watermark_b = 0;
  932. u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
  933. if (amdgpu_crtc->base.enabled && num_heads && mode) {
  934. active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
  935. (u32)mode->clock);
  936. line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
  937. (u32)mode->clock);
  938. line_time = min(line_time, (u32)65535);
  939. /* watermark for high clocks */
  940. if (adev->pm.dpm_enabled) {
  941. wm_high.yclk =
  942. amdgpu_dpm_get_mclk(adev, false) * 10;
  943. wm_high.sclk =
  944. amdgpu_dpm_get_sclk(adev, false) * 10;
  945. } else {
  946. wm_high.yclk = adev->pm.current_mclk * 10;
  947. wm_high.sclk = adev->pm.current_sclk * 10;
  948. }
  949. wm_high.disp_clk = mode->clock;
  950. wm_high.src_width = mode->crtc_hdisplay;
  951. wm_high.active_time = active_time;
  952. wm_high.blank_time = line_time - wm_high.active_time;
  953. wm_high.interlaced = false;
  954. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  955. wm_high.interlaced = true;
  956. wm_high.vsc = amdgpu_crtc->vsc;
  957. wm_high.vtaps = 1;
  958. if (amdgpu_crtc->rmx_type != RMX_OFF)
  959. wm_high.vtaps = 2;
  960. wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
  961. wm_high.lb_size = lb_size;
  962. wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
  963. wm_high.num_heads = num_heads;
  964. /* set for high clocks */
  965. latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
  966. /* possibly force display priority to high */
  967. /* should really do this at mode validation time... */
  968. if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
  969. !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
  970. !dce_v11_0_check_latency_hiding(&wm_high) ||
  971. (adev->mode_info.disp_priority == 2)) {
  972. DRM_DEBUG_KMS("force priority to high\n");
  973. }
  974. /* watermark for low clocks */
  975. if (adev->pm.dpm_enabled) {
  976. wm_low.yclk =
  977. amdgpu_dpm_get_mclk(adev, true) * 10;
  978. wm_low.sclk =
  979. amdgpu_dpm_get_sclk(adev, true) * 10;
  980. } else {
  981. wm_low.yclk = adev->pm.current_mclk * 10;
  982. wm_low.sclk = adev->pm.current_sclk * 10;
  983. }
  984. wm_low.disp_clk = mode->clock;
  985. wm_low.src_width = mode->crtc_hdisplay;
  986. wm_low.active_time = active_time;
  987. wm_low.blank_time = line_time - wm_low.active_time;
  988. wm_low.interlaced = false;
  989. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  990. wm_low.interlaced = true;
  991. wm_low.vsc = amdgpu_crtc->vsc;
  992. wm_low.vtaps = 1;
  993. if (amdgpu_crtc->rmx_type != RMX_OFF)
  994. wm_low.vtaps = 2;
  995. wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
  996. wm_low.lb_size = lb_size;
  997. wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
  998. wm_low.num_heads = num_heads;
  999. /* set for low clocks */
  1000. latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
  1001. /* possibly force display priority to high */
  1002. /* should really do this at mode validation time... */
  1003. if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
  1004. !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
  1005. !dce_v11_0_check_latency_hiding(&wm_low) ||
  1006. (adev->mode_info.disp_priority == 2)) {
  1007. DRM_DEBUG_KMS("force priority to high\n");
  1008. }
  1009. lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
  1010. }
  1011. /* select wm A */
  1012. wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
  1013. tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
  1014. WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1015. tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
  1016. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
  1017. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
  1018. WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1019. /* select wm B */
  1020. tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
  1021. WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1022. tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
  1023. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
  1024. tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
  1025. WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1026. /* restore original selection */
  1027. WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
  1028. /* save values for DPM */
  1029. amdgpu_crtc->line_time = line_time;
  1030. amdgpu_crtc->wm_high = latency_watermark_a;
  1031. amdgpu_crtc->wm_low = latency_watermark_b;
  1032. /* Save number of lines the linebuffer leads before the scanout */
  1033. amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
  1034. }
  1035. /**
  1036. * dce_v11_0_bandwidth_update - program display watermarks
  1037. *
  1038. * @adev: amdgpu_device pointer
  1039. *
  1040. * Calculate and program the display watermarks and line
  1041. * buffer allocation (CIK).
  1042. */
  1043. static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
  1044. {
  1045. struct drm_display_mode *mode = NULL;
  1046. u32 num_heads = 0, lb_size;
  1047. int i;
  1048. amdgpu_display_update_priority(adev);
  1049. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  1050. if (adev->mode_info.crtcs[i]->base.enabled)
  1051. num_heads++;
  1052. }
  1053. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  1054. mode = &adev->mode_info.crtcs[i]->base.mode;
  1055. lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
  1056. dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
  1057. lb_size, num_heads);
  1058. }
  1059. }
  1060. static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
  1061. {
  1062. int i;
  1063. u32 offset, tmp;
  1064. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  1065. offset = adev->mode_info.audio.pin[i].offset;
  1066. tmp = RREG32_AUDIO_ENDPT(offset,
  1067. ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
  1068. if (((tmp &
  1069. AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
  1070. AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
  1071. adev->mode_info.audio.pin[i].connected = false;
  1072. else
  1073. adev->mode_info.audio.pin[i].connected = true;
  1074. }
  1075. }
  1076. static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
  1077. {
  1078. int i;
  1079. dce_v11_0_audio_get_connected_pins(adev);
  1080. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  1081. if (adev->mode_info.audio.pin[i].connected)
  1082. return &adev->mode_info.audio.pin[i];
  1083. }
  1084. DRM_ERROR("No connected audio pins found!\n");
  1085. return NULL;
  1086. }
  1087. static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
  1088. {
  1089. struct amdgpu_device *adev = encoder->dev->dev_private;
  1090. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1091. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1092. u32 tmp;
  1093. if (!dig || !dig->afmt || !dig->afmt->pin)
  1094. return;
  1095. tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
  1096. tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
  1097. WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
  1098. }
  1099. static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
  1100. struct drm_display_mode *mode)
  1101. {
  1102. struct amdgpu_device *adev = encoder->dev->dev_private;
  1103. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1104. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1105. struct drm_connector *connector;
  1106. struct amdgpu_connector *amdgpu_connector = NULL;
  1107. u32 tmp;
  1108. int interlace = 0;
  1109. if (!dig || !dig->afmt || !dig->afmt->pin)
  1110. return;
  1111. list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  1112. if (connector->encoder == encoder) {
  1113. amdgpu_connector = to_amdgpu_connector(connector);
  1114. break;
  1115. }
  1116. }
  1117. if (!amdgpu_connector) {
  1118. DRM_ERROR("Couldn't find encoder's connector\n");
  1119. return;
  1120. }
  1121. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1122. interlace = 1;
  1123. if (connector->latency_present[interlace]) {
  1124. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1125. VIDEO_LIPSYNC, connector->video_latency[interlace]);
  1126. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1127. AUDIO_LIPSYNC, connector->audio_latency[interlace]);
  1128. } else {
  1129. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1130. VIDEO_LIPSYNC, 0);
  1131. tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
  1132. AUDIO_LIPSYNC, 0);
  1133. }
  1134. WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
  1135. ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
  1136. }
  1137. static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
  1138. {
  1139. struct amdgpu_device *adev = encoder->dev->dev_private;
  1140. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1141. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1142. struct drm_connector *connector;
  1143. struct amdgpu_connector *amdgpu_connector = NULL;
  1144. u32 tmp;
  1145. u8 *sadb = NULL;
  1146. int sad_count;
  1147. if (!dig || !dig->afmt || !dig->afmt->pin)
  1148. return;
  1149. list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  1150. if (connector->encoder == encoder) {
  1151. amdgpu_connector = to_amdgpu_connector(connector);
  1152. break;
  1153. }
  1154. }
  1155. if (!amdgpu_connector) {
  1156. DRM_ERROR("Couldn't find encoder's connector\n");
  1157. return;
  1158. }
  1159. sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
  1160. if (sad_count < 0) {
  1161. DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
  1162. sad_count = 0;
  1163. }
  1164. /* program the speaker allocation */
  1165. tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
  1166. ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
  1167. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1168. DP_CONNECTION, 0);
  1169. /* set HDMI mode */
  1170. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1171. HDMI_CONNECTION, 1);
  1172. if (sad_count)
  1173. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1174. SPEAKER_ALLOCATION, sadb[0]);
  1175. else
  1176. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
  1177. SPEAKER_ALLOCATION, 5); /* stereo */
  1178. WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
  1179. ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
  1180. kfree(sadb);
  1181. }
  1182. static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
  1183. {
  1184. struct amdgpu_device *adev = encoder->dev->dev_private;
  1185. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1186. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1187. struct drm_connector *connector;
  1188. struct amdgpu_connector *amdgpu_connector = NULL;
  1189. struct cea_sad *sads;
  1190. int i, sad_count;
  1191. static const u16 eld_reg_to_type[][2] = {
  1192. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
  1193. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
  1194. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
  1195. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
  1196. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
  1197. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
  1198. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
  1199. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
  1200. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
  1201. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
  1202. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
  1203. { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
  1204. };
  1205. if (!dig || !dig->afmt || !dig->afmt->pin)
  1206. return;
  1207. list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
  1208. if (connector->encoder == encoder) {
  1209. amdgpu_connector = to_amdgpu_connector(connector);
  1210. break;
  1211. }
  1212. }
  1213. if (!amdgpu_connector) {
  1214. DRM_ERROR("Couldn't find encoder's connector\n");
  1215. return;
  1216. }
  1217. sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
  1218. if (sad_count <= 0) {
  1219. DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
  1220. return;
  1221. }
  1222. BUG_ON(!sads);
  1223. for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
  1224. u32 tmp = 0;
  1225. u8 stereo_freqs = 0;
  1226. int max_channels = -1;
  1227. int j;
  1228. for (j = 0; j < sad_count; j++) {
  1229. struct cea_sad *sad = &sads[j];
  1230. if (sad->format == eld_reg_to_type[i][1]) {
  1231. if (sad->channels > max_channels) {
  1232. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1233. MAX_CHANNELS, sad->channels);
  1234. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1235. DESCRIPTOR_BYTE_2, sad->byte2);
  1236. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1237. SUPPORTED_FREQUENCIES, sad->freq);
  1238. max_channels = sad->channels;
  1239. }
  1240. if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
  1241. stereo_freqs |= sad->freq;
  1242. else
  1243. break;
  1244. }
  1245. }
  1246. tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
  1247. SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
  1248. WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
  1249. }
  1250. kfree(sads);
  1251. }
  1252. static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
  1253. struct amdgpu_audio_pin *pin,
  1254. bool enable)
  1255. {
  1256. if (!pin)
  1257. return;
  1258. WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
  1259. enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
  1260. }
  1261. static const u32 pin_offsets[] =
  1262. {
  1263. AUD0_REGISTER_OFFSET,
  1264. AUD1_REGISTER_OFFSET,
  1265. AUD2_REGISTER_OFFSET,
  1266. AUD3_REGISTER_OFFSET,
  1267. AUD4_REGISTER_OFFSET,
  1268. AUD5_REGISTER_OFFSET,
  1269. AUD6_REGISTER_OFFSET,
  1270. AUD7_REGISTER_OFFSET,
  1271. };
  1272. static int dce_v11_0_audio_init(struct amdgpu_device *adev)
  1273. {
  1274. int i;
  1275. if (!amdgpu_audio)
  1276. return 0;
  1277. adev->mode_info.audio.enabled = true;
  1278. switch (adev->asic_type) {
  1279. case CHIP_CARRIZO:
  1280. case CHIP_STONEY:
  1281. adev->mode_info.audio.num_pins = 7;
  1282. break;
  1283. case CHIP_POLARIS10:
  1284. adev->mode_info.audio.num_pins = 8;
  1285. break;
  1286. case CHIP_POLARIS11:
  1287. case CHIP_POLARIS12:
  1288. adev->mode_info.audio.num_pins = 6;
  1289. break;
  1290. default:
  1291. return -EINVAL;
  1292. }
  1293. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  1294. adev->mode_info.audio.pin[i].channels = -1;
  1295. adev->mode_info.audio.pin[i].rate = -1;
  1296. adev->mode_info.audio.pin[i].bits_per_sample = -1;
  1297. adev->mode_info.audio.pin[i].status_bits = 0;
  1298. adev->mode_info.audio.pin[i].category_code = 0;
  1299. adev->mode_info.audio.pin[i].connected = false;
  1300. adev->mode_info.audio.pin[i].offset = pin_offsets[i];
  1301. adev->mode_info.audio.pin[i].id = i;
  1302. /* disable audio. it will be set up later */
  1303. /* XXX remove once we switch to ip funcs */
  1304. dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  1305. }
  1306. return 0;
  1307. }
  1308. static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
  1309. {
  1310. int i;
  1311. if (!amdgpu_audio)
  1312. return;
  1313. if (!adev->mode_info.audio.enabled)
  1314. return;
  1315. for (i = 0; i < adev->mode_info.audio.num_pins; i++)
  1316. dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  1317. adev->mode_info.audio.enabled = false;
  1318. }
  1319. /*
  1320. * update the N and CTS parameters for a given pixel clock rate
  1321. */
  1322. static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  1323. {
  1324. struct drm_device *dev = encoder->dev;
  1325. struct amdgpu_device *adev = dev->dev_private;
  1326. struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
  1327. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1328. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1329. u32 tmp;
  1330. tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
  1331. tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
  1332. WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
  1333. tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
  1334. tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
  1335. WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
  1336. tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
  1337. tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
  1338. WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
  1339. tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
  1340. tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
  1341. WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
  1342. tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
  1343. tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
  1344. WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
  1345. tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
  1346. tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
  1347. WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
  1348. }
  1349. /*
  1350. * build a HDMI Video Info Frame
  1351. */
  1352. static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
  1353. void *buffer, size_t size)
  1354. {
  1355. struct drm_device *dev = encoder->dev;
  1356. struct amdgpu_device *adev = dev->dev_private;
  1357. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1358. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1359. uint8_t *frame = buffer + 3;
  1360. uint8_t *header = buffer;
  1361. WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
  1362. frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
  1363. WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
  1364. frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
  1365. WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
  1366. frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
  1367. WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
  1368. frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
  1369. }
  1370. static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
  1371. {
  1372. struct drm_device *dev = encoder->dev;
  1373. struct amdgpu_device *adev = dev->dev_private;
  1374. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1375. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1376. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
  1377. u32 dto_phase = 24 * 1000;
  1378. u32 dto_modulo = clock;
  1379. u32 tmp;
  1380. if (!dig || !dig->afmt)
  1381. return;
  1382. /* XXX two dtos; generally use dto0 for hdmi */
  1383. /* Express [24MHz / target pixel clock] as an exact rational
  1384. * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
  1385. * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
  1386. */
  1387. tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
  1388. tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
  1389. amdgpu_crtc->crtc_id);
  1390. WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
  1391. WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
  1392. WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
  1393. }
  1394. /*
  1395. * update the info frames with the data from the current display mode
  1396. */
  1397. static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
  1398. struct drm_display_mode *mode)
  1399. {
  1400. struct drm_device *dev = encoder->dev;
  1401. struct amdgpu_device *adev = dev->dev_private;
  1402. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1403. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1404. struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
  1405. u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
  1406. struct hdmi_avi_infoframe frame;
  1407. ssize_t err;
  1408. u32 tmp;
  1409. int bpc = 8;
  1410. if (!dig || !dig->afmt)
  1411. return;
  1412. /* Silent, r600_hdmi_enable will raise WARN for us */
  1413. if (!dig->afmt->enabled)
  1414. return;
  1415. /* hdmi deep color mode general control packets setup, if bpc > 8 */
  1416. if (encoder->crtc) {
  1417. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
  1418. bpc = amdgpu_crtc->bpc;
  1419. }
  1420. /* disable audio prior to setting up hw */
  1421. dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
  1422. dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
  1423. dce_v11_0_audio_set_dto(encoder, mode->clock);
  1424. tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
  1425. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
  1426. WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
  1427. WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
  1428. tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
  1429. switch (bpc) {
  1430. case 0:
  1431. case 6:
  1432. case 8:
  1433. case 16:
  1434. default:
  1435. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
  1436. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
  1437. DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
  1438. connector->name, bpc);
  1439. break;
  1440. case 10:
  1441. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
  1442. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
  1443. DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
  1444. connector->name);
  1445. break;
  1446. case 12:
  1447. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
  1448. tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
  1449. DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
  1450. connector->name);
  1451. break;
  1452. }
  1453. WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
  1454. tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
  1455. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
  1456. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
  1457. tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
  1458. WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
  1459. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
  1460. /* enable audio info frames (frames won't be set until audio is enabled) */
  1461. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
  1462. /* required for audio info values to be updated */
  1463. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
  1464. WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
  1465. tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
  1466. /* required for audio info values to be updated */
  1467. tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
  1468. WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
  1469. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
  1470. /* anything other than 0 */
  1471. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
  1472. WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
  1473. WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
  1474. tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
  1475. /* set the default audio delay */
  1476. tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
  1477. /* should be suffient for all audio modes and small enough for all hblanks */
  1478. tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
  1479. WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
  1480. tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
  1481. /* allow 60958 channel status fields to be updated */
  1482. tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
  1483. WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
  1484. tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
  1485. if (bpc > 8)
  1486. /* clear SW CTS value */
  1487. tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
  1488. else
  1489. /* select SW CTS value */
  1490. tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
  1491. /* allow hw to sent ACR packets when required */
  1492. tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
  1493. WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
  1494. dce_v11_0_afmt_update_ACR(encoder, mode->clock);
  1495. tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
  1496. tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
  1497. WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
  1498. tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
  1499. tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
  1500. WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
  1501. tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
  1502. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
  1503. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
  1504. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
  1505. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
  1506. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
  1507. tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
  1508. WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
  1509. dce_v11_0_audio_write_speaker_allocation(encoder);
  1510. WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
  1511. (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
  1512. dce_v11_0_afmt_audio_select_pin(encoder);
  1513. dce_v11_0_audio_write_sad_regs(encoder);
  1514. dce_v11_0_audio_write_latency_fields(encoder, mode);
  1515. err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
  1516. if (err < 0) {
  1517. DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
  1518. return;
  1519. }
  1520. err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
  1521. if (err < 0) {
  1522. DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
  1523. return;
  1524. }
  1525. dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
  1526. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
  1527. /* enable AVI info frames */
  1528. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
  1529. /* required for audio info values to be updated */
  1530. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
  1531. WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
  1532. tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
  1533. tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
  1534. WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
  1535. tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
  1536. /* send audio packets */
  1537. tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
  1538. WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
  1539. WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
  1540. WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
  1541. WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
  1542. WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
  1543. /* enable audio after to setting up hw */
  1544. dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
  1545. }
  1546. static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
  1547. {
  1548. struct drm_device *dev = encoder->dev;
  1549. struct amdgpu_device *adev = dev->dev_private;
  1550. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1551. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1552. if (!dig || !dig->afmt)
  1553. return;
  1554. /* Silent, r600_hdmi_enable will raise WARN for us */
  1555. if (enable && dig->afmt->enabled)
  1556. return;
  1557. if (!enable && !dig->afmt->enabled)
  1558. return;
  1559. if (!enable && dig->afmt->pin) {
  1560. dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
  1561. dig->afmt->pin = NULL;
  1562. }
  1563. dig->afmt->enabled = enable;
  1564. DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
  1565. enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
  1566. }
  1567. static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
  1568. {
  1569. int i;
  1570. for (i = 0; i < adev->mode_info.num_dig; i++)
  1571. adev->mode_info.afmt[i] = NULL;
  1572. /* DCE11 has audio blocks tied to DIG encoders */
  1573. for (i = 0; i < adev->mode_info.num_dig; i++) {
  1574. adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
  1575. if (adev->mode_info.afmt[i]) {
  1576. adev->mode_info.afmt[i]->offset = dig_offsets[i];
  1577. adev->mode_info.afmt[i]->id = i;
  1578. } else {
  1579. int j;
  1580. for (j = 0; j < i; j++) {
  1581. kfree(adev->mode_info.afmt[j]);
  1582. adev->mode_info.afmt[j] = NULL;
  1583. }
  1584. return -ENOMEM;
  1585. }
  1586. }
  1587. return 0;
  1588. }
  1589. static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
  1590. {
  1591. int i;
  1592. for (i = 0; i < adev->mode_info.num_dig; i++) {
  1593. kfree(adev->mode_info.afmt[i]);
  1594. adev->mode_info.afmt[i] = NULL;
  1595. }
  1596. }
  1597. static const u32 vga_control_regs[6] =
  1598. {
  1599. mmD1VGA_CONTROL,
  1600. mmD2VGA_CONTROL,
  1601. mmD3VGA_CONTROL,
  1602. mmD4VGA_CONTROL,
  1603. mmD5VGA_CONTROL,
  1604. mmD6VGA_CONTROL,
  1605. };
  1606. static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
  1607. {
  1608. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1609. struct drm_device *dev = crtc->dev;
  1610. struct amdgpu_device *adev = dev->dev_private;
  1611. u32 vga_control;
  1612. vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
  1613. if (enable)
  1614. WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
  1615. else
  1616. WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
  1617. }
  1618. static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
  1619. {
  1620. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1621. struct drm_device *dev = crtc->dev;
  1622. struct amdgpu_device *adev = dev->dev_private;
  1623. if (enable)
  1624. WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
  1625. else
  1626. WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
  1627. }
  1628. static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
  1629. struct drm_framebuffer *fb,
  1630. int x, int y, int atomic)
  1631. {
  1632. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1633. struct drm_device *dev = crtc->dev;
  1634. struct amdgpu_device *adev = dev->dev_private;
  1635. struct amdgpu_framebuffer *amdgpu_fb;
  1636. struct drm_framebuffer *target_fb;
  1637. struct drm_gem_object *obj;
  1638. struct amdgpu_bo *abo;
  1639. uint64_t fb_location, tiling_flags;
  1640. uint32_t fb_format, fb_pitch_pixels;
  1641. u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
  1642. u32 pipe_config;
  1643. u32 tmp, viewport_w, viewport_h;
  1644. int r;
  1645. bool bypass_lut = false;
  1646. struct drm_format_name_buf format_name;
  1647. /* no fb bound */
  1648. if (!atomic && !crtc->primary->fb) {
  1649. DRM_DEBUG_KMS("No FB bound\n");
  1650. return 0;
  1651. }
  1652. if (atomic) {
  1653. amdgpu_fb = to_amdgpu_framebuffer(fb);
  1654. target_fb = fb;
  1655. } else {
  1656. amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
  1657. target_fb = crtc->primary->fb;
  1658. }
  1659. /* If atomic, assume fb object is pinned & idle & fenced and
  1660. * just update base pointers
  1661. */
  1662. obj = amdgpu_fb->obj;
  1663. abo = gem_to_amdgpu_bo(obj);
  1664. r = amdgpu_bo_reserve(abo, false);
  1665. if (unlikely(r != 0))
  1666. return r;
  1667. if (atomic) {
  1668. fb_location = amdgpu_bo_gpu_offset(abo);
  1669. } else {
  1670. r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
  1671. if (unlikely(r != 0)) {
  1672. amdgpu_bo_unreserve(abo);
  1673. return -EINVAL;
  1674. }
  1675. }
  1676. amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
  1677. amdgpu_bo_unreserve(abo);
  1678. pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
  1679. switch (target_fb->format->format) {
  1680. case DRM_FORMAT_C8:
  1681. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
  1682. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
  1683. break;
  1684. case DRM_FORMAT_XRGB4444:
  1685. case DRM_FORMAT_ARGB4444:
  1686. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1687. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
  1688. #ifdef __BIG_ENDIAN
  1689. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1690. ENDIAN_8IN16);
  1691. #endif
  1692. break;
  1693. case DRM_FORMAT_XRGB1555:
  1694. case DRM_FORMAT_ARGB1555:
  1695. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1696. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
  1697. #ifdef __BIG_ENDIAN
  1698. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1699. ENDIAN_8IN16);
  1700. #endif
  1701. break;
  1702. case DRM_FORMAT_BGRX5551:
  1703. case DRM_FORMAT_BGRA5551:
  1704. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1705. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
  1706. #ifdef __BIG_ENDIAN
  1707. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1708. ENDIAN_8IN16);
  1709. #endif
  1710. break;
  1711. case DRM_FORMAT_RGB565:
  1712. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
  1713. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
  1714. #ifdef __BIG_ENDIAN
  1715. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1716. ENDIAN_8IN16);
  1717. #endif
  1718. break;
  1719. case DRM_FORMAT_XRGB8888:
  1720. case DRM_FORMAT_ARGB8888:
  1721. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
  1722. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
  1723. #ifdef __BIG_ENDIAN
  1724. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1725. ENDIAN_8IN32);
  1726. #endif
  1727. break;
  1728. case DRM_FORMAT_XRGB2101010:
  1729. case DRM_FORMAT_ARGB2101010:
  1730. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
  1731. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
  1732. #ifdef __BIG_ENDIAN
  1733. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1734. ENDIAN_8IN32);
  1735. #endif
  1736. /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
  1737. bypass_lut = true;
  1738. break;
  1739. case DRM_FORMAT_BGRX1010102:
  1740. case DRM_FORMAT_BGRA1010102:
  1741. fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
  1742. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
  1743. #ifdef __BIG_ENDIAN
  1744. fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
  1745. ENDIAN_8IN32);
  1746. #endif
  1747. /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
  1748. bypass_lut = true;
  1749. break;
  1750. default:
  1751. DRM_ERROR("Unsupported screen format %s\n",
  1752. drm_get_format_name(target_fb->format->format, &format_name));
  1753. return -EINVAL;
  1754. }
  1755. if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
  1756. unsigned bankw, bankh, mtaspect, tile_split, num_banks;
  1757. bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
  1758. bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
  1759. mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
  1760. tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
  1761. num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
  1762. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
  1763. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
  1764. ARRAY_2D_TILED_THIN1);
  1765. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
  1766. tile_split);
  1767. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
  1768. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
  1769. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
  1770. mtaspect);
  1771. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
  1772. ADDR_SURF_MICRO_TILING_DISPLAY);
  1773. } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
  1774. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
  1775. ARRAY_1D_TILED_THIN1);
  1776. }
  1777. fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
  1778. pipe_config);
  1779. dce_v11_0_vga_enable(crtc, false);
  1780. /* Make sure surface address is updated at vertical blank rather than
  1781. * horizontal blank
  1782. */
  1783. tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
  1784. tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
  1785. GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
  1786. WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1787. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  1788. upper_32_bits(fb_location));
  1789. WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  1790. upper_32_bits(fb_location));
  1791. WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  1792. (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
  1793. WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  1794. (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
  1795. WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
  1796. WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
  1797. /*
  1798. * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
  1799. * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
  1800. * retain the full precision throughout the pipeline.
  1801. */
  1802. tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
  1803. if (bypass_lut)
  1804. tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
  1805. else
  1806. tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
  1807. WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
  1808. if (bypass_lut)
  1809. DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
  1810. WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
  1811. WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
  1812. WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
  1813. WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
  1814. WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
  1815. WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
  1816. fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
  1817. WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
  1818. dce_v11_0_grph_enable(crtc, true);
  1819. WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
  1820. target_fb->height);
  1821. x &= ~3;
  1822. y &= ~1;
  1823. WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
  1824. (x << 16) | y);
  1825. viewport_w = crtc->mode.hdisplay;
  1826. viewport_h = (crtc->mode.vdisplay + 1) & ~1;
  1827. WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
  1828. (viewport_w << 16) | viewport_h);
  1829. /* set pageflip to happen anywhere in vblank interval */
  1830. WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
  1831. if (!atomic && fb && fb != crtc->primary->fb) {
  1832. amdgpu_fb = to_amdgpu_framebuffer(fb);
  1833. abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
  1834. r = amdgpu_bo_reserve(abo, true);
  1835. if (unlikely(r != 0))
  1836. return r;
  1837. amdgpu_bo_unpin(abo);
  1838. amdgpu_bo_unreserve(abo);
  1839. }
  1840. /* Bytes per pixel may have changed */
  1841. dce_v11_0_bandwidth_update(adev);
  1842. return 0;
  1843. }
  1844. static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
  1845. struct drm_display_mode *mode)
  1846. {
  1847. struct drm_device *dev = crtc->dev;
  1848. struct amdgpu_device *adev = dev->dev_private;
  1849. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1850. u32 tmp;
  1851. tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
  1852. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  1853. tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
  1854. else
  1855. tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
  1856. WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
  1857. }
  1858. static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
  1859. {
  1860. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1861. struct drm_device *dev = crtc->dev;
  1862. struct amdgpu_device *adev = dev->dev_private;
  1863. u16 *r, *g, *b;
  1864. int i;
  1865. u32 tmp;
  1866. DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
  1867. tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
  1868. tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
  1869. WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1870. tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
  1871. tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
  1872. WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1873. tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
  1874. tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
  1875. WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1876. WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
  1877. WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
  1878. WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
  1879. WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
  1880. WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
  1881. WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
  1882. WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
  1883. WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
  1884. WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
  1885. WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
  1886. r = crtc->gamma_store;
  1887. g = r + crtc->gamma_size;
  1888. b = g + crtc->gamma_size;
  1889. for (i = 0; i < 256; i++) {
  1890. WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
  1891. ((*r++ & 0xffc0) << 14) |
  1892. ((*g++ & 0xffc0) << 4) |
  1893. (*b++ >> 6));
  1894. }
  1895. tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
  1896. tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
  1897. tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
  1898. tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
  1899. WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1900. tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
  1901. tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
  1902. WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1903. tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
  1904. tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
  1905. WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1906. tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
  1907. tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
  1908. WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1909. /* XXX match this to the depth of the crtc fmt block, move to modeset? */
  1910. WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
  1911. /* XXX this only needs to be programmed once per crtc at startup,
  1912. * not sure where the best place for it is
  1913. */
  1914. tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
  1915. tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
  1916. WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  1917. }
  1918. static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
  1919. {
  1920. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  1921. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1922. switch (amdgpu_encoder->encoder_id) {
  1923. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1924. if (dig->linkb)
  1925. return 1;
  1926. else
  1927. return 0;
  1928. break;
  1929. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1930. if (dig->linkb)
  1931. return 3;
  1932. else
  1933. return 2;
  1934. break;
  1935. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  1936. if (dig->linkb)
  1937. return 5;
  1938. else
  1939. return 4;
  1940. break;
  1941. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  1942. return 6;
  1943. break;
  1944. default:
  1945. DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
  1946. return 0;
  1947. }
  1948. }
  1949. /**
  1950. * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
  1951. *
  1952. * @crtc: drm crtc
  1953. *
  1954. * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
  1955. * a single PPLL can be used for all DP crtcs/encoders. For non-DP
  1956. * monitors a dedicated PPLL must be used. If a particular board has
  1957. * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
  1958. * as there is no need to program the PLL itself. If we are not able to
  1959. * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
  1960. * avoid messing up an existing monitor.
  1961. *
  1962. * Asic specific PLL information
  1963. *
  1964. * DCE 10.x
  1965. * Tonga
  1966. * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
  1967. * CI
  1968. * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
  1969. *
  1970. */
  1971. static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
  1972. {
  1973. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  1974. struct drm_device *dev = crtc->dev;
  1975. struct amdgpu_device *adev = dev->dev_private;
  1976. u32 pll_in_use;
  1977. int pll;
  1978. if ((adev->asic_type == CHIP_POLARIS10) ||
  1979. (adev->asic_type == CHIP_POLARIS11) ||
  1980. (adev->asic_type == CHIP_POLARIS12)) {
  1981. struct amdgpu_encoder *amdgpu_encoder =
  1982. to_amdgpu_encoder(amdgpu_crtc->encoder);
  1983. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  1984. if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
  1985. return ATOM_DP_DTO;
  1986. switch (amdgpu_encoder->encoder_id) {
  1987. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  1988. if (dig->linkb)
  1989. return ATOM_COMBOPHY_PLL1;
  1990. else
  1991. return ATOM_COMBOPHY_PLL0;
  1992. break;
  1993. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  1994. if (dig->linkb)
  1995. return ATOM_COMBOPHY_PLL3;
  1996. else
  1997. return ATOM_COMBOPHY_PLL2;
  1998. break;
  1999. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  2000. if (dig->linkb)
  2001. return ATOM_COMBOPHY_PLL5;
  2002. else
  2003. return ATOM_COMBOPHY_PLL4;
  2004. break;
  2005. default:
  2006. DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
  2007. return ATOM_PPLL_INVALID;
  2008. }
  2009. }
  2010. if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
  2011. if (adev->clock.dp_extclk)
  2012. /* skip PPLL programming if using ext clock */
  2013. return ATOM_PPLL_INVALID;
  2014. else {
  2015. /* use the same PPLL for all DP monitors */
  2016. pll = amdgpu_pll_get_shared_dp_ppll(crtc);
  2017. if (pll != ATOM_PPLL_INVALID)
  2018. return pll;
  2019. }
  2020. } else {
  2021. /* use the same PPLL for all monitors with the same clock */
  2022. pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
  2023. if (pll != ATOM_PPLL_INVALID)
  2024. return pll;
  2025. }
  2026. /* XXX need to determine what plls are available on each DCE11 part */
  2027. pll_in_use = amdgpu_pll_get_use_mask(crtc);
  2028. if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
  2029. if (!(pll_in_use & (1 << ATOM_PPLL1)))
  2030. return ATOM_PPLL1;
  2031. if (!(pll_in_use & (1 << ATOM_PPLL0)))
  2032. return ATOM_PPLL0;
  2033. DRM_ERROR("unable to allocate a PPLL\n");
  2034. return ATOM_PPLL_INVALID;
  2035. } else {
  2036. if (!(pll_in_use & (1 << ATOM_PPLL2)))
  2037. return ATOM_PPLL2;
  2038. if (!(pll_in_use & (1 << ATOM_PPLL1)))
  2039. return ATOM_PPLL1;
  2040. if (!(pll_in_use & (1 << ATOM_PPLL0)))
  2041. return ATOM_PPLL0;
  2042. DRM_ERROR("unable to allocate a PPLL\n");
  2043. return ATOM_PPLL_INVALID;
  2044. }
  2045. return ATOM_PPLL_INVALID;
  2046. }
  2047. static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
  2048. {
  2049. struct amdgpu_device *adev = crtc->dev->dev_private;
  2050. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2051. uint32_t cur_lock;
  2052. cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
  2053. if (lock)
  2054. cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
  2055. else
  2056. cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
  2057. WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
  2058. }
  2059. static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
  2060. {
  2061. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2062. struct amdgpu_device *adev = crtc->dev->dev_private;
  2063. u32 tmp;
  2064. tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
  2065. tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
  2066. WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2067. }
  2068. static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
  2069. {
  2070. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2071. struct amdgpu_device *adev = crtc->dev->dev_private;
  2072. u32 tmp;
  2073. WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
  2074. upper_32_bits(amdgpu_crtc->cursor_addr));
  2075. WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
  2076. lower_32_bits(amdgpu_crtc->cursor_addr));
  2077. tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
  2078. tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
  2079. tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
  2080. WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
  2081. }
  2082. static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
  2083. int x, int y)
  2084. {
  2085. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2086. struct amdgpu_device *adev = crtc->dev->dev_private;
  2087. int xorigin = 0, yorigin = 0;
  2088. amdgpu_crtc->cursor_x = x;
  2089. amdgpu_crtc->cursor_y = y;
  2090. /* avivo cursor are offset into the total surface */
  2091. x += crtc->x;
  2092. y += crtc->y;
  2093. DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
  2094. if (x < 0) {
  2095. xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
  2096. x = 0;
  2097. }
  2098. if (y < 0) {
  2099. yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
  2100. y = 0;
  2101. }
  2102. WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
  2103. WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
  2104. WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
  2105. ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
  2106. return 0;
  2107. }
  2108. static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
  2109. int x, int y)
  2110. {
  2111. int ret;
  2112. dce_v11_0_lock_cursor(crtc, true);
  2113. ret = dce_v11_0_cursor_move_locked(crtc, x, y);
  2114. dce_v11_0_lock_cursor(crtc, false);
  2115. return ret;
  2116. }
  2117. static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
  2118. struct drm_file *file_priv,
  2119. uint32_t handle,
  2120. uint32_t width,
  2121. uint32_t height,
  2122. int32_t hot_x,
  2123. int32_t hot_y)
  2124. {
  2125. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2126. struct drm_gem_object *obj;
  2127. struct amdgpu_bo *aobj;
  2128. int ret;
  2129. if (!handle) {
  2130. /* turn off cursor */
  2131. dce_v11_0_hide_cursor(crtc);
  2132. obj = NULL;
  2133. goto unpin;
  2134. }
  2135. if ((width > amdgpu_crtc->max_cursor_width) ||
  2136. (height > amdgpu_crtc->max_cursor_height)) {
  2137. DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
  2138. return -EINVAL;
  2139. }
  2140. obj = drm_gem_object_lookup(file_priv, handle);
  2141. if (!obj) {
  2142. DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
  2143. return -ENOENT;
  2144. }
  2145. aobj = gem_to_amdgpu_bo(obj);
  2146. ret = amdgpu_bo_reserve(aobj, false);
  2147. if (ret != 0) {
  2148. drm_gem_object_put_unlocked(obj);
  2149. return ret;
  2150. }
  2151. ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
  2152. amdgpu_bo_unreserve(aobj);
  2153. if (ret) {
  2154. DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
  2155. drm_gem_object_put_unlocked(obj);
  2156. return ret;
  2157. }
  2158. dce_v11_0_lock_cursor(crtc, true);
  2159. if (width != amdgpu_crtc->cursor_width ||
  2160. height != amdgpu_crtc->cursor_height ||
  2161. hot_x != amdgpu_crtc->cursor_hot_x ||
  2162. hot_y != amdgpu_crtc->cursor_hot_y) {
  2163. int x, y;
  2164. x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
  2165. y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
  2166. dce_v11_0_cursor_move_locked(crtc, x, y);
  2167. amdgpu_crtc->cursor_width = width;
  2168. amdgpu_crtc->cursor_height = height;
  2169. amdgpu_crtc->cursor_hot_x = hot_x;
  2170. amdgpu_crtc->cursor_hot_y = hot_y;
  2171. }
  2172. dce_v11_0_show_cursor(crtc);
  2173. dce_v11_0_lock_cursor(crtc, false);
  2174. unpin:
  2175. if (amdgpu_crtc->cursor_bo) {
  2176. struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
  2177. ret = amdgpu_bo_reserve(aobj, true);
  2178. if (likely(ret == 0)) {
  2179. amdgpu_bo_unpin(aobj);
  2180. amdgpu_bo_unreserve(aobj);
  2181. }
  2182. drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
  2183. }
  2184. amdgpu_crtc->cursor_bo = obj;
  2185. return 0;
  2186. }
  2187. static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
  2188. {
  2189. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2190. if (amdgpu_crtc->cursor_bo) {
  2191. dce_v11_0_lock_cursor(crtc, true);
  2192. dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
  2193. amdgpu_crtc->cursor_y);
  2194. dce_v11_0_show_cursor(crtc);
  2195. dce_v11_0_lock_cursor(crtc, false);
  2196. }
  2197. }
  2198. static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
  2199. u16 *blue, uint32_t size,
  2200. struct drm_modeset_acquire_ctx *ctx)
  2201. {
  2202. dce_v11_0_crtc_load_lut(crtc);
  2203. return 0;
  2204. }
  2205. static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
  2206. {
  2207. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2208. drm_crtc_cleanup(crtc);
  2209. kfree(amdgpu_crtc);
  2210. }
  2211. static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
  2212. .cursor_set2 = dce_v11_0_crtc_cursor_set2,
  2213. .cursor_move = dce_v11_0_crtc_cursor_move,
  2214. .gamma_set = dce_v11_0_crtc_gamma_set,
  2215. .set_config = amdgpu_display_crtc_set_config,
  2216. .destroy = dce_v11_0_crtc_destroy,
  2217. .page_flip_target = amdgpu_display_crtc_page_flip_target,
  2218. };
  2219. static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
  2220. {
  2221. struct drm_device *dev = crtc->dev;
  2222. struct amdgpu_device *adev = dev->dev_private;
  2223. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2224. unsigned type;
  2225. switch (mode) {
  2226. case DRM_MODE_DPMS_ON:
  2227. amdgpu_crtc->enabled = true;
  2228. amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
  2229. dce_v11_0_vga_enable(crtc, true);
  2230. amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
  2231. dce_v11_0_vga_enable(crtc, false);
  2232. /* Make sure VBLANK and PFLIP interrupts are still enabled */
  2233. type = amdgpu_display_crtc_idx_to_irq_type(adev,
  2234. amdgpu_crtc->crtc_id);
  2235. amdgpu_irq_update(adev, &adev->crtc_irq, type);
  2236. amdgpu_irq_update(adev, &adev->pageflip_irq, type);
  2237. drm_crtc_vblank_on(crtc);
  2238. dce_v11_0_crtc_load_lut(crtc);
  2239. break;
  2240. case DRM_MODE_DPMS_STANDBY:
  2241. case DRM_MODE_DPMS_SUSPEND:
  2242. case DRM_MODE_DPMS_OFF:
  2243. drm_crtc_vblank_off(crtc);
  2244. if (amdgpu_crtc->enabled) {
  2245. dce_v11_0_vga_enable(crtc, true);
  2246. amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
  2247. dce_v11_0_vga_enable(crtc, false);
  2248. }
  2249. amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
  2250. amdgpu_crtc->enabled = false;
  2251. break;
  2252. }
  2253. /* adjust pm to dpms */
  2254. amdgpu_pm_compute_clocks(adev);
  2255. }
  2256. static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
  2257. {
  2258. /* disable crtc pair power gating before programming */
  2259. amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
  2260. amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
  2261. dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  2262. }
  2263. static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
  2264. {
  2265. dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  2266. amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
  2267. }
  2268. static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
  2269. {
  2270. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2271. struct drm_device *dev = crtc->dev;
  2272. struct amdgpu_device *adev = dev->dev_private;
  2273. struct amdgpu_atom_ss ss;
  2274. int i;
  2275. dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  2276. if (crtc->primary->fb) {
  2277. int r;
  2278. struct amdgpu_framebuffer *amdgpu_fb;
  2279. struct amdgpu_bo *abo;
  2280. amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
  2281. abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
  2282. r = amdgpu_bo_reserve(abo, true);
  2283. if (unlikely(r))
  2284. DRM_ERROR("failed to reserve abo before unpin\n");
  2285. else {
  2286. amdgpu_bo_unpin(abo);
  2287. amdgpu_bo_unreserve(abo);
  2288. }
  2289. }
  2290. /* disable the GRPH */
  2291. dce_v11_0_grph_enable(crtc, false);
  2292. amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
  2293. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  2294. if (adev->mode_info.crtcs[i] &&
  2295. adev->mode_info.crtcs[i]->enabled &&
  2296. i != amdgpu_crtc->crtc_id &&
  2297. amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
  2298. /* one other crtc is using this pll don't turn
  2299. * off the pll
  2300. */
  2301. goto done;
  2302. }
  2303. }
  2304. switch (amdgpu_crtc->pll_id) {
  2305. case ATOM_PPLL0:
  2306. case ATOM_PPLL1:
  2307. case ATOM_PPLL2:
  2308. /* disable the ppll */
  2309. amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
  2310. 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
  2311. break;
  2312. case ATOM_COMBOPHY_PLL0:
  2313. case ATOM_COMBOPHY_PLL1:
  2314. case ATOM_COMBOPHY_PLL2:
  2315. case ATOM_COMBOPHY_PLL3:
  2316. case ATOM_COMBOPHY_PLL4:
  2317. case ATOM_COMBOPHY_PLL5:
  2318. /* disable the ppll */
  2319. amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
  2320. 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
  2321. break;
  2322. default:
  2323. break;
  2324. }
  2325. done:
  2326. amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  2327. amdgpu_crtc->adjusted_clock = 0;
  2328. amdgpu_crtc->encoder = NULL;
  2329. amdgpu_crtc->connector = NULL;
  2330. }
  2331. static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
  2332. struct drm_display_mode *mode,
  2333. struct drm_display_mode *adjusted_mode,
  2334. int x, int y, struct drm_framebuffer *old_fb)
  2335. {
  2336. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2337. struct drm_device *dev = crtc->dev;
  2338. struct amdgpu_device *adev = dev->dev_private;
  2339. if (!amdgpu_crtc->adjusted_clock)
  2340. return -EINVAL;
  2341. if ((adev->asic_type == CHIP_POLARIS10) ||
  2342. (adev->asic_type == CHIP_POLARIS11) ||
  2343. (adev->asic_type == CHIP_POLARIS12)) {
  2344. struct amdgpu_encoder *amdgpu_encoder =
  2345. to_amdgpu_encoder(amdgpu_crtc->encoder);
  2346. int encoder_mode =
  2347. amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
  2348. /* SetPixelClock calculates the plls and ss values now */
  2349. amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
  2350. amdgpu_crtc->pll_id,
  2351. encoder_mode, amdgpu_encoder->encoder_id,
  2352. adjusted_mode->clock, 0, 0, 0, 0,
  2353. amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
  2354. } else {
  2355. amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
  2356. }
  2357. amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
  2358. dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
  2359. amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
  2360. amdgpu_atombios_crtc_scaler_setup(crtc);
  2361. dce_v11_0_cursor_reset(crtc);
  2362. /* update the hw version fpr dpm */
  2363. amdgpu_crtc->hw_mode = *adjusted_mode;
  2364. return 0;
  2365. }
  2366. static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
  2367. const struct drm_display_mode *mode,
  2368. struct drm_display_mode *adjusted_mode)
  2369. {
  2370. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  2371. struct drm_device *dev = crtc->dev;
  2372. struct drm_encoder *encoder;
  2373. /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
  2374. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  2375. if (encoder->crtc == crtc) {
  2376. amdgpu_crtc->encoder = encoder;
  2377. amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
  2378. break;
  2379. }
  2380. }
  2381. if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
  2382. amdgpu_crtc->encoder = NULL;
  2383. amdgpu_crtc->connector = NULL;
  2384. return false;
  2385. }
  2386. if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
  2387. return false;
  2388. if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
  2389. return false;
  2390. /* pick pll */
  2391. amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
  2392. /* if we can't get a PPLL for a non-DP encoder, fail */
  2393. if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
  2394. !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
  2395. return false;
  2396. return true;
  2397. }
  2398. static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  2399. struct drm_framebuffer *old_fb)
  2400. {
  2401. return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
  2402. }
  2403. static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
  2404. struct drm_framebuffer *fb,
  2405. int x, int y, enum mode_set_atomic state)
  2406. {
  2407. return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
  2408. }
  2409. static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
  2410. .dpms = dce_v11_0_crtc_dpms,
  2411. .mode_fixup = dce_v11_0_crtc_mode_fixup,
  2412. .mode_set = dce_v11_0_crtc_mode_set,
  2413. .mode_set_base = dce_v11_0_crtc_set_base,
  2414. .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
  2415. .prepare = dce_v11_0_crtc_prepare,
  2416. .commit = dce_v11_0_crtc_commit,
  2417. .disable = dce_v11_0_crtc_disable,
  2418. };
  2419. static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
  2420. {
  2421. struct amdgpu_crtc *amdgpu_crtc;
  2422. amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
  2423. (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  2424. if (amdgpu_crtc == NULL)
  2425. return -ENOMEM;
  2426. drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
  2427. drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
  2428. amdgpu_crtc->crtc_id = index;
  2429. adev->mode_info.crtcs[index] = amdgpu_crtc;
  2430. amdgpu_crtc->max_cursor_width = 128;
  2431. amdgpu_crtc->max_cursor_height = 128;
  2432. adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
  2433. adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
  2434. switch (amdgpu_crtc->crtc_id) {
  2435. case 0:
  2436. default:
  2437. amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
  2438. break;
  2439. case 1:
  2440. amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
  2441. break;
  2442. case 2:
  2443. amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
  2444. break;
  2445. case 3:
  2446. amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
  2447. break;
  2448. case 4:
  2449. amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
  2450. break;
  2451. case 5:
  2452. amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
  2453. break;
  2454. }
  2455. amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  2456. amdgpu_crtc->adjusted_clock = 0;
  2457. amdgpu_crtc->encoder = NULL;
  2458. amdgpu_crtc->connector = NULL;
  2459. drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
  2460. return 0;
  2461. }
  2462. static int dce_v11_0_early_init(void *handle)
  2463. {
  2464. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2465. adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
  2466. adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
  2467. dce_v11_0_set_display_funcs(adev);
  2468. adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
  2469. switch (adev->asic_type) {
  2470. case CHIP_CARRIZO:
  2471. adev->mode_info.num_hpd = 6;
  2472. adev->mode_info.num_dig = 9;
  2473. break;
  2474. case CHIP_STONEY:
  2475. adev->mode_info.num_hpd = 6;
  2476. adev->mode_info.num_dig = 9;
  2477. break;
  2478. case CHIP_POLARIS10:
  2479. adev->mode_info.num_hpd = 6;
  2480. adev->mode_info.num_dig = 6;
  2481. break;
  2482. case CHIP_POLARIS11:
  2483. case CHIP_POLARIS12:
  2484. adev->mode_info.num_hpd = 5;
  2485. adev->mode_info.num_dig = 5;
  2486. break;
  2487. default:
  2488. /* FIXME: not supported yet */
  2489. return -EINVAL;
  2490. }
  2491. dce_v11_0_set_irq_funcs(adev);
  2492. return 0;
  2493. }
  2494. static int dce_v11_0_sw_init(void *handle)
  2495. {
  2496. int r, i;
  2497. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2498. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  2499. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
  2500. if (r)
  2501. return r;
  2502. }
  2503. for (i = 8; i < 20; i += 2) {
  2504. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
  2505. if (r)
  2506. return r;
  2507. }
  2508. /* HPD hotplug */
  2509. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
  2510. if (r)
  2511. return r;
  2512. adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
  2513. adev->ddev->mode_config.async_page_flip = true;
  2514. adev->ddev->mode_config.max_width = 16384;
  2515. adev->ddev->mode_config.max_height = 16384;
  2516. adev->ddev->mode_config.preferred_depth = 24;
  2517. adev->ddev->mode_config.prefer_shadow = 1;
  2518. adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
  2519. r = amdgpu_display_modeset_create_props(adev);
  2520. if (r)
  2521. return r;
  2522. adev->ddev->mode_config.max_width = 16384;
  2523. adev->ddev->mode_config.max_height = 16384;
  2524. /* allocate crtcs */
  2525. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  2526. r = dce_v11_0_crtc_init(adev, i);
  2527. if (r)
  2528. return r;
  2529. }
  2530. if (amdgpu_atombios_get_connector_info_from_object_table(adev))
  2531. amdgpu_display_print_display_setup(adev->ddev);
  2532. else
  2533. return -EINVAL;
  2534. /* setup afmt */
  2535. r = dce_v11_0_afmt_init(adev);
  2536. if (r)
  2537. return r;
  2538. r = dce_v11_0_audio_init(adev);
  2539. if (r)
  2540. return r;
  2541. drm_kms_helper_poll_init(adev->ddev);
  2542. adev->mode_info.mode_config_initialized = true;
  2543. return 0;
  2544. }
  2545. static int dce_v11_0_sw_fini(void *handle)
  2546. {
  2547. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2548. kfree(adev->mode_info.bios_hardcoded_edid);
  2549. drm_kms_helper_poll_fini(adev->ddev);
  2550. dce_v11_0_audio_fini(adev);
  2551. dce_v11_0_afmt_fini(adev);
  2552. drm_mode_config_cleanup(adev->ddev);
  2553. adev->mode_info.mode_config_initialized = false;
  2554. return 0;
  2555. }
  2556. static int dce_v11_0_hw_init(void *handle)
  2557. {
  2558. int i;
  2559. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2560. dce_v11_0_init_golden_registers(adev);
  2561. /* disable vga render */
  2562. dce_v11_0_set_vga_render_state(adev, false);
  2563. /* init dig PHYs, disp eng pll */
  2564. amdgpu_atombios_crtc_powergate_init(adev);
  2565. amdgpu_atombios_encoder_init_dig(adev);
  2566. if ((adev->asic_type == CHIP_POLARIS10) ||
  2567. (adev->asic_type == CHIP_POLARIS11) ||
  2568. (adev->asic_type == CHIP_POLARIS12)) {
  2569. amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
  2570. DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
  2571. amdgpu_atombios_crtc_set_dce_clock(adev, 0,
  2572. DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
  2573. } else {
  2574. amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
  2575. }
  2576. /* initialize hpd */
  2577. dce_v11_0_hpd_init(adev);
  2578. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  2579. dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  2580. }
  2581. dce_v11_0_pageflip_interrupt_init(adev);
  2582. return 0;
  2583. }
  2584. static int dce_v11_0_hw_fini(void *handle)
  2585. {
  2586. int i;
  2587. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2588. dce_v11_0_hpd_fini(adev);
  2589. for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
  2590. dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
  2591. }
  2592. dce_v11_0_pageflip_interrupt_fini(adev);
  2593. return 0;
  2594. }
  2595. static int dce_v11_0_suspend(void *handle)
  2596. {
  2597. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2598. adev->mode_info.bl_level =
  2599. amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
  2600. return dce_v11_0_hw_fini(handle);
  2601. }
  2602. static int dce_v11_0_resume(void *handle)
  2603. {
  2604. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2605. int ret;
  2606. amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
  2607. adev->mode_info.bl_level);
  2608. ret = dce_v11_0_hw_init(handle);
  2609. /* turn on the BL */
  2610. if (adev->mode_info.bl_encoder) {
  2611. u8 bl_level = amdgpu_display_backlight_get_level(adev,
  2612. adev->mode_info.bl_encoder);
  2613. amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
  2614. bl_level);
  2615. }
  2616. return ret;
  2617. }
  2618. static bool dce_v11_0_is_idle(void *handle)
  2619. {
  2620. return true;
  2621. }
  2622. static int dce_v11_0_wait_for_idle(void *handle)
  2623. {
  2624. return 0;
  2625. }
  2626. static int dce_v11_0_soft_reset(void *handle)
  2627. {
  2628. u32 srbm_soft_reset = 0, tmp;
  2629. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2630. if (dce_v11_0_is_display_hung(adev))
  2631. srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
  2632. if (srbm_soft_reset) {
  2633. tmp = RREG32(mmSRBM_SOFT_RESET);
  2634. tmp |= srbm_soft_reset;
  2635. dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
  2636. WREG32(mmSRBM_SOFT_RESET, tmp);
  2637. tmp = RREG32(mmSRBM_SOFT_RESET);
  2638. udelay(50);
  2639. tmp &= ~srbm_soft_reset;
  2640. WREG32(mmSRBM_SOFT_RESET, tmp);
  2641. tmp = RREG32(mmSRBM_SOFT_RESET);
  2642. /* Wait a little for things to settle down */
  2643. udelay(50);
  2644. }
  2645. return 0;
  2646. }
  2647. static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  2648. int crtc,
  2649. enum amdgpu_interrupt_state state)
  2650. {
  2651. u32 lb_interrupt_mask;
  2652. if (crtc >= adev->mode_info.num_crtc) {
  2653. DRM_DEBUG("invalid crtc %d\n", crtc);
  2654. return;
  2655. }
  2656. switch (state) {
  2657. case AMDGPU_IRQ_STATE_DISABLE:
  2658. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2659. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2660. VBLANK_INTERRUPT_MASK, 0);
  2661. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2662. break;
  2663. case AMDGPU_IRQ_STATE_ENABLE:
  2664. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2665. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2666. VBLANK_INTERRUPT_MASK, 1);
  2667. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2668. break;
  2669. default:
  2670. break;
  2671. }
  2672. }
  2673. static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
  2674. int crtc,
  2675. enum amdgpu_interrupt_state state)
  2676. {
  2677. u32 lb_interrupt_mask;
  2678. if (crtc >= adev->mode_info.num_crtc) {
  2679. DRM_DEBUG("invalid crtc %d\n", crtc);
  2680. return;
  2681. }
  2682. switch (state) {
  2683. case AMDGPU_IRQ_STATE_DISABLE:
  2684. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2685. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2686. VLINE_INTERRUPT_MASK, 0);
  2687. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2688. break;
  2689. case AMDGPU_IRQ_STATE_ENABLE:
  2690. lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
  2691. lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
  2692. VLINE_INTERRUPT_MASK, 1);
  2693. WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
  2694. break;
  2695. default:
  2696. break;
  2697. }
  2698. }
  2699. static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
  2700. struct amdgpu_irq_src *source,
  2701. unsigned hpd,
  2702. enum amdgpu_interrupt_state state)
  2703. {
  2704. u32 tmp;
  2705. if (hpd >= adev->mode_info.num_hpd) {
  2706. DRM_DEBUG("invalid hdp %d\n", hpd);
  2707. return 0;
  2708. }
  2709. switch (state) {
  2710. case AMDGPU_IRQ_STATE_DISABLE:
  2711. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  2712. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
  2713. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  2714. break;
  2715. case AMDGPU_IRQ_STATE_ENABLE:
  2716. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  2717. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
  2718. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  2719. break;
  2720. default:
  2721. break;
  2722. }
  2723. return 0;
  2724. }
  2725. static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
  2726. struct amdgpu_irq_src *source,
  2727. unsigned type,
  2728. enum amdgpu_interrupt_state state)
  2729. {
  2730. switch (type) {
  2731. case AMDGPU_CRTC_IRQ_VBLANK1:
  2732. dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
  2733. break;
  2734. case AMDGPU_CRTC_IRQ_VBLANK2:
  2735. dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
  2736. break;
  2737. case AMDGPU_CRTC_IRQ_VBLANK3:
  2738. dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
  2739. break;
  2740. case AMDGPU_CRTC_IRQ_VBLANK4:
  2741. dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
  2742. break;
  2743. case AMDGPU_CRTC_IRQ_VBLANK5:
  2744. dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
  2745. break;
  2746. case AMDGPU_CRTC_IRQ_VBLANK6:
  2747. dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
  2748. break;
  2749. case AMDGPU_CRTC_IRQ_VLINE1:
  2750. dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
  2751. break;
  2752. case AMDGPU_CRTC_IRQ_VLINE2:
  2753. dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
  2754. break;
  2755. case AMDGPU_CRTC_IRQ_VLINE3:
  2756. dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
  2757. break;
  2758. case AMDGPU_CRTC_IRQ_VLINE4:
  2759. dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
  2760. break;
  2761. case AMDGPU_CRTC_IRQ_VLINE5:
  2762. dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
  2763. break;
  2764. case AMDGPU_CRTC_IRQ_VLINE6:
  2765. dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
  2766. break;
  2767. default:
  2768. break;
  2769. }
  2770. return 0;
  2771. }
  2772. static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
  2773. struct amdgpu_irq_src *src,
  2774. unsigned type,
  2775. enum amdgpu_interrupt_state state)
  2776. {
  2777. u32 reg;
  2778. if (type >= adev->mode_info.num_crtc) {
  2779. DRM_ERROR("invalid pageflip crtc %d\n", type);
  2780. return -EINVAL;
  2781. }
  2782. reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
  2783. if (state == AMDGPU_IRQ_STATE_DISABLE)
  2784. WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
  2785. reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
  2786. else
  2787. WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
  2788. reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
  2789. return 0;
  2790. }
  2791. static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
  2792. struct amdgpu_irq_src *source,
  2793. struct amdgpu_iv_entry *entry)
  2794. {
  2795. unsigned long flags;
  2796. unsigned crtc_id;
  2797. struct amdgpu_crtc *amdgpu_crtc;
  2798. struct amdgpu_flip_work *works;
  2799. crtc_id = (entry->src_id - 8) >> 1;
  2800. amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
  2801. if (crtc_id >= adev->mode_info.num_crtc) {
  2802. DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
  2803. return -EINVAL;
  2804. }
  2805. if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
  2806. GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
  2807. WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
  2808. GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
  2809. /* IRQ could occur when in initial stage */
  2810. if(amdgpu_crtc == NULL)
  2811. return 0;
  2812. spin_lock_irqsave(&adev->ddev->event_lock, flags);
  2813. works = amdgpu_crtc->pflip_works;
  2814. if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
  2815. DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
  2816. "AMDGPU_FLIP_SUBMITTED(%d)\n",
  2817. amdgpu_crtc->pflip_status,
  2818. AMDGPU_FLIP_SUBMITTED);
  2819. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  2820. return 0;
  2821. }
  2822. /* page flip completed. clean up */
  2823. amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
  2824. amdgpu_crtc->pflip_works = NULL;
  2825. /* wakeup usersapce */
  2826. if(works->event)
  2827. drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
  2828. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  2829. drm_crtc_vblank_put(&amdgpu_crtc->base);
  2830. schedule_work(&works->unpin_work);
  2831. return 0;
  2832. }
  2833. static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
  2834. int hpd)
  2835. {
  2836. u32 tmp;
  2837. if (hpd >= adev->mode_info.num_hpd) {
  2838. DRM_DEBUG("invalid hdp %d\n", hpd);
  2839. return;
  2840. }
  2841. tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
  2842. tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
  2843. WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
  2844. }
  2845. static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
  2846. int crtc)
  2847. {
  2848. u32 tmp;
  2849. if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
  2850. DRM_DEBUG("invalid crtc %d\n", crtc);
  2851. return;
  2852. }
  2853. tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
  2854. tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
  2855. WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
  2856. }
  2857. static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
  2858. int crtc)
  2859. {
  2860. u32 tmp;
  2861. if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
  2862. DRM_DEBUG("invalid crtc %d\n", crtc);
  2863. return;
  2864. }
  2865. tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
  2866. tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
  2867. WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
  2868. }
  2869. static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
  2870. struct amdgpu_irq_src *source,
  2871. struct amdgpu_iv_entry *entry)
  2872. {
  2873. unsigned crtc = entry->src_id - 1;
  2874. uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
  2875. unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
  2876. crtc);
  2877. switch (entry->src_data[0]) {
  2878. case 0: /* vblank */
  2879. if (disp_int & interrupt_status_offsets[crtc].vblank)
  2880. dce_v11_0_crtc_vblank_int_ack(adev, crtc);
  2881. else
  2882. DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
  2883. if (amdgpu_irq_enabled(adev, source, irq_type)) {
  2884. drm_handle_vblank(adev->ddev, crtc);
  2885. }
  2886. DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
  2887. break;
  2888. case 1: /* vline */
  2889. if (disp_int & interrupt_status_offsets[crtc].vline)
  2890. dce_v11_0_crtc_vline_int_ack(adev, crtc);
  2891. else
  2892. DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
  2893. DRM_DEBUG("IH: D%d vline\n", crtc + 1);
  2894. break;
  2895. default:
  2896. DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
  2897. break;
  2898. }
  2899. return 0;
  2900. }
  2901. static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
  2902. struct amdgpu_irq_src *source,
  2903. struct amdgpu_iv_entry *entry)
  2904. {
  2905. uint32_t disp_int, mask;
  2906. unsigned hpd;
  2907. if (entry->src_data[0] >= adev->mode_info.num_hpd) {
  2908. DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
  2909. return 0;
  2910. }
  2911. hpd = entry->src_data[0];
  2912. disp_int = RREG32(interrupt_status_offsets[hpd].reg);
  2913. mask = interrupt_status_offsets[hpd].hpd;
  2914. if (disp_int & mask) {
  2915. dce_v11_0_hpd_int_ack(adev, hpd);
  2916. schedule_work(&adev->hotplug_work);
  2917. DRM_DEBUG("IH: HPD%d\n", hpd + 1);
  2918. }
  2919. return 0;
  2920. }
  2921. static int dce_v11_0_set_clockgating_state(void *handle,
  2922. enum amd_clockgating_state state)
  2923. {
  2924. return 0;
  2925. }
  2926. static int dce_v11_0_set_powergating_state(void *handle,
  2927. enum amd_powergating_state state)
  2928. {
  2929. return 0;
  2930. }
  2931. static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
  2932. .name = "dce_v11_0",
  2933. .early_init = dce_v11_0_early_init,
  2934. .late_init = NULL,
  2935. .sw_init = dce_v11_0_sw_init,
  2936. .sw_fini = dce_v11_0_sw_fini,
  2937. .hw_init = dce_v11_0_hw_init,
  2938. .hw_fini = dce_v11_0_hw_fini,
  2939. .suspend = dce_v11_0_suspend,
  2940. .resume = dce_v11_0_resume,
  2941. .is_idle = dce_v11_0_is_idle,
  2942. .wait_for_idle = dce_v11_0_wait_for_idle,
  2943. .soft_reset = dce_v11_0_soft_reset,
  2944. .set_clockgating_state = dce_v11_0_set_clockgating_state,
  2945. .set_powergating_state = dce_v11_0_set_powergating_state,
  2946. };
  2947. static void
  2948. dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
  2949. struct drm_display_mode *mode,
  2950. struct drm_display_mode *adjusted_mode)
  2951. {
  2952. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  2953. amdgpu_encoder->pixel_clock = adjusted_mode->clock;
  2954. /* need to call this here rather than in prepare() since we need some crtc info */
  2955. amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  2956. /* set scaler clears this on some chips */
  2957. dce_v11_0_set_interleave(encoder->crtc, mode);
  2958. if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
  2959. dce_v11_0_afmt_enable(encoder, true);
  2960. dce_v11_0_afmt_setmode(encoder, adjusted_mode);
  2961. }
  2962. }
  2963. static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
  2964. {
  2965. struct amdgpu_device *adev = encoder->dev->dev_private;
  2966. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  2967. struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
  2968. if ((amdgpu_encoder->active_device &
  2969. (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
  2970. (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
  2971. ENCODER_OBJECT_ID_NONE)) {
  2972. struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
  2973. if (dig) {
  2974. dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
  2975. if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
  2976. dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
  2977. }
  2978. }
  2979. amdgpu_atombios_scratch_regs_lock(adev, true);
  2980. if (connector) {
  2981. struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
  2982. /* select the clock/data port if it uses a router */
  2983. if (amdgpu_connector->router.cd_valid)
  2984. amdgpu_i2c_router_select_cd_port(amdgpu_connector);
  2985. /* turn eDP panel on for mode set */
  2986. if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
  2987. amdgpu_atombios_encoder_set_edp_panel_power(connector,
  2988. ATOM_TRANSMITTER_ACTION_POWER_ON);
  2989. }
  2990. /* this is needed for the pll/ss setup to work correctly in some cases */
  2991. amdgpu_atombios_encoder_set_crtc_source(encoder);
  2992. /* set up the FMT blocks */
  2993. dce_v11_0_program_fmt(encoder);
  2994. }
  2995. static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
  2996. {
  2997. struct drm_device *dev = encoder->dev;
  2998. struct amdgpu_device *adev = dev->dev_private;
  2999. /* need to call this here as we need the crtc set up */
  3000. amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
  3001. amdgpu_atombios_scratch_regs_lock(adev, false);
  3002. }
  3003. static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
  3004. {
  3005. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  3006. struct amdgpu_encoder_atom_dig *dig;
  3007. amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
  3008. if (amdgpu_atombios_encoder_is_digital(encoder)) {
  3009. if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
  3010. dce_v11_0_afmt_enable(encoder, false);
  3011. dig = amdgpu_encoder->enc_priv;
  3012. dig->dig_encoder = -1;
  3013. }
  3014. amdgpu_encoder->active_device = 0;
  3015. }
  3016. /* these are handled by the primary encoders */
  3017. static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
  3018. {
  3019. }
  3020. static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
  3021. {
  3022. }
  3023. static void
  3024. dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
  3025. struct drm_display_mode *mode,
  3026. struct drm_display_mode *adjusted_mode)
  3027. {
  3028. }
  3029. static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
  3030. {
  3031. }
  3032. static void
  3033. dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
  3034. {
  3035. }
  3036. static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
  3037. .dpms = dce_v11_0_ext_dpms,
  3038. .prepare = dce_v11_0_ext_prepare,
  3039. .mode_set = dce_v11_0_ext_mode_set,
  3040. .commit = dce_v11_0_ext_commit,
  3041. .disable = dce_v11_0_ext_disable,
  3042. /* no detect for TMDS/LVDS yet */
  3043. };
  3044. static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
  3045. .dpms = amdgpu_atombios_encoder_dpms,
  3046. .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
  3047. .prepare = dce_v11_0_encoder_prepare,
  3048. .mode_set = dce_v11_0_encoder_mode_set,
  3049. .commit = dce_v11_0_encoder_commit,
  3050. .disable = dce_v11_0_encoder_disable,
  3051. .detect = amdgpu_atombios_encoder_dig_detect,
  3052. };
  3053. static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
  3054. .dpms = amdgpu_atombios_encoder_dpms,
  3055. .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
  3056. .prepare = dce_v11_0_encoder_prepare,
  3057. .mode_set = dce_v11_0_encoder_mode_set,
  3058. .commit = dce_v11_0_encoder_commit,
  3059. .detect = amdgpu_atombios_encoder_dac_detect,
  3060. };
  3061. static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
  3062. {
  3063. struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
  3064. if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  3065. amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
  3066. kfree(amdgpu_encoder->enc_priv);
  3067. drm_encoder_cleanup(encoder);
  3068. kfree(amdgpu_encoder);
  3069. }
  3070. static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
  3071. .destroy = dce_v11_0_encoder_destroy,
  3072. };
  3073. static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
  3074. uint32_t encoder_enum,
  3075. uint32_t supported_device,
  3076. u16 caps)
  3077. {
  3078. struct drm_device *dev = adev->ddev;
  3079. struct drm_encoder *encoder;
  3080. struct amdgpu_encoder *amdgpu_encoder;
  3081. /* see if we already added it */
  3082. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  3083. amdgpu_encoder = to_amdgpu_encoder(encoder);
  3084. if (amdgpu_encoder->encoder_enum == encoder_enum) {
  3085. amdgpu_encoder->devices |= supported_device;
  3086. return;
  3087. }
  3088. }
  3089. /* add a new one */
  3090. amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
  3091. if (!amdgpu_encoder)
  3092. return;
  3093. encoder = &amdgpu_encoder->base;
  3094. switch (adev->mode_info.num_crtc) {
  3095. case 1:
  3096. encoder->possible_crtcs = 0x1;
  3097. break;
  3098. case 2:
  3099. default:
  3100. encoder->possible_crtcs = 0x3;
  3101. break;
  3102. case 3:
  3103. encoder->possible_crtcs = 0x7;
  3104. break;
  3105. case 4:
  3106. encoder->possible_crtcs = 0xf;
  3107. break;
  3108. case 5:
  3109. encoder->possible_crtcs = 0x1f;
  3110. break;
  3111. case 6:
  3112. encoder->possible_crtcs = 0x3f;
  3113. break;
  3114. }
  3115. amdgpu_encoder->enc_priv = NULL;
  3116. amdgpu_encoder->encoder_enum = encoder_enum;
  3117. amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
  3118. amdgpu_encoder->devices = supported_device;
  3119. amdgpu_encoder->rmx_type = RMX_OFF;
  3120. amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
  3121. amdgpu_encoder->is_ext_encoder = false;
  3122. amdgpu_encoder->caps = caps;
  3123. switch (amdgpu_encoder->encoder_id) {
  3124. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
  3125. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
  3126. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3127. DRM_MODE_ENCODER_DAC, NULL);
  3128. drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
  3129. break;
  3130. case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
  3131. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
  3132. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
  3133. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
  3134. case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
  3135. if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
  3136. amdgpu_encoder->rmx_type = RMX_FULL;
  3137. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3138. DRM_MODE_ENCODER_LVDS, NULL);
  3139. amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
  3140. } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
  3141. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3142. DRM_MODE_ENCODER_DAC, NULL);
  3143. amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
  3144. } else {
  3145. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3146. DRM_MODE_ENCODER_TMDS, NULL);
  3147. amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
  3148. }
  3149. drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
  3150. break;
  3151. case ENCODER_OBJECT_ID_SI170B:
  3152. case ENCODER_OBJECT_ID_CH7303:
  3153. case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
  3154. case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
  3155. case ENCODER_OBJECT_ID_TITFP513:
  3156. case ENCODER_OBJECT_ID_VT1623:
  3157. case ENCODER_OBJECT_ID_HDMI_SI1930:
  3158. case ENCODER_OBJECT_ID_TRAVIS:
  3159. case ENCODER_OBJECT_ID_NUTMEG:
  3160. /* these are handled by the primary encoders */
  3161. amdgpu_encoder->is_ext_encoder = true;
  3162. if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
  3163. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3164. DRM_MODE_ENCODER_LVDS, NULL);
  3165. else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
  3166. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3167. DRM_MODE_ENCODER_DAC, NULL);
  3168. else
  3169. drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
  3170. DRM_MODE_ENCODER_TMDS, NULL);
  3171. drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
  3172. break;
  3173. }
  3174. }
  3175. static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
  3176. .bandwidth_update = &dce_v11_0_bandwidth_update,
  3177. .vblank_get_counter = &dce_v11_0_vblank_get_counter,
  3178. .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
  3179. .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
  3180. .hpd_sense = &dce_v11_0_hpd_sense,
  3181. .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
  3182. .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
  3183. .page_flip = &dce_v11_0_page_flip,
  3184. .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
  3185. .add_encoder = &dce_v11_0_encoder_add,
  3186. .add_connector = &amdgpu_connector_add,
  3187. };
  3188. static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
  3189. {
  3190. if (adev->mode_info.funcs == NULL)
  3191. adev->mode_info.funcs = &dce_v11_0_display_funcs;
  3192. }
  3193. static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
  3194. .set = dce_v11_0_set_crtc_irq_state,
  3195. .process = dce_v11_0_crtc_irq,
  3196. };
  3197. static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
  3198. .set = dce_v11_0_set_pageflip_irq_state,
  3199. .process = dce_v11_0_pageflip_irq,
  3200. };
  3201. static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
  3202. .set = dce_v11_0_set_hpd_irq_state,
  3203. .process = dce_v11_0_hpd_irq,
  3204. };
  3205. static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
  3206. {
  3207. if (adev->mode_info.num_crtc > 0)
  3208. adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
  3209. else
  3210. adev->crtc_irq.num_types = 0;
  3211. adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
  3212. adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
  3213. adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
  3214. adev->hpd_irq.num_types = adev->mode_info.num_hpd;
  3215. adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
  3216. }
  3217. const struct amdgpu_ip_block_version dce_v11_0_ip_block =
  3218. {
  3219. .type = AMD_IP_BLOCK_TYPE_DCE,
  3220. .major = 11,
  3221. .minor = 0,
  3222. .rev = 0,
  3223. .funcs = &dce_v11_0_ip_funcs,
  3224. };
  3225. const struct amdgpu_ip_block_version dce_v11_2_ip_block =
  3226. {
  3227. .type = AMD_IP_BLOCK_TYPE_DCE,
  3228. .major = 11,
  3229. .minor = 2,
  3230. .rev = 0,
  3231. .funcs = &dce_v11_0_ip_funcs,
  3232. };