arch_timer.h 4.1 KB

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  1. /*
  2. * arch/arm64/include/asm/arch_timer.h
  3. *
  4. * Copyright (C) 2012 ARM Ltd.
  5. * Author: Marc Zyngier <marc.zyngier@arm.com>
  6. *
  7. * This program is free software: you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #ifndef __ASM_ARCH_TIMER_H
  20. #define __ASM_ARCH_TIMER_H
  21. #include <asm/barrier.h>
  22. #include <asm/sysreg.h>
  23. #include <linux/bug.h>
  24. #include <linux/init.h>
  25. #include <linux/jump_label.h>
  26. #include <linux/smp.h>
  27. #include <linux/types.h>
  28. #include <clocksource/arm_arch_timer.h>
  29. #if IS_ENABLED(CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND)
  30. extern struct static_key_false arch_timer_read_ool_enabled;
  31. #define needs_unstable_timer_counter_workaround() \
  32. static_branch_unlikely(&arch_timer_read_ool_enabled)
  33. #else
  34. #define needs_unstable_timer_counter_workaround() false
  35. #endif
  36. enum arch_timer_erratum_match_type {
  37. ate_match_dt,
  38. ate_match_local_cap_id,
  39. ate_match_acpi_oem_info,
  40. };
  41. struct clock_event_device;
  42. struct arch_timer_erratum_workaround {
  43. enum arch_timer_erratum_match_type match_type;
  44. const void *id;
  45. const char *desc;
  46. u32 (*read_cntp_tval_el0)(void);
  47. u32 (*read_cntv_tval_el0)(void);
  48. u64 (*read_cntpct_el0)(void);
  49. u64 (*read_cntvct_el0)(void);
  50. int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
  51. int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
  52. };
  53. DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
  54. timer_unstable_counter_workaround);
  55. #define arch_timer_reg_read_stable(reg) \
  56. ({ \
  57. u64 _val; \
  58. if (needs_unstable_timer_counter_workaround()) { \
  59. const struct arch_timer_erratum_workaround *wa; \
  60. preempt_disable_notrace(); \
  61. wa = __this_cpu_read(timer_unstable_counter_workaround); \
  62. if (wa && wa->read_##reg) \
  63. _val = wa->read_##reg(); \
  64. else \
  65. _val = read_sysreg(reg); \
  66. preempt_enable_notrace(); \
  67. } else { \
  68. _val = read_sysreg(reg); \
  69. } \
  70. _val; \
  71. })
  72. /*
  73. * These register accessors are marked inline so the compiler can
  74. * nicely work out which register we want, and chuck away the rest of
  75. * the code.
  76. */
  77. static __always_inline
  78. void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
  79. {
  80. if (access == ARCH_TIMER_PHYS_ACCESS) {
  81. switch (reg) {
  82. case ARCH_TIMER_REG_CTRL:
  83. write_sysreg(val, cntp_ctl_el0);
  84. break;
  85. case ARCH_TIMER_REG_TVAL:
  86. write_sysreg(val, cntp_tval_el0);
  87. break;
  88. }
  89. } else if (access == ARCH_TIMER_VIRT_ACCESS) {
  90. switch (reg) {
  91. case ARCH_TIMER_REG_CTRL:
  92. write_sysreg(val, cntv_ctl_el0);
  93. break;
  94. case ARCH_TIMER_REG_TVAL:
  95. write_sysreg(val, cntv_tval_el0);
  96. break;
  97. }
  98. }
  99. isb();
  100. }
  101. static __always_inline
  102. u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
  103. {
  104. if (access == ARCH_TIMER_PHYS_ACCESS) {
  105. switch (reg) {
  106. case ARCH_TIMER_REG_CTRL:
  107. return read_sysreg(cntp_ctl_el0);
  108. case ARCH_TIMER_REG_TVAL:
  109. return arch_timer_reg_read_stable(cntp_tval_el0);
  110. }
  111. } else if (access == ARCH_TIMER_VIRT_ACCESS) {
  112. switch (reg) {
  113. case ARCH_TIMER_REG_CTRL:
  114. return read_sysreg(cntv_ctl_el0);
  115. case ARCH_TIMER_REG_TVAL:
  116. return arch_timer_reg_read_stable(cntv_tval_el0);
  117. }
  118. }
  119. BUG();
  120. }
  121. static inline u32 arch_timer_get_cntfrq(void)
  122. {
  123. return read_sysreg(cntfrq_el0);
  124. }
  125. static inline u32 arch_timer_get_cntkctl(void)
  126. {
  127. return read_sysreg(cntkctl_el1);
  128. }
  129. static inline void arch_timer_set_cntkctl(u32 cntkctl)
  130. {
  131. write_sysreg(cntkctl, cntkctl_el1);
  132. isb();
  133. }
  134. static inline u64 arch_counter_get_cntpct(void)
  135. {
  136. isb();
  137. return arch_timer_reg_read_stable(cntpct_el0);
  138. }
  139. static inline u64 arch_counter_get_cntvct(void)
  140. {
  141. isb();
  142. return arch_timer_reg_read_stable(cntvct_el0);
  143. }
  144. static inline int arch_timer_arch_init(void)
  145. {
  146. return 0;
  147. }
  148. #endif