setup.c 14 KB

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  1. /*
  2. * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. */
  8. #include <linux/seq_file.h>
  9. #include <linux/fs.h>
  10. #include <linux/delay.h>
  11. #include <linux/root_dev.h>
  12. #include <linux/console.h>
  13. #include <linux/module.h>
  14. #include <linux/cpu.h>
  15. #include <linux/clk-provider.h>
  16. #include <linux/of_fdt.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/cache.h>
  19. #include <asm/sections.h>
  20. #include <asm/arcregs.h>
  21. #include <asm/tlb.h>
  22. #include <asm/setup.h>
  23. #include <asm/page.h>
  24. #include <asm/irq.h>
  25. #include <asm/unwind.h>
  26. #include <asm/clk.h>
  27. #include <asm/mach_desc.h>
  28. #include <asm/smp.h>
  29. #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x))
  30. unsigned int intr_to_DE_cnt;
  31. /* Part of U-boot ABI: see head.S */
  32. int __initdata uboot_tag;
  33. char __initdata *uboot_arg;
  34. const struct machine_desc *machine_desc;
  35. struct task_struct *_current_task[NR_CPUS]; /* For stack switching */
  36. struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  37. static void read_arc_build_cfg_regs(void)
  38. {
  39. struct bcr_perip uncached_space;
  40. struct bcr_generic bcr;
  41. struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
  42. FIX_PTR(cpu);
  43. READ_BCR(AUX_IDENTITY, cpu->core);
  44. READ_BCR(ARC_REG_ISA_CFG_BCR, cpu->isa);
  45. READ_BCR(ARC_REG_TIMERS_BCR, cpu->timers);
  46. cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
  47. READ_BCR(ARC_REG_D_UNCACH_BCR, uncached_space);
  48. BUG_ON((uncached_space.start << 24) != ARC_UNCACHED_ADDR_SPACE);
  49. READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
  50. cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
  51. cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
  52. cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0; /* 1,3 */
  53. cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
  54. cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
  55. /* Note that we read the CCM BCRs independent of kernel config
  56. * This is to catch the cases where user doesn't know that
  57. * CCMs are present in hardware build
  58. */
  59. {
  60. struct bcr_iccm iccm;
  61. struct bcr_dccm dccm;
  62. struct bcr_dccm_base dccm_base;
  63. unsigned int bcr_32bit_val;
  64. bcr_32bit_val = read_aux_reg(ARC_REG_ICCM_BCR);
  65. if (bcr_32bit_val) {
  66. iccm = *((struct bcr_iccm *)&bcr_32bit_val);
  67. cpu->iccm.base_addr = iccm.base << 16;
  68. cpu->iccm.sz = 0x2000 << (iccm.sz - 1);
  69. }
  70. bcr_32bit_val = read_aux_reg(ARC_REG_DCCM_BCR);
  71. if (bcr_32bit_val) {
  72. dccm = *((struct bcr_dccm *)&bcr_32bit_val);
  73. cpu->dccm.sz = 0x800 << (dccm.sz);
  74. READ_BCR(ARC_REG_DCCMBASE_BCR, dccm_base);
  75. cpu->dccm.base_addr = dccm_base.addr << 8;
  76. }
  77. }
  78. READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
  79. read_decode_mmu_bcr();
  80. read_decode_cache_bcr();
  81. if (is_isa_arcompact()) {
  82. struct bcr_fp_arcompact sp, dp;
  83. struct bcr_bpu_arcompact bpu;
  84. READ_BCR(ARC_REG_FP_BCR, sp);
  85. READ_BCR(ARC_REG_DPFP_BCR, dp);
  86. cpu->extn.fpu_sp = sp.ver ? 1 : 0;
  87. cpu->extn.fpu_dp = dp.ver ? 1 : 0;
  88. READ_BCR(ARC_REG_BPU_BCR, bpu);
  89. cpu->bpu.ver = bpu.ver;
  90. cpu->bpu.full = bpu.fam ? 1 : 0;
  91. if (bpu.ent) {
  92. cpu->bpu.num_cache = 256 << (bpu.ent - 1);
  93. cpu->bpu.num_pred = 256 << (bpu.ent - 1);
  94. }
  95. } else {
  96. struct bcr_fp_arcv2 spdp;
  97. struct bcr_bpu_arcv2 bpu;
  98. READ_BCR(ARC_REG_FP_V2_BCR, spdp);
  99. cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
  100. cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
  101. READ_BCR(ARC_REG_BPU_BCR, bpu);
  102. cpu->bpu.ver = bpu.ver;
  103. cpu->bpu.full = bpu.ft;
  104. cpu->bpu.num_cache = 256 << bpu.bce;
  105. cpu->bpu.num_pred = 2048 << bpu.pte;
  106. }
  107. READ_BCR(ARC_REG_AP_BCR, bcr);
  108. cpu->extn.ap = bcr.ver ? 1 : 0;
  109. READ_BCR(ARC_REG_SMART_BCR, bcr);
  110. cpu->extn.smart = bcr.ver ? 1 : 0;
  111. READ_BCR(ARC_REG_RTT_BCR, bcr);
  112. cpu->extn.rtt = bcr.ver ? 1 : 0;
  113. cpu->extn.debug = cpu->extn.ap | cpu->extn.smart | cpu->extn.rtt;
  114. }
  115. static const struct cpuinfo_data arc_cpu_tbl[] = {
  116. { {0x20, "ARC 600" }, 0x2F},
  117. { {0x30, "ARC 700" }, 0x33},
  118. { {0x34, "ARC 700 R4.10"}, 0x34},
  119. { {0x35, "ARC 700 R4.11"}, 0x35},
  120. { {0x50, "ARC HS38" }, 0x51},
  121. { {0x00, NULL } }
  122. };
  123. #define IS_AVAIL1(v, str) ((v) ? str : "")
  124. #define IS_USED(cfg) (IS_ENABLED(cfg) ? "" : "(not used) ")
  125. #define IS_AVAIL2(v, str, cfg) IS_AVAIL1(v, str), IS_AVAIL1(v, IS_USED(cfg))
  126. static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
  127. {
  128. struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
  129. struct bcr_identity *core = &cpu->core;
  130. const struct cpuinfo_data *tbl;
  131. char *isa_nm;
  132. int i, be, atomic;
  133. int n = 0;
  134. FIX_PTR(cpu);
  135. if (is_isa_arcompact()) {
  136. isa_nm = "ARCompact";
  137. be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
  138. atomic = cpu->isa.atomic1;
  139. if (!cpu->isa.ver) /* ISA BCR absent, use Kconfig info */
  140. atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
  141. } else {
  142. isa_nm = "ARCv2";
  143. be = cpu->isa.be;
  144. atomic = cpu->isa.atomic;
  145. }
  146. n += scnprintf(buf + n, len - n,
  147. "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
  148. core->family, core->cpu_id, core->chip_id);
  149. for (tbl = &arc_cpu_tbl[0]; tbl->info.id != 0; tbl++) {
  150. if ((core->family >= tbl->info.id) &&
  151. (core->family <= tbl->up_range)) {
  152. n += scnprintf(buf + n, len - n,
  153. "processor [%d]\t: %s (%s ISA) %s\n",
  154. cpu_id, tbl->info.str, isa_nm,
  155. IS_AVAIL1(be, "[Big-Endian]"));
  156. break;
  157. }
  158. }
  159. if (tbl->info.id == 0)
  160. n += scnprintf(buf + n, len - n, "UNKNOWN ARC Processor\n");
  161. n += scnprintf(buf + n, len - n, "CPU speed\t: %u.%02u Mhz\n",
  162. (unsigned int)(arc_get_core_freq() / 1000000),
  163. (unsigned int)(arc_get_core_freq() / 10000) % 100);
  164. n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s\nISA Extn\t: ",
  165. IS_AVAIL1(cpu->timers.t0, "Timer0 "),
  166. IS_AVAIL1(cpu->timers.t1, "Timer1 "),
  167. IS_AVAIL2(cpu->timers.rtc, "64-bit RTC ",
  168. CONFIG_ARC_HAS_RTC));
  169. n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s",
  170. IS_AVAIL2(atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
  171. IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
  172. IS_AVAIL1(cpu->isa.unalign, "unalign (not used)"));
  173. if (i)
  174. n += scnprintf(buf + n, len - n, "\n\t\t: ");
  175. if (cpu->extn_mpy.ver) {
  176. if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */
  177. n += scnprintf(buf + n, len - n, "mpy ");
  178. } else {
  179. int opt = 2; /* stock MPY/MPYH */
  180. if (cpu->extn_mpy.dsp) /* OPT 7-9 */
  181. opt = cpu->extn_mpy.dsp + 6;
  182. n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
  183. }
  184. n += scnprintf(buf + n, len - n, "%s",
  185. IS_USED(CONFIG_ARC_HAS_HW_MPY));
  186. }
  187. n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
  188. IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
  189. IS_AVAIL1(cpu->extn.norm, "norm "),
  190. IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
  191. IS_AVAIL1(cpu->extn.swap, "swap "),
  192. IS_AVAIL1(cpu->extn.minmax, "minmax "),
  193. IS_AVAIL1(cpu->extn.crc, "crc "),
  194. IS_AVAIL2(1, "swape", CONFIG_ARC_HAS_SWAPE));
  195. if (cpu->bpu.ver)
  196. n += scnprintf(buf + n, len - n,
  197. "BPU\t\t: %s%s match, cache:%d, Predict Table:%d\n",
  198. IS_AVAIL1(cpu->bpu.full, "full"),
  199. IS_AVAIL1(!cpu->bpu.full, "partial"),
  200. cpu->bpu.num_cache, cpu->bpu.num_pred);
  201. return buf;
  202. }
  203. static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
  204. {
  205. int n = 0;
  206. struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
  207. FIX_PTR(cpu);
  208. n += scnprintf(buf + n, len - n,
  209. "Vector Table\t: %#x\nUncached Base\t: %#x\n",
  210. cpu->vec_base, ARC_UNCACHED_ADDR_SPACE);
  211. if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
  212. n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
  213. IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
  214. IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
  215. if (cpu->extn.debug)
  216. n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s%s\n",
  217. IS_AVAIL1(cpu->extn.ap, "ActionPoint "),
  218. IS_AVAIL1(cpu->extn.smart, "smaRT "),
  219. IS_AVAIL1(cpu->extn.rtt, "RTT "));
  220. if (cpu->dccm.sz || cpu->iccm.sz)
  221. n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
  222. cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
  223. cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
  224. n += scnprintf(buf + n, len - n,
  225. "OS ABI [v3]\t: no-legacy-syscalls\n");
  226. return buf;
  227. }
  228. static void arc_chk_core_config(void)
  229. {
  230. struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
  231. int fpu_enabled;
  232. if (!cpu->timers.t0)
  233. panic("Timer0 is not present!\n");
  234. if (!cpu->timers.t1)
  235. panic("Timer1 is not present!\n");
  236. if (IS_ENABLED(CONFIG_ARC_HAS_RTC) && !cpu->timers.rtc)
  237. panic("RTC is not present\n");
  238. #ifdef CONFIG_ARC_HAS_DCCM
  239. /*
  240. * DCCM can be arbit placed in hardware.
  241. * Make sure it's placement/sz matches what Linux is built with
  242. */
  243. if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
  244. panic("Linux built with incorrect DCCM Base address\n");
  245. if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
  246. panic("Linux built with incorrect DCCM Size\n");
  247. #endif
  248. #ifdef CONFIG_ARC_HAS_ICCM
  249. if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
  250. panic("Linux built with incorrect ICCM Size\n");
  251. #endif
  252. /*
  253. * FP hardware/software config sanity
  254. * -If hardware contains DPFP, kernel needs to save/restore FPU state
  255. * -If not, it will crash trying to save/restore the non-existant regs
  256. *
  257. * (only DPDP checked since SP has no arch visible regs)
  258. */
  259. fpu_enabled = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
  260. if (cpu->extn.fpu_dp && !fpu_enabled)
  261. pr_warn("CONFIG_ARC_FPU_SAVE_RESTORE needed for working apps\n");
  262. else if (!cpu->extn.fpu_dp && fpu_enabled)
  263. panic("FPU non-existent, disable CONFIG_ARC_FPU_SAVE_RESTORE\n");
  264. }
  265. /*
  266. * Initialize and setup the processor core
  267. * This is called by all the CPUs thus should not do special case stuff
  268. * such as only for boot CPU etc
  269. */
  270. void setup_processor(void)
  271. {
  272. char str[512];
  273. int cpu_id = smp_processor_id();
  274. read_arc_build_cfg_regs();
  275. arc_init_IRQ();
  276. printk(arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
  277. arc_mmu_init();
  278. arc_cache_init();
  279. printk(arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
  280. printk(arc_platform_smp_cpuinfo());
  281. arc_chk_core_config();
  282. }
  283. static inline int is_kernel(unsigned long addr)
  284. {
  285. if (addr >= (unsigned long)_stext && addr <= (unsigned long)_end)
  286. return 1;
  287. return 0;
  288. }
  289. void __init setup_arch(char **cmdline_p)
  290. {
  291. #ifdef CONFIG_ARC_UBOOT_SUPPORT
  292. /* make sure that uboot passed pointer to cmdline/dtb is valid */
  293. if (uboot_tag && is_kernel((unsigned long)uboot_arg))
  294. panic("Invalid uboot arg\n");
  295. /* See if u-boot passed an external Device Tree blob */
  296. machine_desc = setup_machine_fdt(uboot_arg); /* uboot_tag == 2 */
  297. if (!machine_desc)
  298. #endif
  299. {
  300. /* No, so try the embedded one */
  301. machine_desc = setup_machine_fdt(__dtb_start);
  302. if (!machine_desc)
  303. panic("Embedded DT invalid\n");
  304. /*
  305. * If we are here, it is established that @uboot_arg didn't
  306. * point to DT blob. Instead if u-boot says it is cmdline,
  307. * Appent to embedded DT cmdline.
  308. * setup_machine_fdt() would have populated @boot_command_line
  309. */
  310. if (uboot_tag == 1) {
  311. /* Ensure a whitespace between the 2 cmdlines */
  312. strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
  313. strlcat(boot_command_line, uboot_arg,
  314. COMMAND_LINE_SIZE);
  315. }
  316. }
  317. /* Save unparsed command line copy for /proc/cmdline */
  318. *cmdline_p = boot_command_line;
  319. /* To force early parsing of things like mem=xxx */
  320. parse_early_param();
  321. /* Platform/board specific: e.g. early console registration */
  322. if (machine_desc->init_early)
  323. machine_desc->init_early();
  324. setup_processor();
  325. smp_init_cpus();
  326. setup_arch_memory();
  327. /* copy flat DT out of .init and then unflatten it */
  328. unflatten_and_copy_device_tree();
  329. /* Can be issue if someone passes cmd line arg "ro"
  330. * But that is unlikely so keeping it as it is
  331. */
  332. root_mountflags &= ~MS_RDONLY;
  333. #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
  334. conswitchp = &dummy_con;
  335. #endif
  336. arc_unwind_init();
  337. arc_unwind_setup();
  338. }
  339. static int __init customize_machine(void)
  340. {
  341. of_clk_init(NULL);
  342. /*
  343. * Traverses flattened DeviceTree - registering platform devices
  344. * (if any) complete with their resources
  345. */
  346. of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
  347. if (machine_desc->init_machine)
  348. machine_desc->init_machine();
  349. return 0;
  350. }
  351. arch_initcall(customize_machine);
  352. static int __init init_late_machine(void)
  353. {
  354. if (machine_desc->init_late)
  355. machine_desc->init_late();
  356. return 0;
  357. }
  358. late_initcall(init_late_machine);
  359. /*
  360. * Get CPU information for use by the procfs.
  361. */
  362. #define cpu_to_ptr(c) ((void *)(0xFFFF0000 | (unsigned int)(c)))
  363. #define ptr_to_cpu(p) (~0xFFFF0000UL & (unsigned int)(p))
  364. static int show_cpuinfo(struct seq_file *m, void *v)
  365. {
  366. char *str;
  367. int cpu_id = ptr_to_cpu(v);
  368. if (!cpu_online(cpu_id)) {
  369. seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
  370. goto done;
  371. }
  372. str = (char *)__get_free_page(GFP_TEMPORARY);
  373. if (!str)
  374. goto done;
  375. seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
  376. seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
  377. loops_per_jiffy / (500000 / HZ),
  378. (loops_per_jiffy / (5000 / HZ)) % 100);
  379. seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
  380. seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
  381. seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
  382. seq_printf(m, arc_platform_smp_cpuinfo());
  383. free_page((unsigned long)str);
  384. done:
  385. seq_printf(m, "\n");
  386. return 0;
  387. }
  388. static void *c_start(struct seq_file *m, loff_t *pos)
  389. {
  390. /*
  391. * Callback returns cpu-id to iterator for show routine, NULL to stop.
  392. * However since NULL is also a valid cpu-id (0), we use a round-about
  393. * way to pass it w/o having to kmalloc/free a 2 byte string.
  394. * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
  395. */
  396. return *pos < num_possible_cpus() ? cpu_to_ptr(*pos) : NULL;
  397. }
  398. static void *c_next(struct seq_file *m, void *v, loff_t *pos)
  399. {
  400. ++*pos;
  401. return c_start(m, pos);
  402. }
  403. static void c_stop(struct seq_file *m, void *v)
  404. {
  405. }
  406. const struct seq_operations cpuinfo_op = {
  407. .start = c_start,
  408. .next = c_next,
  409. .stop = c_stop,
  410. .show = show_cpuinfo
  411. };
  412. static DEFINE_PER_CPU(struct cpu, cpu_topology);
  413. static int __init topology_init(void)
  414. {
  415. int cpu;
  416. for_each_present_cpu(cpu)
  417. register_cpu(&per_cpu(cpu_topology, cpu), cpu);
  418. return 0;
  419. }
  420. subsys_initcall(topology_init);