gpio-tc3589x.c 8.2 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License, version 2
  5. * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
  6. * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
  7. */
  8. #include <linux/module.h>
  9. #include <linux/init.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/slab.h>
  12. #include <linux/gpio/driver.h>
  13. #include <linux/of.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/mfd/tc3589x.h>
  16. #include <linux/bitops.h>
  17. /*
  18. * These registers are modified under the irq bus lock and cached to avoid
  19. * unnecessary writes in bus_sync_unlock.
  20. */
  21. enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
  22. #define CACHE_NR_REGS 4
  23. #define CACHE_NR_BANKS 3
  24. struct tc3589x_gpio {
  25. struct gpio_chip chip;
  26. struct tc3589x *tc3589x;
  27. struct device *dev;
  28. struct mutex irq_lock;
  29. /* Caches of interrupt control registers for bus_lock */
  30. u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
  31. u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
  32. };
  33. static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned offset)
  34. {
  35. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  36. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  37. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  38. u8 mask = BIT(offset % 8);
  39. int ret;
  40. ret = tc3589x_reg_read(tc3589x, reg);
  41. if (ret < 0)
  42. return ret;
  43. return !!(ret & mask);
  44. }
  45. static void tc3589x_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
  46. {
  47. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  48. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  49. u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
  50. unsigned pos = offset % 8;
  51. u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
  52. tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
  53. }
  54. static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
  55. unsigned offset, int val)
  56. {
  57. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  58. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  59. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  60. unsigned pos = offset % 8;
  61. tc3589x_gpio_set(chip, offset, val);
  62. return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
  63. }
  64. static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
  65. unsigned offset)
  66. {
  67. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
  68. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  69. u8 reg = TC3589x_GPIODIR0 + offset / 8;
  70. unsigned pos = offset % 8;
  71. return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
  72. }
  73. static struct gpio_chip template_chip = {
  74. .label = "tc3589x",
  75. .owner = THIS_MODULE,
  76. .direction_input = tc3589x_gpio_direction_input,
  77. .get = tc3589x_gpio_get,
  78. .direction_output = tc3589x_gpio_direction_output,
  79. .set = tc3589x_gpio_set,
  80. .can_sleep = true,
  81. };
  82. static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  83. {
  84. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  85. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  86. int offset = d->hwirq;
  87. int regoffset = offset / 8;
  88. int mask = BIT(offset % 8);
  89. if (type == IRQ_TYPE_EDGE_BOTH) {
  90. tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
  91. return 0;
  92. }
  93. tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
  94. if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
  95. tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
  96. else
  97. tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
  98. if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
  99. tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
  100. else
  101. tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
  102. return 0;
  103. }
  104. static void tc3589x_gpio_irq_lock(struct irq_data *d)
  105. {
  106. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  107. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  108. mutex_lock(&tc3589x_gpio->irq_lock);
  109. }
  110. static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
  111. {
  112. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  113. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  114. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  115. static const u8 regmap[] = {
  116. [REG_IBE] = TC3589x_GPIOIBE0,
  117. [REG_IEV] = TC3589x_GPIOIEV0,
  118. [REG_IS] = TC3589x_GPIOIS0,
  119. [REG_IE] = TC3589x_GPIOIE0,
  120. };
  121. int i, j;
  122. for (i = 0; i < CACHE_NR_REGS; i++) {
  123. for (j = 0; j < CACHE_NR_BANKS; j++) {
  124. u8 old = tc3589x_gpio->oldregs[i][j];
  125. u8 new = tc3589x_gpio->regs[i][j];
  126. if (new == old)
  127. continue;
  128. tc3589x_gpio->oldregs[i][j] = new;
  129. tc3589x_reg_write(tc3589x, regmap[i] + j * 8, new);
  130. }
  131. }
  132. mutex_unlock(&tc3589x_gpio->irq_lock);
  133. }
  134. static void tc3589x_gpio_irq_mask(struct irq_data *d)
  135. {
  136. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  137. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  138. int offset = d->hwirq;
  139. int regoffset = offset / 8;
  140. int mask = BIT(offset % 8);
  141. tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
  142. }
  143. static void tc3589x_gpio_irq_unmask(struct irq_data *d)
  144. {
  145. struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  146. struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
  147. int offset = d->hwirq;
  148. int regoffset = offset / 8;
  149. int mask = BIT(offset % 8);
  150. tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
  151. }
  152. static struct irq_chip tc3589x_gpio_irq_chip = {
  153. .name = "tc3589x-gpio",
  154. .irq_bus_lock = tc3589x_gpio_irq_lock,
  155. .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
  156. .irq_mask = tc3589x_gpio_irq_mask,
  157. .irq_unmask = tc3589x_gpio_irq_unmask,
  158. .irq_set_type = tc3589x_gpio_irq_set_type,
  159. };
  160. static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
  161. {
  162. struct tc3589x_gpio *tc3589x_gpio = dev;
  163. struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
  164. u8 status[CACHE_NR_BANKS];
  165. int ret;
  166. int i;
  167. ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
  168. ARRAY_SIZE(status), status);
  169. if (ret < 0)
  170. return IRQ_NONE;
  171. for (i = 0; i < ARRAY_SIZE(status); i++) {
  172. unsigned int stat = status[i];
  173. if (!stat)
  174. continue;
  175. while (stat) {
  176. int bit = __ffs(stat);
  177. int line = i * 8 + bit;
  178. int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
  179. line);
  180. handle_nested_irq(irq);
  181. stat &= ~(1 << bit);
  182. }
  183. tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
  184. }
  185. return IRQ_HANDLED;
  186. }
  187. static int tc3589x_gpio_probe(struct platform_device *pdev)
  188. {
  189. struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
  190. struct device_node *np = pdev->dev.of_node;
  191. struct tc3589x_gpio *tc3589x_gpio;
  192. int ret;
  193. int irq;
  194. if (!np) {
  195. dev_err(&pdev->dev, "No Device Tree node found\n");
  196. return -EINVAL;
  197. }
  198. irq = platform_get_irq(pdev, 0);
  199. if (irq < 0)
  200. return irq;
  201. tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
  202. GFP_KERNEL);
  203. if (!tc3589x_gpio)
  204. return -ENOMEM;
  205. mutex_init(&tc3589x_gpio->irq_lock);
  206. tc3589x_gpio->dev = &pdev->dev;
  207. tc3589x_gpio->tc3589x = tc3589x;
  208. tc3589x_gpio->chip = template_chip;
  209. tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
  210. tc3589x_gpio->chip.parent = &pdev->dev;
  211. tc3589x_gpio->chip.base = -1;
  212. tc3589x_gpio->chip.of_node = np;
  213. /* Bring the GPIO module out of reset */
  214. ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
  215. TC3589x_RSTCTRL_GPIRST, 0);
  216. if (ret < 0)
  217. return ret;
  218. ret = devm_request_threaded_irq(&pdev->dev,
  219. irq, NULL, tc3589x_gpio_irq,
  220. IRQF_ONESHOT, "tc3589x-gpio",
  221. tc3589x_gpio);
  222. if (ret) {
  223. dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
  224. return ret;
  225. }
  226. ret = devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip,
  227. tc3589x_gpio);
  228. if (ret) {
  229. dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
  230. return ret;
  231. }
  232. ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
  233. &tc3589x_gpio_irq_chip,
  234. 0,
  235. handle_simple_irq,
  236. IRQ_TYPE_NONE);
  237. if (ret) {
  238. dev_err(&pdev->dev,
  239. "could not connect irqchip to gpiochip\n");
  240. return ret;
  241. }
  242. gpiochip_set_chained_irqchip(&tc3589x_gpio->chip,
  243. &tc3589x_gpio_irq_chip,
  244. irq,
  245. NULL);
  246. platform_set_drvdata(pdev, tc3589x_gpio);
  247. return 0;
  248. }
  249. static struct platform_driver tc3589x_gpio_driver = {
  250. .driver.name = "tc3589x-gpio",
  251. .driver.owner = THIS_MODULE,
  252. .probe = tc3589x_gpio_probe,
  253. };
  254. static int __init tc3589x_gpio_init(void)
  255. {
  256. return platform_driver_register(&tc3589x_gpio_driver);
  257. }
  258. subsys_initcall(tc3589x_gpio_init);
  259. static void __exit tc3589x_gpio_exit(void)
  260. {
  261. platform_driver_unregister(&tc3589x_gpio_driver);
  262. }
  263. module_exit(tc3589x_gpio_exit);
  264. MODULE_LICENSE("GPL v2");
  265. MODULE_DESCRIPTION("TC3589x GPIO driver");
  266. MODULE_AUTHOR("Hanumath Prasad, Rabin Vincent");