udc.c 45 KB

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  1. /*
  2. * udc.c - ChipIdea UDC driver
  3. *
  4. * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
  5. *
  6. * Author: David Lopo
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/delay.h>
  13. #include <linux/device.h>
  14. #include <linux/dmapool.h>
  15. #include <linux/err.h>
  16. #include <linux/irqreturn.h>
  17. #include <linux/kernel.h>
  18. #include <linux/slab.h>
  19. #include <linux/pm_runtime.h>
  20. #include <linux/usb/ch9.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/otg-fsm.h>
  23. #include <linux/usb/chipidea.h>
  24. #include "ci.h"
  25. #include "udc.h"
  26. #include "bits.h"
  27. #include "debug.h"
  28. #include "otg.h"
  29. #include "otg_fsm.h"
  30. /* control endpoint description */
  31. static const struct usb_endpoint_descriptor
  32. ctrl_endpt_out_desc = {
  33. .bLength = USB_DT_ENDPOINT_SIZE,
  34. .bDescriptorType = USB_DT_ENDPOINT,
  35. .bEndpointAddress = USB_DIR_OUT,
  36. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  37. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  38. };
  39. static const struct usb_endpoint_descriptor
  40. ctrl_endpt_in_desc = {
  41. .bLength = USB_DT_ENDPOINT_SIZE,
  42. .bDescriptorType = USB_DT_ENDPOINT,
  43. .bEndpointAddress = USB_DIR_IN,
  44. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  45. .wMaxPacketSize = cpu_to_le16(CTRL_PAYLOAD_MAX),
  46. };
  47. /**
  48. * hw_ep_bit: calculates the bit number
  49. * @num: endpoint number
  50. * @dir: endpoint direction
  51. *
  52. * This function returns bit number
  53. */
  54. static inline int hw_ep_bit(int num, int dir)
  55. {
  56. return num + (dir ? 16 : 0);
  57. }
  58. static inline int ep_to_bit(struct ci_hdrc *ci, int n)
  59. {
  60. int fill = 16 - ci->hw_ep_max / 2;
  61. if (n >= ci->hw_ep_max / 2)
  62. n += fill;
  63. return n;
  64. }
  65. /**
  66. * hw_device_state: enables/disables interrupts (execute without interruption)
  67. * @dma: 0 => disable, !0 => enable and set dma engine
  68. *
  69. * This function returns an error code
  70. */
  71. static int hw_device_state(struct ci_hdrc *ci, u32 dma)
  72. {
  73. if (dma) {
  74. hw_write(ci, OP_ENDPTLISTADDR, ~0, dma);
  75. /* interrupt, error, port change, reset, sleep/suspend */
  76. hw_write(ci, OP_USBINTR, ~0,
  77. USBi_UI|USBi_UEI|USBi_PCI|USBi_URI|USBi_SLI);
  78. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  79. } else {
  80. hw_write(ci, OP_USBINTR, ~0, 0);
  81. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  82. }
  83. return 0;
  84. }
  85. /**
  86. * hw_ep_flush: flush endpoint fifo (execute without interruption)
  87. * @num: endpoint number
  88. * @dir: endpoint direction
  89. *
  90. * This function returns an error code
  91. */
  92. static int hw_ep_flush(struct ci_hdrc *ci, int num, int dir)
  93. {
  94. int n = hw_ep_bit(num, dir);
  95. do {
  96. /* flush any pending transfer */
  97. hw_write(ci, OP_ENDPTFLUSH, ~0, BIT(n));
  98. while (hw_read(ci, OP_ENDPTFLUSH, BIT(n)))
  99. cpu_relax();
  100. } while (hw_read(ci, OP_ENDPTSTAT, BIT(n)));
  101. return 0;
  102. }
  103. /**
  104. * hw_ep_disable: disables endpoint (execute without interruption)
  105. * @num: endpoint number
  106. * @dir: endpoint direction
  107. *
  108. * This function returns an error code
  109. */
  110. static int hw_ep_disable(struct ci_hdrc *ci, int num, int dir)
  111. {
  112. hw_ep_flush(ci, num, dir);
  113. hw_write(ci, OP_ENDPTCTRL + num,
  114. dir ? ENDPTCTRL_TXE : ENDPTCTRL_RXE, 0);
  115. return 0;
  116. }
  117. /**
  118. * hw_ep_enable: enables endpoint (execute without interruption)
  119. * @num: endpoint number
  120. * @dir: endpoint direction
  121. * @type: endpoint type
  122. *
  123. * This function returns an error code
  124. */
  125. static int hw_ep_enable(struct ci_hdrc *ci, int num, int dir, int type)
  126. {
  127. u32 mask, data;
  128. if (dir) {
  129. mask = ENDPTCTRL_TXT; /* type */
  130. data = type << __ffs(mask);
  131. mask |= ENDPTCTRL_TXS; /* unstall */
  132. mask |= ENDPTCTRL_TXR; /* reset data toggle */
  133. data |= ENDPTCTRL_TXR;
  134. mask |= ENDPTCTRL_TXE; /* enable */
  135. data |= ENDPTCTRL_TXE;
  136. } else {
  137. mask = ENDPTCTRL_RXT; /* type */
  138. data = type << __ffs(mask);
  139. mask |= ENDPTCTRL_RXS; /* unstall */
  140. mask |= ENDPTCTRL_RXR; /* reset data toggle */
  141. data |= ENDPTCTRL_RXR;
  142. mask |= ENDPTCTRL_RXE; /* enable */
  143. data |= ENDPTCTRL_RXE;
  144. }
  145. hw_write(ci, OP_ENDPTCTRL + num, mask, data);
  146. return 0;
  147. }
  148. /**
  149. * hw_ep_get_halt: return endpoint halt status
  150. * @num: endpoint number
  151. * @dir: endpoint direction
  152. *
  153. * This function returns 1 if endpoint halted
  154. */
  155. static int hw_ep_get_halt(struct ci_hdrc *ci, int num, int dir)
  156. {
  157. u32 mask = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  158. return hw_read(ci, OP_ENDPTCTRL + num, mask) ? 1 : 0;
  159. }
  160. /**
  161. * hw_ep_prime: primes endpoint (execute without interruption)
  162. * @num: endpoint number
  163. * @dir: endpoint direction
  164. * @is_ctrl: true if control endpoint
  165. *
  166. * This function returns an error code
  167. */
  168. static int hw_ep_prime(struct ci_hdrc *ci, int num, int dir, int is_ctrl)
  169. {
  170. int n = hw_ep_bit(num, dir);
  171. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  172. return -EAGAIN;
  173. hw_write(ci, OP_ENDPTPRIME, ~0, BIT(n));
  174. while (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  175. cpu_relax();
  176. if (is_ctrl && dir == RX && hw_read(ci, OP_ENDPTSETUPSTAT, BIT(num)))
  177. return -EAGAIN;
  178. /* status shoult be tested according with manual but it doesn't work */
  179. return 0;
  180. }
  181. /**
  182. * hw_ep_set_halt: configures ep halt & resets data toggle after clear (execute
  183. * without interruption)
  184. * @num: endpoint number
  185. * @dir: endpoint direction
  186. * @value: true => stall, false => unstall
  187. *
  188. * This function returns an error code
  189. */
  190. static int hw_ep_set_halt(struct ci_hdrc *ci, int num, int dir, int value)
  191. {
  192. if (value != 0 && value != 1)
  193. return -EINVAL;
  194. do {
  195. enum ci_hw_regs reg = OP_ENDPTCTRL + num;
  196. u32 mask_xs = dir ? ENDPTCTRL_TXS : ENDPTCTRL_RXS;
  197. u32 mask_xr = dir ? ENDPTCTRL_TXR : ENDPTCTRL_RXR;
  198. /* data toggle - reserved for EP0 but it's in ESS */
  199. hw_write(ci, reg, mask_xs|mask_xr,
  200. value ? mask_xs : mask_xr);
  201. } while (value != hw_ep_get_halt(ci, num, dir));
  202. return 0;
  203. }
  204. /**
  205. * hw_is_port_high_speed: test if port is high speed
  206. *
  207. * This function returns true if high speed port
  208. */
  209. static int hw_port_is_high_speed(struct ci_hdrc *ci)
  210. {
  211. return ci->hw_bank.lpm ? hw_read(ci, OP_DEVLC, DEVLC_PSPD) :
  212. hw_read(ci, OP_PORTSC, PORTSC_HSP);
  213. }
  214. /**
  215. * hw_test_and_clear_complete: test & clear complete status (execute without
  216. * interruption)
  217. * @n: endpoint number
  218. *
  219. * This function returns complete status
  220. */
  221. static int hw_test_and_clear_complete(struct ci_hdrc *ci, int n)
  222. {
  223. n = ep_to_bit(ci, n);
  224. return hw_test_and_clear(ci, OP_ENDPTCOMPLETE, BIT(n));
  225. }
  226. /**
  227. * hw_test_and_clear_intr_active: test & clear active interrupts (execute
  228. * without interruption)
  229. *
  230. * This function returns active interrutps
  231. */
  232. static u32 hw_test_and_clear_intr_active(struct ci_hdrc *ci)
  233. {
  234. u32 reg = hw_read_intr_status(ci) & hw_read_intr_enable(ci);
  235. hw_write(ci, OP_USBSTS, ~0, reg);
  236. return reg;
  237. }
  238. /**
  239. * hw_test_and_clear_setup_guard: test & clear setup guard (execute without
  240. * interruption)
  241. *
  242. * This function returns guard value
  243. */
  244. static int hw_test_and_clear_setup_guard(struct ci_hdrc *ci)
  245. {
  246. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, 0);
  247. }
  248. /**
  249. * hw_test_and_set_setup_guard: test & set setup guard (execute without
  250. * interruption)
  251. *
  252. * This function returns guard value
  253. */
  254. static int hw_test_and_set_setup_guard(struct ci_hdrc *ci)
  255. {
  256. return hw_test_and_write(ci, OP_USBCMD, USBCMD_SUTW, USBCMD_SUTW);
  257. }
  258. /**
  259. * hw_usb_set_address: configures USB address (execute without interruption)
  260. * @value: new USB address
  261. *
  262. * This function explicitly sets the address, without the "USBADRA" (advance)
  263. * feature, which is not supported by older versions of the controller.
  264. */
  265. static void hw_usb_set_address(struct ci_hdrc *ci, u8 value)
  266. {
  267. hw_write(ci, OP_DEVICEADDR, DEVICEADDR_USBADR,
  268. value << __ffs(DEVICEADDR_USBADR));
  269. }
  270. /**
  271. * hw_usb_reset: restart device after a bus reset (execute without
  272. * interruption)
  273. *
  274. * This function returns an error code
  275. */
  276. static int hw_usb_reset(struct ci_hdrc *ci)
  277. {
  278. hw_usb_set_address(ci, 0);
  279. /* ESS flushes only at end?!? */
  280. hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
  281. /* clear setup token semaphores */
  282. hw_write(ci, OP_ENDPTSETUPSTAT, 0, 0);
  283. /* clear complete status */
  284. hw_write(ci, OP_ENDPTCOMPLETE, 0, 0);
  285. /* wait until all bits cleared */
  286. while (hw_read(ci, OP_ENDPTPRIME, ~0))
  287. udelay(10); /* not RTOS friendly */
  288. /* reset all endpoints ? */
  289. /* reset internal status and wait for further instructions
  290. no need to verify the port reset status (ESS does it) */
  291. return 0;
  292. }
  293. /******************************************************************************
  294. * UTIL block
  295. *****************************************************************************/
  296. static int add_td_to_list(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq,
  297. unsigned length)
  298. {
  299. int i;
  300. u32 temp;
  301. struct td_node *lastnode, *node = kzalloc(sizeof(struct td_node),
  302. GFP_ATOMIC);
  303. if (node == NULL)
  304. return -ENOMEM;
  305. node->ptr = dma_pool_alloc(hwep->td_pool, GFP_ATOMIC,
  306. &node->dma);
  307. if (node->ptr == NULL) {
  308. kfree(node);
  309. return -ENOMEM;
  310. }
  311. memset(node->ptr, 0, sizeof(struct ci_hw_td));
  312. node->ptr->token = cpu_to_le32(length << __ffs(TD_TOTAL_BYTES));
  313. node->ptr->token &= cpu_to_le32(TD_TOTAL_BYTES);
  314. node->ptr->token |= cpu_to_le32(TD_STATUS_ACTIVE);
  315. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX) {
  316. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  317. if (hwreq->req.length == 0
  318. || hwreq->req.length % hwep->ep.maxpacket)
  319. mul++;
  320. node->ptr->token |= mul << __ffs(TD_MULTO);
  321. }
  322. temp = (u32) (hwreq->req.dma + hwreq->req.actual);
  323. if (length) {
  324. node->ptr->page[0] = cpu_to_le32(temp);
  325. for (i = 1; i < TD_PAGE_COUNT; i++) {
  326. u32 page = temp + i * CI_HDRC_PAGE_SIZE;
  327. page &= ~TD_RESERVED_MASK;
  328. node->ptr->page[i] = cpu_to_le32(page);
  329. }
  330. }
  331. hwreq->req.actual += length;
  332. if (!list_empty(&hwreq->tds)) {
  333. /* get the last entry */
  334. lastnode = list_entry(hwreq->tds.prev,
  335. struct td_node, td);
  336. lastnode->ptr->next = cpu_to_le32(node->dma);
  337. }
  338. INIT_LIST_HEAD(&node->td);
  339. list_add_tail(&node->td, &hwreq->tds);
  340. return 0;
  341. }
  342. /**
  343. * _usb_addr: calculates endpoint address from direction & number
  344. * @ep: endpoint
  345. */
  346. static inline u8 _usb_addr(struct ci_hw_ep *ep)
  347. {
  348. return ((ep->dir == TX) ? USB_ENDPOINT_DIR_MASK : 0) | ep->num;
  349. }
  350. /**
  351. * _hardware_queue: configures a request at hardware level
  352. * @gadget: gadget
  353. * @hwep: endpoint
  354. *
  355. * This function returns an error code
  356. */
  357. static int _hardware_enqueue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  358. {
  359. struct ci_hdrc *ci = hwep->ci;
  360. int ret = 0;
  361. unsigned rest = hwreq->req.length;
  362. int pages = TD_PAGE_COUNT;
  363. struct td_node *firstnode, *lastnode;
  364. /* don't queue twice */
  365. if (hwreq->req.status == -EALREADY)
  366. return -EALREADY;
  367. hwreq->req.status = -EALREADY;
  368. ret = usb_gadget_map_request(&ci->gadget, &hwreq->req, hwep->dir);
  369. if (ret)
  370. return ret;
  371. /*
  372. * The first buffer could be not page aligned.
  373. * In that case we have to span into one extra td.
  374. */
  375. if (hwreq->req.dma % PAGE_SIZE)
  376. pages--;
  377. if (rest == 0)
  378. add_td_to_list(hwep, hwreq, 0);
  379. while (rest > 0) {
  380. unsigned count = min(hwreq->req.length - hwreq->req.actual,
  381. (unsigned)(pages * CI_HDRC_PAGE_SIZE));
  382. add_td_to_list(hwep, hwreq, count);
  383. rest -= count;
  384. }
  385. if (hwreq->req.zero && hwreq->req.length
  386. && (hwreq->req.length % hwep->ep.maxpacket == 0))
  387. add_td_to_list(hwep, hwreq, 0);
  388. firstnode = list_first_entry(&hwreq->tds, struct td_node, td);
  389. lastnode = list_entry(hwreq->tds.prev,
  390. struct td_node, td);
  391. lastnode->ptr->next = cpu_to_le32(TD_TERMINATE);
  392. if (!hwreq->req.no_interrupt)
  393. lastnode->ptr->token |= cpu_to_le32(TD_IOC);
  394. wmb();
  395. hwreq->req.actual = 0;
  396. if (!list_empty(&hwep->qh.queue)) {
  397. struct ci_hw_req *hwreqprev;
  398. int n = hw_ep_bit(hwep->num, hwep->dir);
  399. int tmp_stat;
  400. struct td_node *prevlastnode;
  401. u32 next = firstnode->dma & TD_ADDR_MASK;
  402. hwreqprev = list_entry(hwep->qh.queue.prev,
  403. struct ci_hw_req, queue);
  404. prevlastnode = list_entry(hwreqprev->tds.prev,
  405. struct td_node, td);
  406. prevlastnode->ptr->next = cpu_to_le32(next);
  407. wmb();
  408. if (hw_read(ci, OP_ENDPTPRIME, BIT(n)))
  409. goto done;
  410. do {
  411. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, USBCMD_ATDTW);
  412. tmp_stat = hw_read(ci, OP_ENDPTSTAT, BIT(n));
  413. } while (!hw_read(ci, OP_USBCMD, USBCMD_ATDTW));
  414. hw_write(ci, OP_USBCMD, USBCMD_ATDTW, 0);
  415. if (tmp_stat)
  416. goto done;
  417. }
  418. /* QH configuration */
  419. hwep->qh.ptr->td.next = cpu_to_le32(firstnode->dma);
  420. hwep->qh.ptr->td.token &=
  421. cpu_to_le32(~(TD_STATUS_HALTED|TD_STATUS_ACTIVE));
  422. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == RX) {
  423. u32 mul = hwreq->req.length / hwep->ep.maxpacket;
  424. if (hwreq->req.length == 0
  425. || hwreq->req.length % hwep->ep.maxpacket)
  426. mul++;
  427. hwep->qh.ptr->cap |= mul << __ffs(QH_MULT);
  428. }
  429. wmb(); /* synchronize before ep prime */
  430. ret = hw_ep_prime(ci, hwep->num, hwep->dir,
  431. hwep->type == USB_ENDPOINT_XFER_CONTROL);
  432. done:
  433. return ret;
  434. }
  435. /*
  436. * free_pending_td: remove a pending request for the endpoint
  437. * @hwep: endpoint
  438. */
  439. static void free_pending_td(struct ci_hw_ep *hwep)
  440. {
  441. struct td_node *pending = hwep->pending_td;
  442. dma_pool_free(hwep->td_pool, pending->ptr, pending->dma);
  443. hwep->pending_td = NULL;
  444. kfree(pending);
  445. }
  446. /**
  447. * _hardware_dequeue: handles a request at hardware level
  448. * @gadget: gadget
  449. * @hwep: endpoint
  450. *
  451. * This function returns an error code
  452. */
  453. static int _hardware_dequeue(struct ci_hw_ep *hwep, struct ci_hw_req *hwreq)
  454. {
  455. u32 tmptoken;
  456. struct td_node *node, *tmpnode;
  457. unsigned remaining_length;
  458. unsigned actual = hwreq->req.length;
  459. if (hwreq->req.status != -EALREADY)
  460. return -EINVAL;
  461. hwreq->req.status = 0;
  462. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  463. tmptoken = le32_to_cpu(node->ptr->token);
  464. if ((TD_STATUS_ACTIVE & tmptoken) != 0) {
  465. hwreq->req.status = -EALREADY;
  466. return -EBUSY;
  467. }
  468. remaining_length = (tmptoken & TD_TOTAL_BYTES);
  469. remaining_length >>= __ffs(TD_TOTAL_BYTES);
  470. actual -= remaining_length;
  471. hwreq->req.status = tmptoken & TD_STATUS;
  472. if ((TD_STATUS_HALTED & hwreq->req.status)) {
  473. hwreq->req.status = -EPIPE;
  474. break;
  475. } else if ((TD_STATUS_DT_ERR & hwreq->req.status)) {
  476. hwreq->req.status = -EPROTO;
  477. break;
  478. } else if ((TD_STATUS_TR_ERR & hwreq->req.status)) {
  479. hwreq->req.status = -EILSEQ;
  480. break;
  481. }
  482. if (remaining_length) {
  483. if (hwep->dir) {
  484. hwreq->req.status = -EPROTO;
  485. break;
  486. }
  487. }
  488. /*
  489. * As the hardware could still address the freed td
  490. * which will run the udc unusable, the cleanup of the
  491. * td has to be delayed by one.
  492. */
  493. if (hwep->pending_td)
  494. free_pending_td(hwep);
  495. hwep->pending_td = node;
  496. list_del_init(&node->td);
  497. }
  498. usb_gadget_unmap_request(&hwep->ci->gadget, &hwreq->req, hwep->dir);
  499. hwreq->req.actual += actual;
  500. if (hwreq->req.status)
  501. return hwreq->req.status;
  502. return hwreq->req.actual;
  503. }
  504. /**
  505. * _ep_nuke: dequeues all endpoint requests
  506. * @hwep: endpoint
  507. *
  508. * This function returns an error code
  509. * Caller must hold lock
  510. */
  511. static int _ep_nuke(struct ci_hw_ep *hwep)
  512. __releases(hwep->lock)
  513. __acquires(hwep->lock)
  514. {
  515. struct td_node *node, *tmpnode;
  516. if (hwep == NULL)
  517. return -EINVAL;
  518. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  519. while (!list_empty(&hwep->qh.queue)) {
  520. /* pop oldest request */
  521. struct ci_hw_req *hwreq = list_entry(hwep->qh.queue.next,
  522. struct ci_hw_req, queue);
  523. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  524. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  525. list_del_init(&node->td);
  526. node->ptr = NULL;
  527. kfree(node);
  528. }
  529. list_del_init(&hwreq->queue);
  530. hwreq->req.status = -ESHUTDOWN;
  531. if (hwreq->req.complete != NULL) {
  532. spin_unlock(hwep->lock);
  533. usb_gadget_giveback_request(&hwep->ep, &hwreq->req);
  534. spin_lock(hwep->lock);
  535. }
  536. }
  537. if (hwep->pending_td)
  538. free_pending_td(hwep);
  539. return 0;
  540. }
  541. /**
  542. * _gadget_stop_activity: stops all USB activity, flushes & disables all endpts
  543. * @gadget: gadget
  544. *
  545. * This function returns an error code
  546. */
  547. static int _gadget_stop_activity(struct usb_gadget *gadget)
  548. {
  549. struct usb_ep *ep;
  550. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  551. unsigned long flags;
  552. spin_lock_irqsave(&ci->lock, flags);
  553. ci->gadget.speed = USB_SPEED_UNKNOWN;
  554. ci->remote_wakeup = 0;
  555. ci->suspended = 0;
  556. spin_unlock_irqrestore(&ci->lock, flags);
  557. /* flush all endpoints */
  558. gadget_for_each_ep(ep, gadget) {
  559. usb_ep_fifo_flush(ep);
  560. }
  561. usb_ep_fifo_flush(&ci->ep0out->ep);
  562. usb_ep_fifo_flush(&ci->ep0in->ep);
  563. /* make sure to disable all endpoints */
  564. gadget_for_each_ep(ep, gadget) {
  565. usb_ep_disable(ep);
  566. }
  567. if (ci->status != NULL) {
  568. usb_ep_free_request(&ci->ep0in->ep, ci->status);
  569. ci->status = NULL;
  570. }
  571. return 0;
  572. }
  573. /******************************************************************************
  574. * ISR block
  575. *****************************************************************************/
  576. /**
  577. * isr_reset_handler: USB reset interrupt handler
  578. * @ci: UDC device
  579. *
  580. * This function resets USB engine after a bus reset occurred
  581. */
  582. static void isr_reset_handler(struct ci_hdrc *ci)
  583. __releases(ci->lock)
  584. __acquires(ci->lock)
  585. {
  586. int retval;
  587. spin_unlock(&ci->lock);
  588. if (ci->gadget.speed != USB_SPEED_UNKNOWN)
  589. usb_gadget_udc_reset(&ci->gadget, ci->driver);
  590. retval = _gadget_stop_activity(&ci->gadget);
  591. if (retval)
  592. goto done;
  593. retval = hw_usb_reset(ci);
  594. if (retval)
  595. goto done;
  596. ci->status = usb_ep_alloc_request(&ci->ep0in->ep, GFP_ATOMIC);
  597. if (ci->status == NULL)
  598. retval = -ENOMEM;
  599. done:
  600. spin_lock(&ci->lock);
  601. if (retval)
  602. dev_err(ci->dev, "error: %i\n", retval);
  603. }
  604. /**
  605. * isr_get_status_complete: get_status request complete function
  606. * @ep: endpoint
  607. * @req: request handled
  608. *
  609. * Caller must release lock
  610. */
  611. static void isr_get_status_complete(struct usb_ep *ep, struct usb_request *req)
  612. {
  613. if (ep == NULL || req == NULL)
  614. return;
  615. kfree(req->buf);
  616. usb_ep_free_request(ep, req);
  617. }
  618. /**
  619. * _ep_queue: queues (submits) an I/O request to an endpoint
  620. *
  621. * Caller must hold lock
  622. */
  623. static int _ep_queue(struct usb_ep *ep, struct usb_request *req,
  624. gfp_t __maybe_unused gfp_flags)
  625. {
  626. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  627. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  628. struct ci_hdrc *ci = hwep->ci;
  629. int retval = 0;
  630. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  631. return -EINVAL;
  632. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  633. if (req->length)
  634. hwep = (ci->ep0_dir == RX) ?
  635. ci->ep0out : ci->ep0in;
  636. if (!list_empty(&hwep->qh.queue)) {
  637. _ep_nuke(hwep);
  638. retval = -EOVERFLOW;
  639. dev_warn(hwep->ci->dev, "endpoint ctrl %X nuked\n",
  640. _usb_addr(hwep));
  641. }
  642. }
  643. if (usb_endpoint_xfer_isoc(hwep->ep.desc) &&
  644. hwreq->req.length > (1 + hwep->ep.mult) * hwep->ep.maxpacket) {
  645. dev_err(hwep->ci->dev, "request length too big for isochronous\n");
  646. return -EMSGSIZE;
  647. }
  648. /* first nuke then test link, e.g. previous status has not sent */
  649. if (!list_empty(&hwreq->queue)) {
  650. dev_err(hwep->ci->dev, "request already in queue\n");
  651. return -EBUSY;
  652. }
  653. /* push request */
  654. hwreq->req.status = -EINPROGRESS;
  655. hwreq->req.actual = 0;
  656. retval = _hardware_enqueue(hwep, hwreq);
  657. if (retval == -EALREADY)
  658. retval = 0;
  659. if (!retval)
  660. list_add_tail(&hwreq->queue, &hwep->qh.queue);
  661. return retval;
  662. }
  663. /**
  664. * isr_get_status_response: get_status request response
  665. * @ci: ci struct
  666. * @setup: setup request packet
  667. *
  668. * This function returns an error code
  669. */
  670. static int isr_get_status_response(struct ci_hdrc *ci,
  671. struct usb_ctrlrequest *setup)
  672. __releases(hwep->lock)
  673. __acquires(hwep->lock)
  674. {
  675. struct ci_hw_ep *hwep = ci->ep0in;
  676. struct usb_request *req = NULL;
  677. gfp_t gfp_flags = GFP_ATOMIC;
  678. int dir, num, retval;
  679. if (hwep == NULL || setup == NULL)
  680. return -EINVAL;
  681. spin_unlock(hwep->lock);
  682. req = usb_ep_alloc_request(&hwep->ep, gfp_flags);
  683. spin_lock(hwep->lock);
  684. if (req == NULL)
  685. return -ENOMEM;
  686. req->complete = isr_get_status_complete;
  687. req->length = 2;
  688. req->buf = kzalloc(req->length, gfp_flags);
  689. if (req->buf == NULL) {
  690. retval = -ENOMEM;
  691. goto err_free_req;
  692. }
  693. if ((setup->bRequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  694. *(u16 *)req->buf = (ci->remote_wakeup << 1) |
  695. ci->gadget.is_selfpowered;
  696. } else if ((setup->bRequestType & USB_RECIP_MASK) \
  697. == USB_RECIP_ENDPOINT) {
  698. dir = (le16_to_cpu(setup->wIndex) & USB_ENDPOINT_DIR_MASK) ?
  699. TX : RX;
  700. num = le16_to_cpu(setup->wIndex) & USB_ENDPOINT_NUMBER_MASK;
  701. *(u16 *)req->buf = hw_ep_get_halt(ci, num, dir);
  702. }
  703. /* else do nothing; reserved for future use */
  704. retval = _ep_queue(&hwep->ep, req, gfp_flags);
  705. if (retval)
  706. goto err_free_buf;
  707. return 0;
  708. err_free_buf:
  709. kfree(req->buf);
  710. err_free_req:
  711. spin_unlock(hwep->lock);
  712. usb_ep_free_request(&hwep->ep, req);
  713. spin_lock(hwep->lock);
  714. return retval;
  715. }
  716. /**
  717. * isr_setup_status_complete: setup_status request complete function
  718. * @ep: endpoint
  719. * @req: request handled
  720. *
  721. * Caller must release lock. Put the port in test mode if test mode
  722. * feature is selected.
  723. */
  724. static void
  725. isr_setup_status_complete(struct usb_ep *ep, struct usb_request *req)
  726. {
  727. struct ci_hdrc *ci = req->context;
  728. unsigned long flags;
  729. if (ci->setaddr) {
  730. hw_usb_set_address(ci, ci->address);
  731. ci->setaddr = false;
  732. if (ci->address)
  733. usb_gadget_set_state(&ci->gadget, USB_STATE_ADDRESS);
  734. }
  735. spin_lock_irqsave(&ci->lock, flags);
  736. if (ci->test_mode)
  737. hw_port_test_set(ci, ci->test_mode);
  738. spin_unlock_irqrestore(&ci->lock, flags);
  739. }
  740. /**
  741. * isr_setup_status_phase: queues the status phase of a setup transation
  742. * @ci: ci struct
  743. *
  744. * This function returns an error code
  745. */
  746. static int isr_setup_status_phase(struct ci_hdrc *ci)
  747. {
  748. int retval;
  749. struct ci_hw_ep *hwep;
  750. hwep = (ci->ep0_dir == TX) ? ci->ep0out : ci->ep0in;
  751. ci->status->context = ci;
  752. ci->status->complete = isr_setup_status_complete;
  753. retval = _ep_queue(&hwep->ep, ci->status, GFP_ATOMIC);
  754. return retval;
  755. }
  756. /**
  757. * isr_tr_complete_low: transaction complete low level handler
  758. * @hwep: endpoint
  759. *
  760. * This function returns an error code
  761. * Caller must hold lock
  762. */
  763. static int isr_tr_complete_low(struct ci_hw_ep *hwep)
  764. __releases(hwep->lock)
  765. __acquires(hwep->lock)
  766. {
  767. struct ci_hw_req *hwreq, *hwreqtemp;
  768. struct ci_hw_ep *hweptemp = hwep;
  769. int retval = 0;
  770. list_for_each_entry_safe(hwreq, hwreqtemp, &hwep->qh.queue,
  771. queue) {
  772. retval = _hardware_dequeue(hwep, hwreq);
  773. if (retval < 0)
  774. break;
  775. list_del_init(&hwreq->queue);
  776. if (hwreq->req.complete != NULL) {
  777. spin_unlock(hwep->lock);
  778. if ((hwep->type == USB_ENDPOINT_XFER_CONTROL) &&
  779. hwreq->req.length)
  780. hweptemp = hwep->ci->ep0in;
  781. usb_gadget_giveback_request(&hweptemp->ep, &hwreq->req);
  782. spin_lock(hwep->lock);
  783. }
  784. }
  785. if (retval == -EBUSY)
  786. retval = 0;
  787. return retval;
  788. }
  789. static int otg_a_alt_hnp_support(struct ci_hdrc *ci)
  790. {
  791. dev_warn(&ci->gadget.dev,
  792. "connect the device to an alternate port if you want HNP\n");
  793. return isr_setup_status_phase(ci);
  794. }
  795. /**
  796. * isr_setup_packet_handler: setup packet handler
  797. * @ci: UDC descriptor
  798. *
  799. * This function handles setup packet
  800. */
  801. static void isr_setup_packet_handler(struct ci_hdrc *ci)
  802. __releases(ci->lock)
  803. __acquires(ci->lock)
  804. {
  805. struct ci_hw_ep *hwep = &ci->ci_hw_ep[0];
  806. struct usb_ctrlrequest req;
  807. int type, num, dir, err = -EINVAL;
  808. u8 tmode = 0;
  809. /*
  810. * Flush data and handshake transactions of previous
  811. * setup packet.
  812. */
  813. _ep_nuke(ci->ep0out);
  814. _ep_nuke(ci->ep0in);
  815. /* read_setup_packet */
  816. do {
  817. hw_test_and_set_setup_guard(ci);
  818. memcpy(&req, &hwep->qh.ptr->setup, sizeof(req));
  819. } while (!hw_test_and_clear_setup_guard(ci));
  820. type = req.bRequestType;
  821. ci->ep0_dir = (type & USB_DIR_IN) ? TX : RX;
  822. switch (req.bRequest) {
  823. case USB_REQ_CLEAR_FEATURE:
  824. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  825. le16_to_cpu(req.wValue) ==
  826. USB_ENDPOINT_HALT) {
  827. if (req.wLength != 0)
  828. break;
  829. num = le16_to_cpu(req.wIndex);
  830. dir = num & USB_ENDPOINT_DIR_MASK;
  831. num &= USB_ENDPOINT_NUMBER_MASK;
  832. if (dir) /* TX */
  833. num += ci->hw_ep_max / 2;
  834. if (!ci->ci_hw_ep[num].wedge) {
  835. spin_unlock(&ci->lock);
  836. err = usb_ep_clear_halt(
  837. &ci->ci_hw_ep[num].ep);
  838. spin_lock(&ci->lock);
  839. if (err)
  840. break;
  841. }
  842. err = isr_setup_status_phase(ci);
  843. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE) &&
  844. le16_to_cpu(req.wValue) ==
  845. USB_DEVICE_REMOTE_WAKEUP) {
  846. if (req.wLength != 0)
  847. break;
  848. ci->remote_wakeup = 0;
  849. err = isr_setup_status_phase(ci);
  850. } else {
  851. goto delegate;
  852. }
  853. break;
  854. case USB_REQ_GET_STATUS:
  855. if (type != (USB_DIR_IN|USB_RECIP_DEVICE) &&
  856. type != (USB_DIR_IN|USB_RECIP_ENDPOINT) &&
  857. type != (USB_DIR_IN|USB_RECIP_INTERFACE))
  858. goto delegate;
  859. if (le16_to_cpu(req.wLength) != 2 ||
  860. le16_to_cpu(req.wValue) != 0)
  861. break;
  862. err = isr_get_status_response(ci, &req);
  863. break;
  864. case USB_REQ_SET_ADDRESS:
  865. if (type != (USB_DIR_OUT|USB_RECIP_DEVICE))
  866. goto delegate;
  867. if (le16_to_cpu(req.wLength) != 0 ||
  868. le16_to_cpu(req.wIndex) != 0)
  869. break;
  870. ci->address = (u8)le16_to_cpu(req.wValue);
  871. ci->setaddr = true;
  872. err = isr_setup_status_phase(ci);
  873. break;
  874. case USB_REQ_SET_FEATURE:
  875. if (type == (USB_DIR_OUT|USB_RECIP_ENDPOINT) &&
  876. le16_to_cpu(req.wValue) ==
  877. USB_ENDPOINT_HALT) {
  878. if (req.wLength != 0)
  879. break;
  880. num = le16_to_cpu(req.wIndex);
  881. dir = num & USB_ENDPOINT_DIR_MASK;
  882. num &= USB_ENDPOINT_NUMBER_MASK;
  883. if (dir) /* TX */
  884. num += ci->hw_ep_max / 2;
  885. spin_unlock(&ci->lock);
  886. err = usb_ep_set_halt(&ci->ci_hw_ep[num].ep);
  887. spin_lock(&ci->lock);
  888. if (!err)
  889. isr_setup_status_phase(ci);
  890. } else if (type == (USB_DIR_OUT|USB_RECIP_DEVICE)) {
  891. if (req.wLength != 0)
  892. break;
  893. switch (le16_to_cpu(req.wValue)) {
  894. case USB_DEVICE_REMOTE_WAKEUP:
  895. ci->remote_wakeup = 1;
  896. err = isr_setup_status_phase(ci);
  897. break;
  898. case USB_DEVICE_TEST_MODE:
  899. tmode = le16_to_cpu(req.wIndex) >> 8;
  900. switch (tmode) {
  901. case TEST_J:
  902. case TEST_K:
  903. case TEST_SE0_NAK:
  904. case TEST_PACKET:
  905. case TEST_FORCE_EN:
  906. ci->test_mode = tmode;
  907. err = isr_setup_status_phase(
  908. ci);
  909. break;
  910. default:
  911. break;
  912. }
  913. break;
  914. case USB_DEVICE_B_HNP_ENABLE:
  915. if (ci_otg_is_fsm_mode(ci)) {
  916. ci->gadget.b_hnp_enable = 1;
  917. err = isr_setup_status_phase(
  918. ci);
  919. }
  920. break;
  921. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  922. if (ci_otg_is_fsm_mode(ci))
  923. err = otg_a_alt_hnp_support(ci);
  924. break;
  925. default:
  926. goto delegate;
  927. }
  928. } else {
  929. goto delegate;
  930. }
  931. break;
  932. default:
  933. delegate:
  934. if (req.wLength == 0) /* no data phase */
  935. ci->ep0_dir = TX;
  936. spin_unlock(&ci->lock);
  937. err = ci->driver->setup(&ci->gadget, &req);
  938. spin_lock(&ci->lock);
  939. break;
  940. }
  941. if (err < 0) {
  942. spin_unlock(&ci->lock);
  943. if (usb_ep_set_halt(&hwep->ep))
  944. dev_err(ci->dev, "error: ep_set_halt\n");
  945. spin_lock(&ci->lock);
  946. }
  947. }
  948. /**
  949. * isr_tr_complete_handler: transaction complete interrupt handler
  950. * @ci: UDC descriptor
  951. *
  952. * This function handles traffic events
  953. */
  954. static void isr_tr_complete_handler(struct ci_hdrc *ci)
  955. __releases(ci->lock)
  956. __acquires(ci->lock)
  957. {
  958. unsigned i;
  959. int err;
  960. for (i = 0; i < ci->hw_ep_max; i++) {
  961. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  962. if (hwep->ep.desc == NULL)
  963. continue; /* not configured */
  964. if (hw_test_and_clear_complete(ci, i)) {
  965. err = isr_tr_complete_low(hwep);
  966. if (hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  967. if (err > 0) /* needs status phase */
  968. err = isr_setup_status_phase(ci);
  969. if (err < 0) {
  970. spin_unlock(&ci->lock);
  971. if (usb_ep_set_halt(&hwep->ep))
  972. dev_err(ci->dev,
  973. "error: ep_set_halt\n");
  974. spin_lock(&ci->lock);
  975. }
  976. }
  977. }
  978. /* Only handle setup packet below */
  979. if (i == 0 &&
  980. hw_test_and_clear(ci, OP_ENDPTSETUPSTAT, BIT(0)))
  981. isr_setup_packet_handler(ci);
  982. }
  983. }
  984. /******************************************************************************
  985. * ENDPT block
  986. *****************************************************************************/
  987. /**
  988. * ep_enable: configure endpoint, making it usable
  989. *
  990. * Check usb_ep_enable() at "usb_gadget.h" for details
  991. */
  992. static int ep_enable(struct usb_ep *ep,
  993. const struct usb_endpoint_descriptor *desc)
  994. {
  995. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  996. int retval = 0;
  997. unsigned long flags;
  998. u32 cap = 0;
  999. if (ep == NULL || desc == NULL)
  1000. return -EINVAL;
  1001. spin_lock_irqsave(hwep->lock, flags);
  1002. /* only internal SW should enable ctrl endpts */
  1003. hwep->ep.desc = desc;
  1004. if (!list_empty(&hwep->qh.queue))
  1005. dev_warn(hwep->ci->dev, "enabling a non-empty endpoint!\n");
  1006. hwep->dir = usb_endpoint_dir_in(desc) ? TX : RX;
  1007. hwep->num = usb_endpoint_num(desc);
  1008. hwep->type = usb_endpoint_type(desc);
  1009. hwep->ep.maxpacket = usb_endpoint_maxp(desc) & 0x07ff;
  1010. hwep->ep.mult = QH_ISO_MULT(usb_endpoint_maxp(desc));
  1011. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1012. cap |= QH_IOS;
  1013. cap |= QH_ZLT;
  1014. cap |= (hwep->ep.maxpacket << __ffs(QH_MAX_PKT)) & QH_MAX_PKT;
  1015. /*
  1016. * For ISO-TX, we set mult at QH as the largest value, and use
  1017. * MultO at TD as real mult value.
  1018. */
  1019. if (hwep->type == USB_ENDPOINT_XFER_ISOC && hwep->dir == TX)
  1020. cap |= 3 << __ffs(QH_MULT);
  1021. hwep->qh.ptr->cap = cpu_to_le32(cap);
  1022. hwep->qh.ptr->td.next |= cpu_to_le32(TD_TERMINATE); /* needed? */
  1023. if (hwep->num != 0 && hwep->type == USB_ENDPOINT_XFER_CONTROL) {
  1024. dev_err(hwep->ci->dev, "Set control xfer at non-ep0\n");
  1025. retval = -EINVAL;
  1026. }
  1027. /*
  1028. * Enable endpoints in the HW other than ep0 as ep0
  1029. * is always enabled
  1030. */
  1031. if (hwep->num)
  1032. retval |= hw_ep_enable(hwep->ci, hwep->num, hwep->dir,
  1033. hwep->type);
  1034. spin_unlock_irqrestore(hwep->lock, flags);
  1035. return retval;
  1036. }
  1037. /**
  1038. * ep_disable: endpoint is no longer usable
  1039. *
  1040. * Check usb_ep_disable() at "usb_gadget.h" for details
  1041. */
  1042. static int ep_disable(struct usb_ep *ep)
  1043. {
  1044. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1045. int direction, retval = 0;
  1046. unsigned long flags;
  1047. if (ep == NULL)
  1048. return -EINVAL;
  1049. else if (hwep->ep.desc == NULL)
  1050. return -EBUSY;
  1051. spin_lock_irqsave(hwep->lock, flags);
  1052. /* only internal SW should disable ctrl endpts */
  1053. direction = hwep->dir;
  1054. do {
  1055. retval |= _ep_nuke(hwep);
  1056. retval |= hw_ep_disable(hwep->ci, hwep->num, hwep->dir);
  1057. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1058. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1059. } while (hwep->dir != direction);
  1060. hwep->ep.desc = NULL;
  1061. spin_unlock_irqrestore(hwep->lock, flags);
  1062. return retval;
  1063. }
  1064. /**
  1065. * ep_alloc_request: allocate a request object to use with this endpoint
  1066. *
  1067. * Check usb_ep_alloc_request() at "usb_gadget.h" for details
  1068. */
  1069. static struct usb_request *ep_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
  1070. {
  1071. struct ci_hw_req *hwreq = NULL;
  1072. if (ep == NULL)
  1073. return NULL;
  1074. hwreq = kzalloc(sizeof(struct ci_hw_req), gfp_flags);
  1075. if (hwreq != NULL) {
  1076. INIT_LIST_HEAD(&hwreq->queue);
  1077. INIT_LIST_HEAD(&hwreq->tds);
  1078. }
  1079. return (hwreq == NULL) ? NULL : &hwreq->req;
  1080. }
  1081. /**
  1082. * ep_free_request: frees a request object
  1083. *
  1084. * Check usb_ep_free_request() at "usb_gadget.h" for details
  1085. */
  1086. static void ep_free_request(struct usb_ep *ep, struct usb_request *req)
  1087. {
  1088. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1089. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1090. struct td_node *node, *tmpnode;
  1091. unsigned long flags;
  1092. if (ep == NULL || req == NULL) {
  1093. return;
  1094. } else if (!list_empty(&hwreq->queue)) {
  1095. dev_err(hwep->ci->dev, "freeing queued request\n");
  1096. return;
  1097. }
  1098. spin_lock_irqsave(hwep->lock, flags);
  1099. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1100. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1101. list_del_init(&node->td);
  1102. node->ptr = NULL;
  1103. kfree(node);
  1104. }
  1105. kfree(hwreq);
  1106. spin_unlock_irqrestore(hwep->lock, flags);
  1107. }
  1108. /**
  1109. * ep_queue: queues (submits) an I/O request to an endpoint
  1110. *
  1111. * Check usb_ep_queue()* at usb_gadget.h" for details
  1112. */
  1113. static int ep_queue(struct usb_ep *ep, struct usb_request *req,
  1114. gfp_t __maybe_unused gfp_flags)
  1115. {
  1116. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1117. int retval = 0;
  1118. unsigned long flags;
  1119. if (ep == NULL || req == NULL || hwep->ep.desc == NULL)
  1120. return -EINVAL;
  1121. spin_lock_irqsave(hwep->lock, flags);
  1122. retval = _ep_queue(ep, req, gfp_flags);
  1123. spin_unlock_irqrestore(hwep->lock, flags);
  1124. return retval;
  1125. }
  1126. /**
  1127. * ep_dequeue: dequeues (cancels, unlinks) an I/O request from an endpoint
  1128. *
  1129. * Check usb_ep_dequeue() at "usb_gadget.h" for details
  1130. */
  1131. static int ep_dequeue(struct usb_ep *ep, struct usb_request *req)
  1132. {
  1133. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1134. struct ci_hw_req *hwreq = container_of(req, struct ci_hw_req, req);
  1135. unsigned long flags;
  1136. struct td_node *node, *tmpnode;
  1137. if (ep == NULL || req == NULL || hwreq->req.status != -EALREADY ||
  1138. hwep->ep.desc == NULL || list_empty(&hwreq->queue) ||
  1139. list_empty(&hwep->qh.queue))
  1140. return -EINVAL;
  1141. spin_lock_irqsave(hwep->lock, flags);
  1142. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1143. list_for_each_entry_safe(node, tmpnode, &hwreq->tds, td) {
  1144. dma_pool_free(hwep->td_pool, node->ptr, node->dma);
  1145. list_del(&node->td);
  1146. kfree(node);
  1147. }
  1148. /* pop request */
  1149. list_del_init(&hwreq->queue);
  1150. usb_gadget_unmap_request(&hwep->ci->gadget, req, hwep->dir);
  1151. req->status = -ECONNRESET;
  1152. if (hwreq->req.complete != NULL) {
  1153. spin_unlock(hwep->lock);
  1154. usb_gadget_giveback_request(&hwep->ep, &hwreq->req);
  1155. spin_lock(hwep->lock);
  1156. }
  1157. spin_unlock_irqrestore(hwep->lock, flags);
  1158. return 0;
  1159. }
  1160. /**
  1161. * ep_set_halt: sets the endpoint halt feature
  1162. *
  1163. * Check usb_ep_set_halt() at "usb_gadget.h" for details
  1164. */
  1165. static int ep_set_halt(struct usb_ep *ep, int value)
  1166. {
  1167. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1168. int direction, retval = 0;
  1169. unsigned long flags;
  1170. if (ep == NULL || hwep->ep.desc == NULL)
  1171. return -EINVAL;
  1172. if (usb_endpoint_xfer_isoc(hwep->ep.desc))
  1173. return -EOPNOTSUPP;
  1174. spin_lock_irqsave(hwep->lock, flags);
  1175. #ifndef STALL_IN
  1176. /* g_file_storage MS compliant but g_zero fails chapter 9 compliance */
  1177. if (value && hwep->type == USB_ENDPOINT_XFER_BULK && hwep->dir == TX &&
  1178. !list_empty(&hwep->qh.queue)) {
  1179. spin_unlock_irqrestore(hwep->lock, flags);
  1180. return -EAGAIN;
  1181. }
  1182. #endif
  1183. direction = hwep->dir;
  1184. do {
  1185. retval |= hw_ep_set_halt(hwep->ci, hwep->num, hwep->dir, value);
  1186. if (!value)
  1187. hwep->wedge = 0;
  1188. if (hwep->type == USB_ENDPOINT_XFER_CONTROL)
  1189. hwep->dir = (hwep->dir == TX) ? RX : TX;
  1190. } while (hwep->dir != direction);
  1191. spin_unlock_irqrestore(hwep->lock, flags);
  1192. return retval;
  1193. }
  1194. /**
  1195. * ep_set_wedge: sets the halt feature and ignores clear requests
  1196. *
  1197. * Check usb_ep_set_wedge() at "usb_gadget.h" for details
  1198. */
  1199. static int ep_set_wedge(struct usb_ep *ep)
  1200. {
  1201. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1202. unsigned long flags;
  1203. if (ep == NULL || hwep->ep.desc == NULL)
  1204. return -EINVAL;
  1205. spin_lock_irqsave(hwep->lock, flags);
  1206. hwep->wedge = 1;
  1207. spin_unlock_irqrestore(hwep->lock, flags);
  1208. return usb_ep_set_halt(ep);
  1209. }
  1210. /**
  1211. * ep_fifo_flush: flushes contents of a fifo
  1212. *
  1213. * Check usb_ep_fifo_flush() at "usb_gadget.h" for details
  1214. */
  1215. static void ep_fifo_flush(struct usb_ep *ep)
  1216. {
  1217. struct ci_hw_ep *hwep = container_of(ep, struct ci_hw_ep, ep);
  1218. unsigned long flags;
  1219. if (ep == NULL) {
  1220. dev_err(hwep->ci->dev, "%02X: -EINVAL\n", _usb_addr(hwep));
  1221. return;
  1222. }
  1223. spin_lock_irqsave(hwep->lock, flags);
  1224. hw_ep_flush(hwep->ci, hwep->num, hwep->dir);
  1225. spin_unlock_irqrestore(hwep->lock, flags);
  1226. }
  1227. /**
  1228. * Endpoint-specific part of the API to the USB controller hardware
  1229. * Check "usb_gadget.h" for details
  1230. */
  1231. static const struct usb_ep_ops usb_ep_ops = {
  1232. .enable = ep_enable,
  1233. .disable = ep_disable,
  1234. .alloc_request = ep_alloc_request,
  1235. .free_request = ep_free_request,
  1236. .queue = ep_queue,
  1237. .dequeue = ep_dequeue,
  1238. .set_halt = ep_set_halt,
  1239. .set_wedge = ep_set_wedge,
  1240. .fifo_flush = ep_fifo_flush,
  1241. };
  1242. /******************************************************************************
  1243. * GADGET block
  1244. *****************************************************************************/
  1245. static int ci_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
  1246. {
  1247. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1248. unsigned long flags;
  1249. int gadget_ready = 0;
  1250. spin_lock_irqsave(&ci->lock, flags);
  1251. ci->vbus_active = is_active;
  1252. if (ci->driver)
  1253. gadget_ready = 1;
  1254. spin_unlock_irqrestore(&ci->lock, flags);
  1255. if (gadget_ready) {
  1256. if (is_active) {
  1257. pm_runtime_get_sync(&_gadget->dev);
  1258. hw_device_reset(ci);
  1259. hw_device_state(ci, ci->ep0out->qh.dma);
  1260. usb_gadget_set_state(_gadget, USB_STATE_POWERED);
  1261. } else {
  1262. if (ci->driver)
  1263. ci->driver->disconnect(&ci->gadget);
  1264. hw_device_state(ci, 0);
  1265. if (ci->platdata->notify_event)
  1266. ci->platdata->notify_event(ci,
  1267. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1268. _gadget_stop_activity(&ci->gadget);
  1269. pm_runtime_put_sync(&_gadget->dev);
  1270. usb_gadget_set_state(_gadget, USB_STATE_NOTATTACHED);
  1271. }
  1272. }
  1273. return 0;
  1274. }
  1275. static int ci_udc_wakeup(struct usb_gadget *_gadget)
  1276. {
  1277. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1278. unsigned long flags;
  1279. int ret = 0;
  1280. spin_lock_irqsave(&ci->lock, flags);
  1281. if (!ci->remote_wakeup) {
  1282. ret = -EOPNOTSUPP;
  1283. goto out;
  1284. }
  1285. if (!hw_read(ci, OP_PORTSC, PORTSC_SUSP)) {
  1286. ret = -EINVAL;
  1287. goto out;
  1288. }
  1289. hw_write(ci, OP_PORTSC, PORTSC_FPR, PORTSC_FPR);
  1290. out:
  1291. spin_unlock_irqrestore(&ci->lock, flags);
  1292. return ret;
  1293. }
  1294. static int ci_udc_vbus_draw(struct usb_gadget *_gadget, unsigned ma)
  1295. {
  1296. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1297. if (ci->usb_phy)
  1298. return usb_phy_set_power(ci->usb_phy, ma);
  1299. return -ENOTSUPP;
  1300. }
  1301. static int ci_udc_selfpowered(struct usb_gadget *_gadget, int is_on)
  1302. {
  1303. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1304. struct ci_hw_ep *hwep = ci->ep0in;
  1305. unsigned long flags;
  1306. spin_lock_irqsave(hwep->lock, flags);
  1307. _gadget->is_selfpowered = (is_on != 0);
  1308. spin_unlock_irqrestore(hwep->lock, flags);
  1309. return 0;
  1310. }
  1311. /* Change Data+ pullup status
  1312. * this func is used by usb_gadget_connect/disconnet
  1313. */
  1314. static int ci_udc_pullup(struct usb_gadget *_gadget, int is_on)
  1315. {
  1316. struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
  1317. if (!ci->vbus_active)
  1318. return -EOPNOTSUPP;
  1319. if (is_on)
  1320. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  1321. else
  1322. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  1323. return 0;
  1324. }
  1325. static int ci_udc_start(struct usb_gadget *gadget,
  1326. struct usb_gadget_driver *driver);
  1327. static int ci_udc_stop(struct usb_gadget *gadget);
  1328. /**
  1329. * Device operations part of the API to the USB controller hardware,
  1330. * which don't involve endpoints (or i/o)
  1331. * Check "usb_gadget.h" for details
  1332. */
  1333. static const struct usb_gadget_ops usb_gadget_ops = {
  1334. .vbus_session = ci_udc_vbus_session,
  1335. .wakeup = ci_udc_wakeup,
  1336. .set_selfpowered = ci_udc_selfpowered,
  1337. .pullup = ci_udc_pullup,
  1338. .vbus_draw = ci_udc_vbus_draw,
  1339. .udc_start = ci_udc_start,
  1340. .udc_stop = ci_udc_stop,
  1341. };
  1342. static int init_eps(struct ci_hdrc *ci)
  1343. {
  1344. int retval = 0, i, j;
  1345. for (i = 0; i < ci->hw_ep_max/2; i++)
  1346. for (j = RX; j <= TX; j++) {
  1347. int k = i + j * ci->hw_ep_max/2;
  1348. struct ci_hw_ep *hwep = &ci->ci_hw_ep[k];
  1349. scnprintf(hwep->name, sizeof(hwep->name), "ep%i%s", i,
  1350. (j == TX) ? "in" : "out");
  1351. hwep->ci = ci;
  1352. hwep->lock = &ci->lock;
  1353. hwep->td_pool = ci->td_pool;
  1354. hwep->ep.name = hwep->name;
  1355. hwep->ep.ops = &usb_ep_ops;
  1356. /*
  1357. * for ep0: maxP defined in desc, for other
  1358. * eps, maxP is set by epautoconfig() called
  1359. * by gadget layer
  1360. */
  1361. usb_ep_set_maxpacket_limit(&hwep->ep, (unsigned short)~0);
  1362. INIT_LIST_HEAD(&hwep->qh.queue);
  1363. hwep->qh.ptr = dma_pool_alloc(ci->qh_pool, GFP_KERNEL,
  1364. &hwep->qh.dma);
  1365. if (hwep->qh.ptr == NULL)
  1366. retval = -ENOMEM;
  1367. else
  1368. memset(hwep->qh.ptr, 0, sizeof(*hwep->qh.ptr));
  1369. /*
  1370. * set up shorthands for ep0 out and in endpoints,
  1371. * don't add to gadget's ep_list
  1372. */
  1373. if (i == 0) {
  1374. if (j == RX)
  1375. ci->ep0out = hwep;
  1376. else
  1377. ci->ep0in = hwep;
  1378. usb_ep_set_maxpacket_limit(&hwep->ep, CTRL_PAYLOAD_MAX);
  1379. continue;
  1380. }
  1381. list_add_tail(&hwep->ep.ep_list, &ci->gadget.ep_list);
  1382. }
  1383. return retval;
  1384. }
  1385. static void destroy_eps(struct ci_hdrc *ci)
  1386. {
  1387. int i;
  1388. for (i = 0; i < ci->hw_ep_max; i++) {
  1389. struct ci_hw_ep *hwep = &ci->ci_hw_ep[i];
  1390. if (hwep->pending_td)
  1391. free_pending_td(hwep);
  1392. dma_pool_free(ci->qh_pool, hwep->qh.ptr, hwep->qh.dma);
  1393. }
  1394. }
  1395. /**
  1396. * ci_udc_start: register a gadget driver
  1397. * @gadget: our gadget
  1398. * @driver: the driver being registered
  1399. *
  1400. * Interrupts are enabled here.
  1401. */
  1402. static int ci_udc_start(struct usb_gadget *gadget,
  1403. struct usb_gadget_driver *driver)
  1404. {
  1405. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1406. unsigned long flags;
  1407. int retval = -ENOMEM;
  1408. if (driver->disconnect == NULL)
  1409. return -EINVAL;
  1410. ci->ep0out->ep.desc = &ctrl_endpt_out_desc;
  1411. retval = usb_ep_enable(&ci->ep0out->ep);
  1412. if (retval)
  1413. return retval;
  1414. ci->ep0in->ep.desc = &ctrl_endpt_in_desc;
  1415. retval = usb_ep_enable(&ci->ep0in->ep);
  1416. if (retval)
  1417. return retval;
  1418. ci->driver = driver;
  1419. /* Start otg fsm for B-device */
  1420. if (ci_otg_is_fsm_mode(ci) && ci->fsm.id) {
  1421. ci_hdrc_otg_fsm_start(ci);
  1422. return retval;
  1423. }
  1424. pm_runtime_get_sync(&ci->gadget.dev);
  1425. if (ci->vbus_active) {
  1426. spin_lock_irqsave(&ci->lock, flags);
  1427. hw_device_reset(ci);
  1428. } else {
  1429. pm_runtime_put_sync(&ci->gadget.dev);
  1430. return retval;
  1431. }
  1432. retval = hw_device_state(ci, ci->ep0out->qh.dma);
  1433. spin_unlock_irqrestore(&ci->lock, flags);
  1434. if (retval)
  1435. pm_runtime_put_sync(&ci->gadget.dev);
  1436. return retval;
  1437. }
  1438. /**
  1439. * ci_udc_stop: unregister a gadget driver
  1440. */
  1441. static int ci_udc_stop(struct usb_gadget *gadget)
  1442. {
  1443. struct ci_hdrc *ci = container_of(gadget, struct ci_hdrc, gadget);
  1444. unsigned long flags;
  1445. spin_lock_irqsave(&ci->lock, flags);
  1446. if (ci->vbus_active) {
  1447. hw_device_state(ci, 0);
  1448. if (ci->platdata->notify_event)
  1449. ci->platdata->notify_event(ci,
  1450. CI_HDRC_CONTROLLER_STOPPED_EVENT);
  1451. spin_unlock_irqrestore(&ci->lock, flags);
  1452. _gadget_stop_activity(&ci->gadget);
  1453. spin_lock_irqsave(&ci->lock, flags);
  1454. pm_runtime_put(&ci->gadget.dev);
  1455. }
  1456. ci->driver = NULL;
  1457. spin_unlock_irqrestore(&ci->lock, flags);
  1458. return 0;
  1459. }
  1460. /******************************************************************************
  1461. * BUS block
  1462. *****************************************************************************/
  1463. /**
  1464. * udc_irq: ci interrupt handler
  1465. *
  1466. * This function returns IRQ_HANDLED if the IRQ has been handled
  1467. * It locks access to registers
  1468. */
  1469. static irqreturn_t udc_irq(struct ci_hdrc *ci)
  1470. {
  1471. irqreturn_t retval;
  1472. u32 intr;
  1473. if (ci == NULL)
  1474. return IRQ_HANDLED;
  1475. spin_lock(&ci->lock);
  1476. if (ci->platdata->flags & CI_HDRC_REGS_SHARED) {
  1477. if (hw_read(ci, OP_USBMODE, USBMODE_CM) !=
  1478. USBMODE_CM_DC) {
  1479. spin_unlock(&ci->lock);
  1480. return IRQ_NONE;
  1481. }
  1482. }
  1483. intr = hw_test_and_clear_intr_active(ci);
  1484. if (intr) {
  1485. /* order defines priority - do NOT change it */
  1486. if (USBi_URI & intr)
  1487. isr_reset_handler(ci);
  1488. if (USBi_PCI & intr) {
  1489. ci->gadget.speed = hw_port_is_high_speed(ci) ?
  1490. USB_SPEED_HIGH : USB_SPEED_FULL;
  1491. if (ci->suspended && ci->driver->resume) {
  1492. spin_unlock(&ci->lock);
  1493. ci->driver->resume(&ci->gadget);
  1494. spin_lock(&ci->lock);
  1495. ci->suspended = 0;
  1496. }
  1497. }
  1498. if (USBi_UI & intr)
  1499. isr_tr_complete_handler(ci);
  1500. if (USBi_SLI & intr) {
  1501. if (ci->gadget.speed != USB_SPEED_UNKNOWN &&
  1502. ci->driver->suspend) {
  1503. ci->suspended = 1;
  1504. spin_unlock(&ci->lock);
  1505. ci->driver->suspend(&ci->gadget);
  1506. usb_gadget_set_state(&ci->gadget,
  1507. USB_STATE_SUSPENDED);
  1508. spin_lock(&ci->lock);
  1509. }
  1510. }
  1511. retval = IRQ_HANDLED;
  1512. } else {
  1513. retval = IRQ_NONE;
  1514. }
  1515. spin_unlock(&ci->lock);
  1516. return retval;
  1517. }
  1518. /**
  1519. * udc_start: initialize gadget role
  1520. * @ci: chipidea controller
  1521. */
  1522. static int udc_start(struct ci_hdrc *ci)
  1523. {
  1524. struct device *dev = ci->dev;
  1525. int retval = 0;
  1526. spin_lock_init(&ci->lock);
  1527. ci->gadget.ops = &usb_gadget_ops;
  1528. ci->gadget.speed = USB_SPEED_UNKNOWN;
  1529. ci->gadget.max_speed = USB_SPEED_HIGH;
  1530. ci->gadget.is_otg = ci->is_otg ? 1 : 0;
  1531. ci->gadget.name = ci->platdata->name;
  1532. INIT_LIST_HEAD(&ci->gadget.ep_list);
  1533. /* alloc resources */
  1534. ci->qh_pool = dma_pool_create("ci_hw_qh", dev,
  1535. sizeof(struct ci_hw_qh),
  1536. 64, CI_HDRC_PAGE_SIZE);
  1537. if (ci->qh_pool == NULL)
  1538. return -ENOMEM;
  1539. ci->td_pool = dma_pool_create("ci_hw_td", dev,
  1540. sizeof(struct ci_hw_td),
  1541. 64, CI_HDRC_PAGE_SIZE);
  1542. if (ci->td_pool == NULL) {
  1543. retval = -ENOMEM;
  1544. goto free_qh_pool;
  1545. }
  1546. retval = init_eps(ci);
  1547. if (retval)
  1548. goto free_pools;
  1549. ci->gadget.ep0 = &ci->ep0in->ep;
  1550. retval = usb_add_gadget_udc(dev, &ci->gadget);
  1551. if (retval)
  1552. goto destroy_eps;
  1553. pm_runtime_no_callbacks(&ci->gadget.dev);
  1554. pm_runtime_enable(&ci->gadget.dev);
  1555. return retval;
  1556. destroy_eps:
  1557. destroy_eps(ci);
  1558. free_pools:
  1559. dma_pool_destroy(ci->td_pool);
  1560. free_qh_pool:
  1561. dma_pool_destroy(ci->qh_pool);
  1562. return retval;
  1563. }
  1564. /**
  1565. * ci_hdrc_gadget_destroy: parent remove must call this to remove UDC
  1566. *
  1567. * No interrupts active, the IRQ has been released
  1568. */
  1569. void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
  1570. {
  1571. if (!ci->roles[CI_ROLE_GADGET])
  1572. return;
  1573. usb_del_gadget_udc(&ci->gadget);
  1574. destroy_eps(ci);
  1575. dma_pool_destroy(ci->td_pool);
  1576. dma_pool_destroy(ci->qh_pool);
  1577. }
  1578. static int udc_id_switch_for_device(struct ci_hdrc *ci)
  1579. {
  1580. if (ci->is_otg)
  1581. /* Clear and enable BSV irq */
  1582. hw_write_otgsc(ci, OTGSC_BSVIS | OTGSC_BSVIE,
  1583. OTGSC_BSVIS | OTGSC_BSVIE);
  1584. return 0;
  1585. }
  1586. static void udc_id_switch_for_host(struct ci_hdrc *ci)
  1587. {
  1588. /*
  1589. * host doesn't care B_SESSION_VALID event
  1590. * so clear and disbale BSV irq
  1591. */
  1592. if (ci->is_otg)
  1593. hw_write_otgsc(ci, OTGSC_BSVIE | OTGSC_BSVIS, OTGSC_BSVIS);
  1594. }
  1595. /**
  1596. * ci_hdrc_gadget_init - initialize device related bits
  1597. * ci: the controller
  1598. *
  1599. * This function initializes the gadget, if the device is "device capable".
  1600. */
  1601. int ci_hdrc_gadget_init(struct ci_hdrc *ci)
  1602. {
  1603. struct ci_role_driver *rdrv;
  1604. if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
  1605. return -ENXIO;
  1606. rdrv = devm_kzalloc(ci->dev, sizeof(struct ci_role_driver), GFP_KERNEL);
  1607. if (!rdrv)
  1608. return -ENOMEM;
  1609. rdrv->start = udc_id_switch_for_device;
  1610. rdrv->stop = udc_id_switch_for_host;
  1611. rdrv->irq = udc_irq;
  1612. rdrv->name = "gadget";
  1613. ci->roles[CI_ROLE_GADGET] = rdrv;
  1614. return udc_start(ci);
  1615. }