rtc-sh.c 19 KB

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  1. /*
  2. * SuperH On-Chip RTC Support
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. * Copyright (C) 2008 Angelo Castello
  7. *
  8. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  9. *
  10. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  11. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc.h>
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/io.h>
  27. #include <linux/log2.h>
  28. #include <linux/clk.h>
  29. #include <linux/slab.h>
  30. #ifdef CONFIG_SUPERH
  31. #include <asm/rtc.h>
  32. #else
  33. /* Default values for RZ/A RTC */
  34. #define rtc_reg_size sizeof(u16)
  35. #define RTC_BIT_INVERTED 0 /* no chip bugs */
  36. #define RTC_CAP_4_DIGIT_YEAR (1 << 0)
  37. #define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
  38. #endif
  39. #define DRV_NAME "sh-rtc"
  40. #define RTC_REG(r) ((r) * rtc_reg_size)
  41. #define R64CNT RTC_REG(0)
  42. #define RSECCNT RTC_REG(1) /* RTC sec */
  43. #define RMINCNT RTC_REG(2) /* RTC min */
  44. #define RHRCNT RTC_REG(3) /* RTC hour */
  45. #define RWKCNT RTC_REG(4) /* RTC week */
  46. #define RDAYCNT RTC_REG(5) /* RTC day */
  47. #define RMONCNT RTC_REG(6) /* RTC month */
  48. #define RYRCNT RTC_REG(7) /* RTC year */
  49. #define RSECAR RTC_REG(8) /* ALARM sec */
  50. #define RMINAR RTC_REG(9) /* ALARM min */
  51. #define RHRAR RTC_REG(10) /* ALARM hour */
  52. #define RWKAR RTC_REG(11) /* ALARM week */
  53. #define RDAYAR RTC_REG(12) /* ALARM day */
  54. #define RMONAR RTC_REG(13) /* ALARM month */
  55. #define RCR1 RTC_REG(14) /* Control */
  56. #define RCR2 RTC_REG(15) /* Control */
  57. /*
  58. * Note on RYRAR and RCR3: Up until this point most of the register
  59. * definitions are consistent across all of the available parts. However,
  60. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  61. * register used to control RYRCNT/RYRAR compare) varies considerably
  62. * across various parts, occasionally being mapped in to a completely
  63. * unrelated address space. For proper RYRAR support a separate resource
  64. * would have to be handed off, but as this is purely optional in
  65. * practice, we simply opt not to support it, thereby keeping the code
  66. * quite a bit more simplified.
  67. */
  68. /* ALARM Bits - or with BCD encoded value */
  69. #define AR_ENB 0x80 /* Enable for alarm cmp */
  70. /* Period Bits */
  71. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  72. #define PF_COUNT 0x200 /* Half periodic counter */
  73. #define PF_OXS 0x400 /* Periodic One x Second */
  74. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  75. #define PF_MASK 0xf00
  76. /* RCR1 Bits */
  77. #define RCR1_CF 0x80 /* Carry Flag */
  78. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  79. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  80. #define RCR1_AF 0x01 /* Alarm Flag */
  81. /* RCR2 Bits */
  82. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  83. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  84. #define RCR2_RTCEN 0x08 /* ENable RTC */
  85. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  86. #define RCR2_RESET 0x02 /* Reset bit */
  87. #define RCR2_START 0x01 /* Start bit */
  88. struct sh_rtc {
  89. void __iomem *regbase;
  90. unsigned long regsize;
  91. struct resource *res;
  92. int alarm_irq;
  93. int periodic_irq;
  94. int carry_irq;
  95. struct clk *clk;
  96. struct rtc_device *rtc_dev;
  97. spinlock_t lock;
  98. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  99. unsigned short periodic_freq;
  100. };
  101. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  102. {
  103. unsigned int tmp, pending;
  104. tmp = readb(rtc->regbase + RCR1);
  105. pending = tmp & RCR1_CF;
  106. tmp &= ~RCR1_CF;
  107. writeb(tmp, rtc->regbase + RCR1);
  108. /* Users have requested One x Second IRQ */
  109. if (pending && rtc->periodic_freq & PF_OXS)
  110. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  111. return pending;
  112. }
  113. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  114. {
  115. unsigned int tmp, pending;
  116. tmp = readb(rtc->regbase + RCR1);
  117. pending = tmp & RCR1_AF;
  118. tmp &= ~(RCR1_AF | RCR1_AIE);
  119. writeb(tmp, rtc->regbase + RCR1);
  120. if (pending)
  121. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  122. return pending;
  123. }
  124. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  125. {
  126. struct rtc_device *rtc_dev = rtc->rtc_dev;
  127. struct rtc_task *irq_task;
  128. unsigned int tmp, pending;
  129. tmp = readb(rtc->regbase + RCR2);
  130. pending = tmp & RCR2_PEF;
  131. tmp &= ~RCR2_PEF;
  132. writeb(tmp, rtc->regbase + RCR2);
  133. if (!pending)
  134. return 0;
  135. /* Half period enabled than one skipped and the next notified */
  136. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  137. rtc->periodic_freq &= ~PF_COUNT;
  138. else {
  139. if (rtc->periodic_freq & PF_HP)
  140. rtc->periodic_freq |= PF_COUNT;
  141. if (rtc->periodic_freq & PF_KOU) {
  142. spin_lock(&rtc_dev->irq_task_lock);
  143. irq_task = rtc_dev->irq_task;
  144. if (irq_task)
  145. irq_task->func(irq_task->private_data);
  146. spin_unlock(&rtc_dev->irq_task_lock);
  147. } else
  148. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  149. }
  150. return pending;
  151. }
  152. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  153. {
  154. struct sh_rtc *rtc = dev_id;
  155. int ret;
  156. spin_lock(&rtc->lock);
  157. ret = __sh_rtc_interrupt(rtc);
  158. spin_unlock(&rtc->lock);
  159. return IRQ_RETVAL(ret);
  160. }
  161. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  162. {
  163. struct sh_rtc *rtc = dev_id;
  164. int ret;
  165. spin_lock(&rtc->lock);
  166. ret = __sh_rtc_alarm(rtc);
  167. spin_unlock(&rtc->lock);
  168. return IRQ_RETVAL(ret);
  169. }
  170. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  171. {
  172. struct sh_rtc *rtc = dev_id;
  173. int ret;
  174. spin_lock(&rtc->lock);
  175. ret = __sh_rtc_periodic(rtc);
  176. spin_unlock(&rtc->lock);
  177. return IRQ_RETVAL(ret);
  178. }
  179. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  180. {
  181. struct sh_rtc *rtc = dev_id;
  182. int ret;
  183. spin_lock(&rtc->lock);
  184. ret = __sh_rtc_interrupt(rtc);
  185. ret |= __sh_rtc_alarm(rtc);
  186. ret |= __sh_rtc_periodic(rtc);
  187. spin_unlock(&rtc->lock);
  188. return IRQ_RETVAL(ret);
  189. }
  190. static int sh_rtc_irq_set_state(struct device *dev, int enable)
  191. {
  192. struct sh_rtc *rtc = dev_get_drvdata(dev);
  193. unsigned int tmp;
  194. spin_lock_irq(&rtc->lock);
  195. tmp = readb(rtc->regbase + RCR2);
  196. if (enable) {
  197. rtc->periodic_freq |= PF_KOU;
  198. tmp &= ~RCR2_PEF; /* Clear PES bit */
  199. tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
  200. } else {
  201. rtc->periodic_freq &= ~PF_KOU;
  202. tmp &= ~(RCR2_PESMASK | RCR2_PEF);
  203. }
  204. writeb(tmp, rtc->regbase + RCR2);
  205. spin_unlock_irq(&rtc->lock);
  206. return 0;
  207. }
  208. static int sh_rtc_irq_set_freq(struct device *dev, int freq)
  209. {
  210. struct sh_rtc *rtc = dev_get_drvdata(dev);
  211. int tmp, ret = 0;
  212. spin_lock_irq(&rtc->lock);
  213. tmp = rtc->periodic_freq & PF_MASK;
  214. switch (freq) {
  215. case 0:
  216. rtc->periodic_freq = 0x00;
  217. break;
  218. case 1:
  219. rtc->periodic_freq = 0x60;
  220. break;
  221. case 2:
  222. rtc->periodic_freq = 0x50;
  223. break;
  224. case 4:
  225. rtc->periodic_freq = 0x40;
  226. break;
  227. case 8:
  228. rtc->periodic_freq = 0x30 | PF_HP;
  229. break;
  230. case 16:
  231. rtc->periodic_freq = 0x30;
  232. break;
  233. case 32:
  234. rtc->periodic_freq = 0x20 | PF_HP;
  235. break;
  236. case 64:
  237. rtc->periodic_freq = 0x20;
  238. break;
  239. case 128:
  240. rtc->periodic_freq = 0x10 | PF_HP;
  241. break;
  242. case 256:
  243. rtc->periodic_freq = 0x10;
  244. break;
  245. default:
  246. ret = -ENOTSUPP;
  247. }
  248. if (ret == 0)
  249. rtc->periodic_freq |= tmp;
  250. spin_unlock_irq(&rtc->lock);
  251. return ret;
  252. }
  253. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  254. {
  255. struct sh_rtc *rtc = dev_get_drvdata(dev);
  256. unsigned int tmp;
  257. spin_lock_irq(&rtc->lock);
  258. tmp = readb(rtc->regbase + RCR1);
  259. if (enable)
  260. tmp |= RCR1_AIE;
  261. else
  262. tmp &= ~RCR1_AIE;
  263. writeb(tmp, rtc->regbase + RCR1);
  264. spin_unlock_irq(&rtc->lock);
  265. }
  266. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  267. {
  268. struct sh_rtc *rtc = dev_get_drvdata(dev);
  269. unsigned int tmp;
  270. tmp = readb(rtc->regbase + RCR1);
  271. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  272. tmp = readb(rtc->regbase + RCR2);
  273. seq_printf(seq, "periodic_IRQ\t: %s\n",
  274. (tmp & RCR2_PESMASK) ? "yes" : "no");
  275. return 0;
  276. }
  277. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  278. {
  279. struct sh_rtc *rtc = dev_get_drvdata(dev);
  280. unsigned int tmp;
  281. spin_lock_irq(&rtc->lock);
  282. tmp = readb(rtc->regbase + RCR1);
  283. if (!enable)
  284. tmp &= ~RCR1_CIE;
  285. else
  286. tmp |= RCR1_CIE;
  287. writeb(tmp, rtc->regbase + RCR1);
  288. spin_unlock_irq(&rtc->lock);
  289. }
  290. static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  291. {
  292. sh_rtc_setaie(dev, enabled);
  293. return 0;
  294. }
  295. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  296. {
  297. struct sh_rtc *rtc = dev_get_drvdata(dev);
  298. unsigned int sec128, sec2, yr, yr100, cf_bit;
  299. do {
  300. unsigned int tmp;
  301. spin_lock_irq(&rtc->lock);
  302. tmp = readb(rtc->regbase + RCR1);
  303. tmp &= ~RCR1_CF; /* Clear CF-bit */
  304. tmp |= RCR1_CIE;
  305. writeb(tmp, rtc->regbase + RCR1);
  306. sec128 = readb(rtc->regbase + R64CNT);
  307. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  308. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  309. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  310. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  311. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  312. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  313. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  314. yr = readw(rtc->regbase + RYRCNT);
  315. yr100 = bcd2bin(yr >> 8);
  316. yr &= 0xff;
  317. } else {
  318. yr = readb(rtc->regbase + RYRCNT);
  319. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  320. }
  321. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  322. sec2 = readb(rtc->regbase + R64CNT);
  323. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  324. spin_unlock_irq(&rtc->lock);
  325. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  326. #if RTC_BIT_INVERTED != 0
  327. if ((sec128 & RTC_BIT_INVERTED))
  328. tm->tm_sec--;
  329. #endif
  330. /* only keep the carry interrupt enabled if UIE is on */
  331. if (!(rtc->periodic_freq & PF_OXS))
  332. sh_rtc_setcie(dev, 0);
  333. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  334. "mday=%d, mon=%d, year=%d, wday=%d\n",
  335. __func__,
  336. tm->tm_sec, tm->tm_min, tm->tm_hour,
  337. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  338. return 0;
  339. }
  340. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  341. {
  342. struct sh_rtc *rtc = dev_get_drvdata(dev);
  343. unsigned int tmp;
  344. int year;
  345. spin_lock_irq(&rtc->lock);
  346. /* Reset pre-scaler & stop RTC */
  347. tmp = readb(rtc->regbase + RCR2);
  348. tmp |= RCR2_RESET;
  349. tmp &= ~RCR2_START;
  350. writeb(tmp, rtc->regbase + RCR2);
  351. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  352. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  353. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  354. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  355. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  356. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  357. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  358. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  359. bin2bcd(tm->tm_year % 100);
  360. writew(year, rtc->regbase + RYRCNT);
  361. } else {
  362. year = tm->tm_year % 100;
  363. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  364. }
  365. /* Start RTC */
  366. tmp = readb(rtc->regbase + RCR2);
  367. tmp &= ~RCR2_RESET;
  368. tmp |= RCR2_RTCEN | RCR2_START;
  369. writeb(tmp, rtc->regbase + RCR2);
  370. spin_unlock_irq(&rtc->lock);
  371. return 0;
  372. }
  373. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  374. {
  375. unsigned int byte;
  376. int value = 0xff; /* return 0xff for ignored values */
  377. byte = readb(rtc->regbase + reg_off);
  378. if (byte & AR_ENB) {
  379. byte &= ~AR_ENB; /* strip the enable bit */
  380. value = bcd2bin(byte);
  381. }
  382. return value;
  383. }
  384. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  385. {
  386. struct sh_rtc *rtc = dev_get_drvdata(dev);
  387. struct rtc_time *tm = &wkalrm->time;
  388. spin_lock_irq(&rtc->lock);
  389. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  390. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  391. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  392. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  393. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  394. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  395. if (tm->tm_mon > 0)
  396. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  397. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  398. spin_unlock_irq(&rtc->lock);
  399. return 0;
  400. }
  401. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  402. int value, int reg_off)
  403. {
  404. /* < 0 for a value that is ignored */
  405. if (value < 0)
  406. writeb(0, rtc->regbase + reg_off);
  407. else
  408. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  409. }
  410. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  411. {
  412. struct sh_rtc *rtc = dev_get_drvdata(dev);
  413. unsigned int rcr1;
  414. struct rtc_time *tm = &wkalrm->time;
  415. int mon;
  416. spin_lock_irq(&rtc->lock);
  417. /* disable alarm interrupt and clear the alarm flag */
  418. rcr1 = readb(rtc->regbase + RCR1);
  419. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  420. writeb(rcr1, rtc->regbase + RCR1);
  421. /* set alarm time */
  422. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  423. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  424. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  425. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  426. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  427. mon = tm->tm_mon;
  428. if (mon >= 0)
  429. mon += 1;
  430. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  431. if (wkalrm->enabled) {
  432. rcr1 |= RCR1_AIE;
  433. writeb(rcr1, rtc->regbase + RCR1);
  434. }
  435. spin_unlock_irq(&rtc->lock);
  436. return 0;
  437. }
  438. static const struct rtc_class_ops sh_rtc_ops = {
  439. .read_time = sh_rtc_read_time,
  440. .set_time = sh_rtc_set_time,
  441. .read_alarm = sh_rtc_read_alarm,
  442. .set_alarm = sh_rtc_set_alarm,
  443. .proc = sh_rtc_proc,
  444. .alarm_irq_enable = sh_rtc_alarm_irq_enable,
  445. };
  446. static int __init sh_rtc_probe(struct platform_device *pdev)
  447. {
  448. struct sh_rtc *rtc;
  449. struct resource *res;
  450. struct rtc_time r;
  451. char clk_name[6];
  452. int clk_id, ret;
  453. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  454. if (unlikely(!rtc))
  455. return -ENOMEM;
  456. spin_lock_init(&rtc->lock);
  457. /* get periodic/carry/alarm irqs */
  458. ret = platform_get_irq(pdev, 0);
  459. if (unlikely(ret <= 0)) {
  460. dev_err(&pdev->dev, "No IRQ resource\n");
  461. return -ENOENT;
  462. }
  463. rtc->periodic_irq = ret;
  464. rtc->carry_irq = platform_get_irq(pdev, 1);
  465. rtc->alarm_irq = platform_get_irq(pdev, 2);
  466. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  467. if (!res)
  468. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  469. if (unlikely(res == NULL)) {
  470. dev_err(&pdev->dev, "No IO resource\n");
  471. return -ENOENT;
  472. }
  473. rtc->regsize = resource_size(res);
  474. rtc->res = devm_request_mem_region(&pdev->dev, res->start,
  475. rtc->regsize, pdev->name);
  476. if (unlikely(!rtc->res))
  477. return -EBUSY;
  478. rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
  479. rtc->regsize);
  480. if (unlikely(!rtc->regbase))
  481. return -EINVAL;
  482. if (!pdev->dev.of_node) {
  483. clk_id = pdev->id;
  484. /* With a single device, the clock id is still "rtc0" */
  485. if (clk_id < 0)
  486. clk_id = 0;
  487. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  488. } else
  489. snprintf(clk_name, sizeof(clk_name), "fck");
  490. rtc->clk = devm_clk_get(&pdev->dev, clk_name);
  491. if (IS_ERR(rtc->clk)) {
  492. /*
  493. * No error handling for rtc->clk intentionally, not all
  494. * platforms will have a unique clock for the RTC, and
  495. * the clk API can handle the struct clk pointer being
  496. * NULL.
  497. */
  498. rtc->clk = NULL;
  499. }
  500. clk_enable(rtc->clk);
  501. rtc->capabilities = RTC_DEF_CAPABILITIES;
  502. #ifdef CONFIG_SUPERH
  503. if (dev_get_platdata(&pdev->dev)) {
  504. struct sh_rtc_platform_info *pinfo =
  505. dev_get_platdata(&pdev->dev);
  506. /*
  507. * Some CPUs have special capabilities in addition to the
  508. * default set. Add those in here.
  509. */
  510. rtc->capabilities |= pinfo->capabilities;
  511. }
  512. #endif
  513. if (rtc->carry_irq <= 0) {
  514. /* register shared periodic/carry/alarm irq */
  515. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  516. sh_rtc_shared, 0, "sh-rtc", rtc);
  517. if (unlikely(ret)) {
  518. dev_err(&pdev->dev,
  519. "request IRQ failed with %d, IRQ %d\n", ret,
  520. rtc->periodic_irq);
  521. goto err_unmap;
  522. }
  523. } else {
  524. /* register periodic/carry/alarm irqs */
  525. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  526. sh_rtc_periodic, 0, "sh-rtc period", rtc);
  527. if (unlikely(ret)) {
  528. dev_err(&pdev->dev,
  529. "request period IRQ failed with %d, IRQ %d\n",
  530. ret, rtc->periodic_irq);
  531. goto err_unmap;
  532. }
  533. ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
  534. sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
  535. if (unlikely(ret)) {
  536. dev_err(&pdev->dev,
  537. "request carry IRQ failed with %d, IRQ %d\n",
  538. ret, rtc->carry_irq);
  539. goto err_unmap;
  540. }
  541. ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
  542. sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
  543. if (unlikely(ret)) {
  544. dev_err(&pdev->dev,
  545. "request alarm IRQ failed with %d, IRQ %d\n",
  546. ret, rtc->alarm_irq);
  547. goto err_unmap;
  548. }
  549. }
  550. platform_set_drvdata(pdev, rtc);
  551. /* everything disabled by default */
  552. sh_rtc_irq_set_freq(&pdev->dev, 0);
  553. sh_rtc_irq_set_state(&pdev->dev, 0);
  554. sh_rtc_setaie(&pdev->dev, 0);
  555. sh_rtc_setcie(&pdev->dev, 0);
  556. rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
  557. &sh_rtc_ops, THIS_MODULE);
  558. if (IS_ERR(rtc->rtc_dev)) {
  559. ret = PTR_ERR(rtc->rtc_dev);
  560. goto err_unmap;
  561. }
  562. rtc->rtc_dev->max_user_freq = 256;
  563. /* reset rtc to epoch 0 if time is invalid */
  564. if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
  565. rtc_time_to_tm(0, &r);
  566. rtc_set_time(rtc->rtc_dev, &r);
  567. }
  568. device_init_wakeup(&pdev->dev, 1);
  569. return 0;
  570. err_unmap:
  571. clk_disable(rtc->clk);
  572. return ret;
  573. }
  574. static int __exit sh_rtc_remove(struct platform_device *pdev)
  575. {
  576. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  577. sh_rtc_irq_set_state(&pdev->dev, 0);
  578. sh_rtc_setaie(&pdev->dev, 0);
  579. sh_rtc_setcie(&pdev->dev, 0);
  580. clk_disable(rtc->clk);
  581. return 0;
  582. }
  583. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  584. {
  585. struct sh_rtc *rtc = dev_get_drvdata(dev);
  586. irq_set_irq_wake(rtc->periodic_irq, enabled);
  587. if (rtc->carry_irq > 0) {
  588. irq_set_irq_wake(rtc->carry_irq, enabled);
  589. irq_set_irq_wake(rtc->alarm_irq, enabled);
  590. }
  591. }
  592. static int __maybe_unused sh_rtc_suspend(struct device *dev)
  593. {
  594. if (device_may_wakeup(dev))
  595. sh_rtc_set_irq_wake(dev, 1);
  596. return 0;
  597. }
  598. static int __maybe_unused sh_rtc_resume(struct device *dev)
  599. {
  600. if (device_may_wakeup(dev))
  601. sh_rtc_set_irq_wake(dev, 0);
  602. return 0;
  603. }
  604. static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
  605. static const struct of_device_id sh_rtc_of_match[] = {
  606. { .compatible = "renesas,sh-rtc", },
  607. { /* sentinel */ }
  608. };
  609. MODULE_DEVICE_TABLE(of, sh_rtc_of_match);
  610. static struct platform_driver sh_rtc_platform_driver = {
  611. .driver = {
  612. .name = DRV_NAME,
  613. .pm = &sh_rtc_pm_ops,
  614. .of_match_table = sh_rtc_of_match,
  615. },
  616. .remove = __exit_p(sh_rtc_remove),
  617. };
  618. module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
  619. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  620. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
  621. "Jamie Lenehan <lenehan@twibble.org>, "
  622. "Angelo Castello <angelo.castello@st.com>");
  623. MODULE_LICENSE("GPL");
  624. MODULE_ALIAS("platform:" DRV_NAME);