omap_drv.c 22 KB

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  1. /*
  2. * drivers/gpu/drm/omapdrm/omap_drv.c
  3. *
  4. * Copyright (C) 2011 Texas Instruments
  5. * Author: Rob Clark <rob@ti.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/wait.h>
  20. #include <drm/drm_atomic.h>
  21. #include <drm/drm_atomic_helper.h>
  22. #include <drm/drm_crtc_helper.h>
  23. #include <drm/drm_fb_helper.h>
  24. #include "omap_dmm_tiler.h"
  25. #include "omap_drv.h"
  26. #define DRIVER_NAME MODULE_NAME
  27. #define DRIVER_DESC "OMAP DRM"
  28. #define DRIVER_DATE "20110917"
  29. #define DRIVER_MAJOR 1
  30. #define DRIVER_MINOR 0
  31. #define DRIVER_PATCHLEVEL 0
  32. static int num_crtc = CONFIG_DRM_OMAP_NUM_CRTCS;
  33. MODULE_PARM_DESC(num_crtc, "Number of overlays to use as CRTCs");
  34. module_param(num_crtc, int, 0600);
  35. /*
  36. * mode config funcs
  37. */
  38. /* Notes about mapping DSS and DRM entities:
  39. * CRTC: overlay
  40. * encoder: manager.. with some extension to allow one primary CRTC
  41. * and zero or more video CRTC's to be mapped to one encoder?
  42. * connector: dssdev.. manager can be attached/detached from different
  43. * devices
  44. */
  45. static void omap_fb_output_poll_changed(struct drm_device *dev)
  46. {
  47. struct omap_drm_private *priv = dev->dev_private;
  48. DBG("dev=%p", dev);
  49. if (priv->fbdev)
  50. drm_fb_helper_hotplug_event(priv->fbdev);
  51. }
  52. struct omap_atomic_state_commit {
  53. struct work_struct work;
  54. struct drm_device *dev;
  55. struct drm_atomic_state *state;
  56. u32 crtcs;
  57. };
  58. static void omap_atomic_wait_for_completion(struct drm_device *dev,
  59. struct drm_atomic_state *old_state)
  60. {
  61. struct drm_crtc_state *old_crtc_state;
  62. struct drm_crtc *crtc;
  63. unsigned int i;
  64. int ret;
  65. for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  66. if (!crtc->state->enable)
  67. continue;
  68. ret = omap_crtc_wait_pending(crtc);
  69. if (!ret)
  70. dev_warn(dev->dev,
  71. "atomic complete timeout (pipe %u)!\n", i);
  72. }
  73. }
  74. static void omap_atomic_complete(struct omap_atomic_state_commit *commit)
  75. {
  76. struct drm_device *dev = commit->dev;
  77. struct omap_drm_private *priv = dev->dev_private;
  78. struct drm_atomic_state *old_state = commit->state;
  79. /* Apply the atomic update. */
  80. dispc_runtime_get();
  81. drm_atomic_helper_commit_modeset_disables(dev, old_state);
  82. drm_atomic_helper_commit_planes(dev, old_state, 0);
  83. drm_atomic_helper_commit_modeset_enables(dev, old_state);
  84. omap_atomic_wait_for_completion(dev, old_state);
  85. drm_atomic_helper_cleanup_planes(dev, old_state);
  86. dispc_runtime_put();
  87. drm_atomic_state_put(old_state);
  88. /* Complete the commit, wake up any waiter. */
  89. spin_lock(&priv->commit.lock);
  90. priv->commit.pending &= ~commit->crtcs;
  91. spin_unlock(&priv->commit.lock);
  92. wake_up_all(&priv->commit.wait);
  93. kfree(commit);
  94. }
  95. static void omap_atomic_work(struct work_struct *work)
  96. {
  97. struct omap_atomic_state_commit *commit =
  98. container_of(work, struct omap_atomic_state_commit, work);
  99. omap_atomic_complete(commit);
  100. }
  101. static bool omap_atomic_is_pending(struct omap_drm_private *priv,
  102. struct omap_atomic_state_commit *commit)
  103. {
  104. bool pending;
  105. spin_lock(&priv->commit.lock);
  106. pending = priv->commit.pending & commit->crtcs;
  107. spin_unlock(&priv->commit.lock);
  108. return pending;
  109. }
  110. static int omap_atomic_commit(struct drm_device *dev,
  111. struct drm_atomic_state *state, bool nonblock)
  112. {
  113. struct omap_drm_private *priv = dev->dev_private;
  114. struct omap_atomic_state_commit *commit;
  115. struct drm_crtc *crtc;
  116. struct drm_crtc_state *crtc_state;
  117. int i, ret;
  118. ret = drm_atomic_helper_prepare_planes(dev, state);
  119. if (ret)
  120. return ret;
  121. /* Allocate the commit object. */
  122. commit = kzalloc(sizeof(*commit), GFP_KERNEL);
  123. if (commit == NULL) {
  124. ret = -ENOMEM;
  125. goto error;
  126. }
  127. INIT_WORK(&commit->work, omap_atomic_work);
  128. commit->dev = dev;
  129. commit->state = state;
  130. /* Wait until all affected CRTCs have completed previous commits and
  131. * mark them as pending.
  132. */
  133. for_each_crtc_in_state(state, crtc, crtc_state, i)
  134. commit->crtcs |= drm_crtc_mask(crtc);
  135. wait_event(priv->commit.wait, !omap_atomic_is_pending(priv, commit));
  136. spin_lock(&priv->commit.lock);
  137. priv->commit.pending |= commit->crtcs;
  138. spin_unlock(&priv->commit.lock);
  139. /* Swap the state, this is the point of no return. */
  140. drm_atomic_helper_swap_state(state, true);
  141. drm_atomic_state_get(state);
  142. if (nonblock)
  143. schedule_work(&commit->work);
  144. else
  145. omap_atomic_complete(commit);
  146. return 0;
  147. error:
  148. drm_atomic_helper_cleanup_planes(dev, state);
  149. return ret;
  150. }
  151. static const struct drm_mode_config_funcs omap_mode_config_funcs = {
  152. .fb_create = omap_framebuffer_create,
  153. .output_poll_changed = omap_fb_output_poll_changed,
  154. .atomic_check = drm_atomic_helper_check,
  155. .atomic_commit = omap_atomic_commit,
  156. };
  157. static int get_connector_type(struct omap_dss_device *dssdev)
  158. {
  159. switch (dssdev->type) {
  160. case OMAP_DISPLAY_TYPE_HDMI:
  161. return DRM_MODE_CONNECTOR_HDMIA;
  162. case OMAP_DISPLAY_TYPE_DVI:
  163. return DRM_MODE_CONNECTOR_DVID;
  164. case OMAP_DISPLAY_TYPE_DSI:
  165. return DRM_MODE_CONNECTOR_DSI;
  166. default:
  167. return DRM_MODE_CONNECTOR_Unknown;
  168. }
  169. }
  170. static bool channel_used(struct drm_device *dev, enum omap_channel channel)
  171. {
  172. struct omap_drm_private *priv = dev->dev_private;
  173. int i;
  174. for (i = 0; i < priv->num_crtcs; i++) {
  175. struct drm_crtc *crtc = priv->crtcs[i];
  176. if (omap_crtc_channel(crtc) == channel)
  177. return true;
  178. }
  179. return false;
  180. }
  181. static void omap_disconnect_dssdevs(void)
  182. {
  183. struct omap_dss_device *dssdev = NULL;
  184. for_each_dss_dev(dssdev)
  185. dssdev->driver->disconnect(dssdev);
  186. }
  187. static int omap_connect_dssdevs(void)
  188. {
  189. int r;
  190. struct omap_dss_device *dssdev = NULL;
  191. bool no_displays = true;
  192. for_each_dss_dev(dssdev) {
  193. r = dssdev->driver->connect(dssdev);
  194. if (r == -EPROBE_DEFER) {
  195. omap_dss_put_device(dssdev);
  196. goto cleanup;
  197. } else if (r) {
  198. dev_warn(dssdev->dev, "could not connect display: %s\n",
  199. dssdev->name);
  200. } else {
  201. no_displays = false;
  202. }
  203. }
  204. if (no_displays)
  205. return -EPROBE_DEFER;
  206. return 0;
  207. cleanup:
  208. /*
  209. * if we are deferring probe, we disconnect the devices we previously
  210. * connected
  211. */
  212. omap_disconnect_dssdevs();
  213. return r;
  214. }
  215. static int omap_modeset_create_crtc(struct drm_device *dev, int id,
  216. enum omap_channel channel)
  217. {
  218. struct omap_drm_private *priv = dev->dev_private;
  219. struct drm_plane *plane;
  220. struct drm_crtc *crtc;
  221. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_PRIMARY);
  222. if (IS_ERR(plane))
  223. return PTR_ERR(plane);
  224. crtc = omap_crtc_init(dev, plane, channel, id);
  225. BUG_ON(priv->num_crtcs >= ARRAY_SIZE(priv->crtcs));
  226. priv->crtcs[id] = crtc;
  227. priv->num_crtcs++;
  228. priv->planes[id] = plane;
  229. priv->num_planes++;
  230. return 0;
  231. }
  232. static int omap_modeset_init_properties(struct drm_device *dev)
  233. {
  234. struct omap_drm_private *priv = dev->dev_private;
  235. priv->zorder_prop = drm_property_create_range(dev, 0, "zorder", 0, 3);
  236. if (!priv->zorder_prop)
  237. return -ENOMEM;
  238. return 0;
  239. }
  240. static int omap_modeset_init(struct drm_device *dev)
  241. {
  242. struct omap_drm_private *priv = dev->dev_private;
  243. struct omap_dss_device *dssdev = NULL;
  244. int num_ovls = dss_feat_get_num_ovls();
  245. int num_mgrs = dss_feat_get_num_mgrs();
  246. int num_crtcs;
  247. int i, id = 0;
  248. int ret;
  249. drm_mode_config_init(dev);
  250. omap_drm_irq_install(dev);
  251. ret = omap_modeset_init_properties(dev);
  252. if (ret < 0)
  253. return ret;
  254. /*
  255. * We usually don't want to create a CRTC for each manager, at least
  256. * not until we have a way to expose private planes to userspace.
  257. * Otherwise there would not be enough video pipes left for drm planes.
  258. * We use the num_crtc argument to limit the number of crtcs we create.
  259. */
  260. num_crtcs = min3(num_crtc, num_mgrs, num_ovls);
  261. dssdev = NULL;
  262. for_each_dss_dev(dssdev) {
  263. struct drm_connector *connector;
  264. struct drm_encoder *encoder;
  265. enum omap_channel channel;
  266. struct omap_dss_device *out;
  267. if (!omapdss_device_is_connected(dssdev))
  268. continue;
  269. encoder = omap_encoder_init(dev, dssdev);
  270. if (!encoder) {
  271. dev_err(dev->dev, "could not create encoder: %s\n",
  272. dssdev->name);
  273. return -ENOMEM;
  274. }
  275. connector = omap_connector_init(dev,
  276. get_connector_type(dssdev), dssdev, encoder);
  277. if (!connector) {
  278. dev_err(dev->dev, "could not create connector: %s\n",
  279. dssdev->name);
  280. return -ENOMEM;
  281. }
  282. BUG_ON(priv->num_encoders >= ARRAY_SIZE(priv->encoders));
  283. BUG_ON(priv->num_connectors >= ARRAY_SIZE(priv->connectors));
  284. priv->encoders[priv->num_encoders++] = encoder;
  285. priv->connectors[priv->num_connectors++] = connector;
  286. drm_mode_connector_attach_encoder(connector, encoder);
  287. /*
  288. * if we have reached the limit of the crtcs we are allowed to
  289. * create, let's not try to look for a crtc for this
  290. * panel/encoder and onwards, we will, of course, populate the
  291. * the possible_crtcs field for all the encoders with the final
  292. * set of crtcs we create
  293. */
  294. if (id == num_crtcs)
  295. continue;
  296. /*
  297. * get the recommended DISPC channel for this encoder. For now,
  298. * we only try to get create a crtc out of the recommended, the
  299. * other possible channels to which the encoder can connect are
  300. * not considered.
  301. */
  302. out = omapdss_find_output_from_display(dssdev);
  303. channel = out->dispc_channel;
  304. omap_dss_put_device(out);
  305. /*
  306. * if this channel hasn't already been taken by a previously
  307. * allocated crtc, we create a new crtc for it
  308. */
  309. if (!channel_used(dev, channel)) {
  310. ret = omap_modeset_create_crtc(dev, id, channel);
  311. if (ret < 0) {
  312. dev_err(dev->dev,
  313. "could not create CRTC (channel %u)\n",
  314. channel);
  315. return ret;
  316. }
  317. id++;
  318. }
  319. }
  320. /*
  321. * we have allocated crtcs according to the need of the panels/encoders,
  322. * adding more crtcs here if needed
  323. */
  324. for (; id < num_crtcs; id++) {
  325. /* find a free manager for this crtc */
  326. for (i = 0; i < num_mgrs; i++) {
  327. if (!channel_used(dev, i))
  328. break;
  329. }
  330. if (i == num_mgrs) {
  331. /* this shouldn't really happen */
  332. dev_err(dev->dev, "no managers left for crtc\n");
  333. return -ENOMEM;
  334. }
  335. ret = omap_modeset_create_crtc(dev, id, i);
  336. if (ret < 0) {
  337. dev_err(dev->dev,
  338. "could not create CRTC (channel %u)\n", i);
  339. return ret;
  340. }
  341. }
  342. /*
  343. * Create normal planes for the remaining overlays:
  344. */
  345. for (; id < num_ovls; id++) {
  346. struct drm_plane *plane;
  347. plane = omap_plane_init(dev, id, DRM_PLANE_TYPE_OVERLAY);
  348. if (IS_ERR(plane))
  349. return PTR_ERR(plane);
  350. BUG_ON(priv->num_planes >= ARRAY_SIZE(priv->planes));
  351. priv->planes[priv->num_planes++] = plane;
  352. }
  353. for (i = 0; i < priv->num_encoders; i++) {
  354. struct drm_encoder *encoder = priv->encoders[i];
  355. struct omap_dss_device *dssdev =
  356. omap_encoder_get_dssdev(encoder);
  357. struct omap_dss_device *output;
  358. output = omapdss_find_output_from_display(dssdev);
  359. /* figure out which crtc's we can connect the encoder to: */
  360. encoder->possible_crtcs = 0;
  361. for (id = 0; id < priv->num_crtcs; id++) {
  362. struct drm_crtc *crtc = priv->crtcs[id];
  363. enum omap_channel crtc_channel;
  364. crtc_channel = omap_crtc_channel(crtc);
  365. if (output->dispc_channel == crtc_channel) {
  366. encoder->possible_crtcs |= (1 << id);
  367. break;
  368. }
  369. }
  370. omap_dss_put_device(output);
  371. }
  372. DBG("registered %d planes, %d crtcs, %d encoders and %d connectors\n",
  373. priv->num_planes, priv->num_crtcs, priv->num_encoders,
  374. priv->num_connectors);
  375. dev->mode_config.min_width = 32;
  376. dev->mode_config.min_height = 32;
  377. /* note: eventually will need some cpu_is_omapXYZ() type stuff here
  378. * to fill in these limits properly on different OMAP generations..
  379. */
  380. dev->mode_config.max_width = 2048;
  381. dev->mode_config.max_height = 2048;
  382. dev->mode_config.funcs = &omap_mode_config_funcs;
  383. drm_mode_config_reset(dev);
  384. return 0;
  385. }
  386. static void omap_modeset_free(struct drm_device *dev)
  387. {
  388. drm_mode_config_cleanup(dev);
  389. }
  390. /*
  391. * drm ioctl funcs
  392. */
  393. static int ioctl_get_param(struct drm_device *dev, void *data,
  394. struct drm_file *file_priv)
  395. {
  396. struct omap_drm_private *priv = dev->dev_private;
  397. struct drm_omap_param *args = data;
  398. DBG("%p: param=%llu", dev, args->param);
  399. switch (args->param) {
  400. case OMAP_PARAM_CHIPSET_ID:
  401. args->value = priv->omaprev;
  402. break;
  403. default:
  404. DBG("unknown parameter %lld", args->param);
  405. return -EINVAL;
  406. }
  407. return 0;
  408. }
  409. static int ioctl_set_param(struct drm_device *dev, void *data,
  410. struct drm_file *file_priv)
  411. {
  412. struct drm_omap_param *args = data;
  413. switch (args->param) {
  414. default:
  415. DBG("unknown parameter %lld", args->param);
  416. return -EINVAL;
  417. }
  418. return 0;
  419. }
  420. #define OMAP_BO_USER_MASK 0x00ffffff /* flags settable by userspace */
  421. static int ioctl_gem_new(struct drm_device *dev, void *data,
  422. struct drm_file *file_priv)
  423. {
  424. struct drm_omap_gem_new *args = data;
  425. u32 flags = args->flags & OMAP_BO_USER_MASK;
  426. VERB("%p:%p: size=0x%08x, flags=%08x", dev, file_priv,
  427. args->size.bytes, flags);
  428. return omap_gem_new_handle(dev, file_priv, args->size, flags,
  429. &args->handle);
  430. }
  431. static int ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
  432. struct drm_file *file_priv)
  433. {
  434. struct drm_omap_gem_cpu_prep *args = data;
  435. struct drm_gem_object *obj;
  436. int ret;
  437. VERB("%p:%p: handle=%d, op=%x", dev, file_priv, args->handle, args->op);
  438. obj = drm_gem_object_lookup(file_priv, args->handle);
  439. if (!obj)
  440. return -ENOENT;
  441. ret = omap_gem_op_sync(obj, args->op);
  442. if (!ret)
  443. ret = omap_gem_op_start(obj, args->op);
  444. drm_gem_object_unreference_unlocked(obj);
  445. return ret;
  446. }
  447. static int ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
  448. struct drm_file *file_priv)
  449. {
  450. struct drm_omap_gem_cpu_fini *args = data;
  451. struct drm_gem_object *obj;
  452. int ret;
  453. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  454. obj = drm_gem_object_lookup(file_priv, args->handle);
  455. if (!obj)
  456. return -ENOENT;
  457. /* XXX flushy, flushy */
  458. ret = 0;
  459. if (!ret)
  460. ret = omap_gem_op_finish(obj, args->op);
  461. drm_gem_object_unreference_unlocked(obj);
  462. return ret;
  463. }
  464. static int ioctl_gem_info(struct drm_device *dev, void *data,
  465. struct drm_file *file_priv)
  466. {
  467. struct drm_omap_gem_info *args = data;
  468. struct drm_gem_object *obj;
  469. int ret = 0;
  470. VERB("%p:%p: handle=%d", dev, file_priv, args->handle);
  471. obj = drm_gem_object_lookup(file_priv, args->handle);
  472. if (!obj)
  473. return -ENOENT;
  474. args->size = omap_gem_mmap_size(obj);
  475. args->offset = omap_gem_mmap_offset(obj);
  476. drm_gem_object_unreference_unlocked(obj);
  477. return ret;
  478. }
  479. static const struct drm_ioctl_desc ioctls[DRM_COMMAND_END - DRM_COMMAND_BASE] = {
  480. DRM_IOCTL_DEF_DRV(OMAP_GET_PARAM, ioctl_get_param, DRM_AUTH),
  481. DRM_IOCTL_DEF_DRV(OMAP_SET_PARAM, ioctl_set_param, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
  482. DRM_IOCTL_DEF_DRV(OMAP_GEM_NEW, ioctl_gem_new, DRM_AUTH),
  483. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_PREP, ioctl_gem_cpu_prep, DRM_AUTH),
  484. DRM_IOCTL_DEF_DRV(OMAP_GEM_CPU_FINI, ioctl_gem_cpu_fini, DRM_AUTH),
  485. DRM_IOCTL_DEF_DRV(OMAP_GEM_INFO, ioctl_gem_info, DRM_AUTH),
  486. };
  487. /*
  488. * drm driver funcs
  489. */
  490. /**
  491. * load - setup chip and create an initial config
  492. * @dev: DRM device
  493. * @flags: startup flags
  494. *
  495. * The driver load routine has to do several things:
  496. * - initialize the memory manager
  497. * - allocate initial config memory
  498. * - setup the DRM framebuffer with the allocated memory
  499. */
  500. static int dev_load(struct drm_device *dev, unsigned long flags)
  501. {
  502. struct omap_drm_platform_data *pdata = dev->dev->platform_data;
  503. struct omap_drm_private *priv;
  504. unsigned int i;
  505. int ret;
  506. DBG("load: dev=%p", dev);
  507. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  508. if (!priv)
  509. return -ENOMEM;
  510. priv->omaprev = pdata->omaprev;
  511. dev->dev_private = priv;
  512. priv->wq = alloc_ordered_workqueue("omapdrm", 0);
  513. init_waitqueue_head(&priv->commit.wait);
  514. spin_lock_init(&priv->commit.lock);
  515. spin_lock_init(&priv->list_lock);
  516. INIT_LIST_HEAD(&priv->obj_list);
  517. omap_gem_init(dev);
  518. ret = omap_modeset_init(dev);
  519. if (ret) {
  520. dev_err(dev->dev, "omap_modeset_init failed: ret=%d\n", ret);
  521. dev->dev_private = NULL;
  522. kfree(priv);
  523. return ret;
  524. }
  525. /* Initialize vblank handling, start with all CRTCs disabled. */
  526. ret = drm_vblank_init(dev, priv->num_crtcs);
  527. if (ret)
  528. dev_warn(dev->dev, "could not init vblank\n");
  529. for (i = 0; i < priv->num_crtcs; i++)
  530. drm_crtc_vblank_off(priv->crtcs[i]);
  531. priv->fbdev = omap_fbdev_init(dev);
  532. /* store off drm_device for use in pm ops */
  533. dev_set_drvdata(dev->dev, dev);
  534. drm_kms_helper_poll_init(dev);
  535. return 0;
  536. }
  537. static int dev_unload(struct drm_device *dev)
  538. {
  539. struct omap_drm_private *priv = dev->dev_private;
  540. DBG("unload: dev=%p", dev);
  541. drm_kms_helper_poll_fini(dev);
  542. if (priv->fbdev)
  543. omap_fbdev_free(dev);
  544. omap_modeset_free(dev);
  545. omap_gem_deinit(dev);
  546. destroy_workqueue(priv->wq);
  547. drm_vblank_cleanup(dev);
  548. omap_drm_irq_uninstall(dev);
  549. kfree(dev->dev_private);
  550. dev->dev_private = NULL;
  551. dev_set_drvdata(dev->dev, NULL);
  552. return 0;
  553. }
  554. static int dev_open(struct drm_device *dev, struct drm_file *file)
  555. {
  556. file->driver_priv = NULL;
  557. DBG("open: dev=%p, file=%p", dev, file);
  558. return 0;
  559. }
  560. /**
  561. * lastclose - clean up after all DRM clients have exited
  562. * @dev: DRM device
  563. *
  564. * Take care of cleaning up after all DRM clients have exited. In the
  565. * mode setting case, we want to restore the kernel's initial mode (just
  566. * in case the last client left us in a bad state).
  567. */
  568. static void dev_lastclose(struct drm_device *dev)
  569. {
  570. int i;
  571. /* we don't support vga_switcheroo.. so just make sure the fbdev
  572. * mode is active
  573. */
  574. struct omap_drm_private *priv = dev->dev_private;
  575. int ret;
  576. DBG("lastclose: dev=%p", dev);
  577. /* need to restore default rotation state.. not sure
  578. * if there is a cleaner way to restore properties to
  579. * default state? Maybe a flag that properties should
  580. * automatically be restored to default state on
  581. * lastclose?
  582. */
  583. for (i = 0; i < priv->num_crtcs; i++) {
  584. struct drm_crtc *crtc = priv->crtcs[i];
  585. if (!crtc->primary->rotation_property)
  586. continue;
  587. drm_object_property_set_value(&crtc->base,
  588. crtc->primary->rotation_property,
  589. DRM_ROTATE_0);
  590. }
  591. for (i = 0; i < priv->num_planes; i++) {
  592. struct drm_plane *plane = priv->planes[i];
  593. if (!plane->rotation_property)
  594. continue;
  595. drm_object_property_set_value(&plane->base,
  596. plane->rotation_property,
  597. DRM_ROTATE_0);
  598. }
  599. if (priv->fbdev) {
  600. ret = drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
  601. if (ret)
  602. DBG("failed to restore crtc mode");
  603. }
  604. }
  605. static const struct vm_operations_struct omap_gem_vm_ops = {
  606. .fault = omap_gem_fault,
  607. .open = drm_gem_vm_open,
  608. .close = drm_gem_vm_close,
  609. };
  610. static const struct file_operations omapdriver_fops = {
  611. .owner = THIS_MODULE,
  612. .open = drm_open,
  613. .unlocked_ioctl = drm_ioctl,
  614. .release = drm_release,
  615. .mmap = omap_gem_mmap,
  616. .poll = drm_poll,
  617. .read = drm_read,
  618. .llseek = noop_llseek,
  619. };
  620. static struct drm_driver omap_drm_driver = {
  621. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  622. DRIVER_ATOMIC,
  623. .load = dev_load,
  624. .unload = dev_unload,
  625. .open = dev_open,
  626. .lastclose = dev_lastclose,
  627. .get_vblank_counter = drm_vblank_no_hw_counter,
  628. .enable_vblank = omap_irq_enable_vblank,
  629. .disable_vblank = omap_irq_disable_vblank,
  630. #ifdef CONFIG_DEBUG_FS
  631. .debugfs_init = omap_debugfs_init,
  632. .debugfs_cleanup = omap_debugfs_cleanup,
  633. #endif
  634. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  635. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  636. .gem_prime_export = omap_gem_prime_export,
  637. .gem_prime_import = omap_gem_prime_import,
  638. .gem_free_object = omap_gem_free_object,
  639. .gem_vm_ops = &omap_gem_vm_ops,
  640. .dumb_create = omap_gem_dumb_create,
  641. .dumb_map_offset = omap_gem_dumb_map_offset,
  642. .dumb_destroy = drm_gem_dumb_destroy,
  643. .ioctls = ioctls,
  644. .num_ioctls = DRM_OMAP_NUM_IOCTLS,
  645. .fops = &omapdriver_fops,
  646. .name = DRIVER_NAME,
  647. .desc = DRIVER_DESC,
  648. .date = DRIVER_DATE,
  649. .major = DRIVER_MAJOR,
  650. .minor = DRIVER_MINOR,
  651. .patchlevel = DRIVER_PATCHLEVEL,
  652. };
  653. static int pdev_probe(struct platform_device *device)
  654. {
  655. int r;
  656. if (omapdss_is_initialized() == false)
  657. return -EPROBE_DEFER;
  658. omap_crtc_pre_init();
  659. r = omap_connect_dssdevs();
  660. if (r) {
  661. omap_crtc_pre_uninit();
  662. return r;
  663. }
  664. DBG("%s", device->name);
  665. return drm_platform_init(&omap_drm_driver, device);
  666. }
  667. static int pdev_remove(struct platform_device *device)
  668. {
  669. DBG("");
  670. drm_put_dev(platform_get_drvdata(device));
  671. omap_disconnect_dssdevs();
  672. omap_crtc_pre_uninit();
  673. return 0;
  674. }
  675. #ifdef CONFIG_PM_SLEEP
  676. static int omap_drm_suspend_all_displays(void)
  677. {
  678. struct omap_dss_device *dssdev = NULL;
  679. for_each_dss_dev(dssdev) {
  680. if (!dssdev->driver)
  681. continue;
  682. if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
  683. dssdev->driver->disable(dssdev);
  684. dssdev->activate_after_resume = true;
  685. } else {
  686. dssdev->activate_after_resume = false;
  687. }
  688. }
  689. return 0;
  690. }
  691. static int omap_drm_resume_all_displays(void)
  692. {
  693. struct omap_dss_device *dssdev = NULL;
  694. for_each_dss_dev(dssdev) {
  695. if (!dssdev->driver)
  696. continue;
  697. if (dssdev->activate_after_resume) {
  698. dssdev->driver->enable(dssdev);
  699. dssdev->activate_after_resume = false;
  700. }
  701. }
  702. return 0;
  703. }
  704. static int omap_drm_suspend(struct device *dev)
  705. {
  706. struct drm_device *drm_dev = dev_get_drvdata(dev);
  707. drm_kms_helper_poll_disable(drm_dev);
  708. drm_modeset_lock_all(drm_dev);
  709. omap_drm_suspend_all_displays();
  710. drm_modeset_unlock_all(drm_dev);
  711. return 0;
  712. }
  713. static int omap_drm_resume(struct device *dev)
  714. {
  715. struct drm_device *drm_dev = dev_get_drvdata(dev);
  716. drm_modeset_lock_all(drm_dev);
  717. omap_drm_resume_all_displays();
  718. drm_modeset_unlock_all(drm_dev);
  719. drm_kms_helper_poll_enable(drm_dev);
  720. return omap_gem_resume(dev);
  721. }
  722. #endif
  723. static SIMPLE_DEV_PM_OPS(omapdrm_pm_ops, omap_drm_suspend, omap_drm_resume);
  724. static struct platform_driver pdev = {
  725. .driver = {
  726. .name = DRIVER_NAME,
  727. .pm = &omapdrm_pm_ops,
  728. },
  729. .probe = pdev_probe,
  730. .remove = pdev_remove,
  731. };
  732. static struct platform_driver * const drivers[] = {
  733. &omap_dmm_driver,
  734. &pdev,
  735. };
  736. static int __init omap_drm_init(void)
  737. {
  738. DBG("init");
  739. return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
  740. }
  741. static void __exit omap_drm_fini(void)
  742. {
  743. DBG("fini");
  744. platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
  745. }
  746. /* need late_initcall() so we load after dss_driver's are loaded */
  747. late_initcall(omap_drm_init);
  748. module_exit(omap_drm_fini);
  749. MODULE_AUTHOR("Rob Clark <rob@ti.com>");
  750. MODULE_DESCRIPTION("OMAP DRM Display Driver");
  751. MODULE_ALIAS("platform:" DRIVER_NAME);
  752. MODULE_LICENSE("GPL v2");