adreno_device.c 6.2 KB

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  1. /*
  2. * Copyright (C) 2013-2014 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * Copyright (c) 2014 The Linux Foundation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include "adreno_gpu.h"
  20. #define ANY_ID 0xff
  21. bool hang_debug = false;
  22. MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
  23. module_param_named(hang_debug, hang_debug, bool, 0600);
  24. static const struct adreno_info gpulist[] = {
  25. {
  26. .rev = ADRENO_REV(3, 0, 5, ANY_ID),
  27. .revn = 305,
  28. .name = "A305",
  29. .pm4fw = "a300_pm4.fw",
  30. .pfpfw = "a300_pfp.fw",
  31. .gmem = SZ_256K,
  32. .init = a3xx_gpu_init,
  33. }, {
  34. .rev = ADRENO_REV(3, 0, 6, 0),
  35. .revn = 307, /* because a305c is revn==306 */
  36. .name = "A306",
  37. .pm4fw = "a300_pm4.fw",
  38. .pfpfw = "a300_pfp.fw",
  39. .gmem = SZ_128K,
  40. .init = a3xx_gpu_init,
  41. }, {
  42. .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
  43. .revn = 320,
  44. .name = "A320",
  45. .pm4fw = "a300_pm4.fw",
  46. .pfpfw = "a300_pfp.fw",
  47. .gmem = SZ_512K,
  48. .init = a3xx_gpu_init,
  49. }, {
  50. .rev = ADRENO_REV(3, 3, 0, ANY_ID),
  51. .revn = 330,
  52. .name = "A330",
  53. .pm4fw = "a330_pm4.fw",
  54. .pfpfw = "a330_pfp.fw",
  55. .gmem = SZ_1M,
  56. .init = a3xx_gpu_init,
  57. }, {
  58. .rev = ADRENO_REV(4, 2, 0, ANY_ID),
  59. .revn = 420,
  60. .name = "A420",
  61. .pm4fw = "a420_pm4.fw",
  62. .pfpfw = "a420_pfp.fw",
  63. .gmem = (SZ_1M + SZ_512K),
  64. .init = a4xx_gpu_init,
  65. }, {
  66. .rev = ADRENO_REV(4, 3, 0, ANY_ID),
  67. .revn = 430,
  68. .name = "A430",
  69. .pm4fw = "a420_pm4.fw",
  70. .pfpfw = "a420_pfp.fw",
  71. .gmem = (SZ_1M + SZ_512K),
  72. .init = a4xx_gpu_init,
  73. },
  74. };
  75. MODULE_FIRMWARE("a300_pm4.fw");
  76. MODULE_FIRMWARE("a300_pfp.fw");
  77. MODULE_FIRMWARE("a330_pm4.fw");
  78. MODULE_FIRMWARE("a330_pfp.fw");
  79. MODULE_FIRMWARE("a420_pm4.fw");
  80. MODULE_FIRMWARE("a420_pfp.fw");
  81. static inline bool _rev_match(uint8_t entry, uint8_t id)
  82. {
  83. return (entry == ANY_ID) || (entry == id);
  84. }
  85. const struct adreno_info *adreno_info(struct adreno_rev rev)
  86. {
  87. int i;
  88. /* identify gpu: */
  89. for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
  90. const struct adreno_info *info = &gpulist[i];
  91. if (_rev_match(info->rev.core, rev.core) &&
  92. _rev_match(info->rev.major, rev.major) &&
  93. _rev_match(info->rev.minor, rev.minor) &&
  94. _rev_match(info->rev.patchid, rev.patchid))
  95. return info;
  96. }
  97. return NULL;
  98. }
  99. struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
  100. {
  101. struct msm_drm_private *priv = dev->dev_private;
  102. struct platform_device *pdev = priv->gpu_pdev;
  103. struct adreno_platform_config *config;
  104. struct adreno_rev rev;
  105. const struct adreno_info *info;
  106. struct msm_gpu *gpu = NULL;
  107. if (!pdev) {
  108. dev_err(dev->dev, "no adreno device\n");
  109. return NULL;
  110. }
  111. config = pdev->dev.platform_data;
  112. rev = config->rev;
  113. info = adreno_info(config->rev);
  114. if (!info) {
  115. dev_warn(dev->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
  116. rev.core, rev.major, rev.minor, rev.patchid);
  117. return NULL;
  118. }
  119. DBG("Found GPU: %u.%u.%u.%u", rev.core, rev.major,
  120. rev.minor, rev.patchid);
  121. gpu = info->init(dev);
  122. if (IS_ERR(gpu)) {
  123. dev_warn(dev->dev, "failed to load adreno gpu\n");
  124. gpu = NULL;
  125. /* not fatal */
  126. }
  127. if (gpu) {
  128. int ret;
  129. mutex_lock(&dev->struct_mutex);
  130. gpu->funcs->pm_resume(gpu);
  131. mutex_unlock(&dev->struct_mutex);
  132. ret = gpu->funcs->hw_init(gpu);
  133. if (ret) {
  134. dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
  135. gpu->funcs->destroy(gpu);
  136. gpu = NULL;
  137. } else {
  138. /* give inactive pm a chance to kick in: */
  139. msm_gpu_retire(gpu);
  140. }
  141. }
  142. return gpu;
  143. }
  144. static void set_gpu_pdev(struct drm_device *dev,
  145. struct platform_device *pdev)
  146. {
  147. struct msm_drm_private *priv = dev->dev_private;
  148. priv->gpu_pdev = pdev;
  149. }
  150. static int adreno_bind(struct device *dev, struct device *master, void *data)
  151. {
  152. static struct adreno_platform_config config = {};
  153. struct device_node *child, *node = dev->of_node;
  154. u32 val;
  155. int ret;
  156. ret = of_property_read_u32(node, "qcom,chipid", &val);
  157. if (ret) {
  158. dev_err(dev, "could not find chipid: %d\n", ret);
  159. return ret;
  160. }
  161. config.rev = ADRENO_REV((val >> 24) & 0xff,
  162. (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
  163. /* find clock rates: */
  164. config.fast_rate = 0;
  165. config.slow_rate = ~0;
  166. for_each_child_of_node(node, child) {
  167. if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
  168. struct device_node *pwrlvl;
  169. for_each_child_of_node(child, pwrlvl) {
  170. ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
  171. if (ret) {
  172. dev_err(dev, "could not find gpu-freq: %d\n", ret);
  173. return ret;
  174. }
  175. config.fast_rate = max(config.fast_rate, val);
  176. config.slow_rate = min(config.slow_rate, val);
  177. }
  178. }
  179. }
  180. if (!config.fast_rate) {
  181. dev_err(dev, "could not find clk rates\n");
  182. return -ENXIO;
  183. }
  184. dev->platform_data = &config;
  185. set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
  186. return 0;
  187. }
  188. static void adreno_unbind(struct device *dev, struct device *master,
  189. void *data)
  190. {
  191. set_gpu_pdev(dev_get_drvdata(master), NULL);
  192. }
  193. static const struct component_ops a3xx_ops = {
  194. .bind = adreno_bind,
  195. .unbind = adreno_unbind,
  196. };
  197. static int adreno_probe(struct platform_device *pdev)
  198. {
  199. return component_add(&pdev->dev, &a3xx_ops);
  200. }
  201. static int adreno_remove(struct platform_device *pdev)
  202. {
  203. component_del(&pdev->dev, &a3xx_ops);
  204. return 0;
  205. }
  206. static const struct of_device_id dt_match[] = {
  207. { .compatible = "qcom,adreno-3xx" },
  208. /* for backwards compat w/ downstream kgsl DT files: */
  209. { .compatible = "qcom,kgsl-3d0" },
  210. {}
  211. };
  212. static struct platform_driver adreno_driver = {
  213. .probe = adreno_probe,
  214. .remove = adreno_remove,
  215. .driver = {
  216. .name = "adreno",
  217. .of_match_table = dt_match,
  218. },
  219. };
  220. void __init adreno_register(void)
  221. {
  222. platform_driver_register(&adreno_driver);
  223. }
  224. void __exit adreno_unregister(void)
  225. {
  226. platform_driver_unregister(&adreno_driver);
  227. }