mtk_drm_drv.c 15 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. * Author: YT SHEN <yt.shen@mediatek.com>
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License version 2 as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. */
  14. #include <drm/drmP.h>
  15. #include <drm/drm_atomic.h>
  16. #include <drm/drm_atomic_helper.h>
  17. #include <drm/drm_crtc_helper.h>
  18. #include <drm/drm_gem.h>
  19. #include <drm/drm_gem_cma_helper.h>
  20. #include <drm/drm_of.h>
  21. #include <linux/component.h>
  22. #include <linux/iommu.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_platform.h>
  25. #include <linux/pm_runtime.h>
  26. #include "mtk_drm_crtc.h"
  27. #include "mtk_drm_ddp.h"
  28. #include "mtk_drm_ddp_comp.h"
  29. #include "mtk_drm_drv.h"
  30. #include "mtk_drm_fb.h"
  31. #include "mtk_drm_gem.h"
  32. #define DRIVER_NAME "mediatek"
  33. #define DRIVER_DESC "Mediatek SoC DRM"
  34. #define DRIVER_DATE "20150513"
  35. #define DRIVER_MAJOR 1
  36. #define DRIVER_MINOR 0
  37. static void mtk_atomic_schedule(struct mtk_drm_private *private,
  38. struct drm_atomic_state *state)
  39. {
  40. private->commit.state = state;
  41. schedule_work(&private->commit.work);
  42. }
  43. static void mtk_atomic_wait_for_fences(struct drm_atomic_state *state)
  44. {
  45. struct drm_plane *plane;
  46. struct drm_plane_state *plane_state;
  47. int i;
  48. for_each_plane_in_state(state, plane, plane_state, i)
  49. mtk_fb_wait(plane->state->fb);
  50. }
  51. static void mtk_atomic_complete(struct mtk_drm_private *private,
  52. struct drm_atomic_state *state)
  53. {
  54. struct drm_device *drm = private->drm;
  55. mtk_atomic_wait_for_fences(state);
  56. /*
  57. * Mediatek drm supports runtime PM, so plane registers cannot be
  58. * written when their crtc is disabled.
  59. *
  60. * The comment for drm_atomic_helper_commit states:
  61. * For drivers supporting runtime PM the recommended sequence is
  62. *
  63. * drm_atomic_helper_commit_modeset_disables(dev, state);
  64. * drm_atomic_helper_commit_modeset_enables(dev, state);
  65. * drm_atomic_helper_commit_planes(dev, state,
  66. * DRM_PLANE_COMMIT_ACTIVE_ONLY);
  67. *
  68. * See the kerneldoc entries for these three functions for more details.
  69. */
  70. drm_atomic_helper_commit_modeset_disables(drm, state);
  71. drm_atomic_helper_commit_modeset_enables(drm, state);
  72. drm_atomic_helper_commit_planes(drm, state,
  73. DRM_PLANE_COMMIT_ACTIVE_ONLY);
  74. drm_atomic_helper_wait_for_vblanks(drm, state);
  75. drm_atomic_helper_cleanup_planes(drm, state);
  76. drm_atomic_state_put(state);
  77. }
  78. static void mtk_atomic_work(struct work_struct *work)
  79. {
  80. struct mtk_drm_private *private = container_of(work,
  81. struct mtk_drm_private, commit.work);
  82. mtk_atomic_complete(private, private->commit.state);
  83. }
  84. static int mtk_atomic_commit(struct drm_device *drm,
  85. struct drm_atomic_state *state,
  86. bool async)
  87. {
  88. struct mtk_drm_private *private = drm->dev_private;
  89. int ret;
  90. ret = drm_atomic_helper_prepare_planes(drm, state);
  91. if (ret)
  92. return ret;
  93. mutex_lock(&private->commit.lock);
  94. flush_work(&private->commit.work);
  95. drm_atomic_helper_swap_state(state, true);
  96. drm_atomic_state_get(state);
  97. if (async)
  98. mtk_atomic_schedule(private, state);
  99. else
  100. mtk_atomic_complete(private, state);
  101. mutex_unlock(&private->commit.lock);
  102. return 0;
  103. }
  104. static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = {
  105. .fb_create = mtk_drm_mode_fb_create,
  106. .atomic_check = drm_atomic_helper_check,
  107. .atomic_commit = mtk_atomic_commit,
  108. };
  109. static const enum mtk_ddp_comp_id mtk_ddp_main[] = {
  110. DDP_COMPONENT_OVL0,
  111. DDP_COMPONENT_COLOR0,
  112. DDP_COMPONENT_AAL,
  113. DDP_COMPONENT_OD,
  114. DDP_COMPONENT_RDMA0,
  115. DDP_COMPONENT_UFOE,
  116. DDP_COMPONENT_DSI0,
  117. DDP_COMPONENT_PWM0,
  118. };
  119. static const enum mtk_ddp_comp_id mtk_ddp_ext[] = {
  120. DDP_COMPONENT_OVL1,
  121. DDP_COMPONENT_COLOR1,
  122. DDP_COMPONENT_GAMMA,
  123. DDP_COMPONENT_RDMA1,
  124. DDP_COMPONENT_DPI0,
  125. };
  126. static int mtk_drm_kms_init(struct drm_device *drm)
  127. {
  128. struct mtk_drm_private *private = drm->dev_private;
  129. struct platform_device *pdev;
  130. struct device_node *np;
  131. int ret;
  132. if (!iommu_present(&platform_bus_type))
  133. return -EPROBE_DEFER;
  134. pdev = of_find_device_by_node(private->mutex_node);
  135. if (!pdev) {
  136. dev_err(drm->dev, "Waiting for disp-mutex device %s\n",
  137. private->mutex_node->full_name);
  138. of_node_put(private->mutex_node);
  139. return -EPROBE_DEFER;
  140. }
  141. private->mutex_dev = &pdev->dev;
  142. drm_mode_config_init(drm);
  143. drm->mode_config.min_width = 64;
  144. drm->mode_config.min_height = 64;
  145. /*
  146. * set max width and height as default value(4096x4096).
  147. * this value would be used to check framebuffer size limitation
  148. * at drm_mode_addfb().
  149. */
  150. drm->mode_config.max_width = 4096;
  151. drm->mode_config.max_height = 4096;
  152. drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
  153. ret = component_bind_all(drm->dev, drm);
  154. if (ret)
  155. goto err_config_cleanup;
  156. /*
  157. * We currently support two fixed data streams, each optional,
  158. * and each statically assigned to a crtc:
  159. * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ...
  160. */
  161. ret = mtk_drm_crtc_create(drm, mtk_ddp_main, ARRAY_SIZE(mtk_ddp_main));
  162. if (ret < 0)
  163. goto err_component_unbind;
  164. /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */
  165. ret = mtk_drm_crtc_create(drm, mtk_ddp_ext, ARRAY_SIZE(mtk_ddp_ext));
  166. if (ret < 0)
  167. goto err_component_unbind;
  168. /* Use OVL device for all DMA memory allocations */
  169. np = private->comp_node[mtk_ddp_main[0]] ?:
  170. private->comp_node[mtk_ddp_ext[0]];
  171. pdev = of_find_device_by_node(np);
  172. if (!pdev) {
  173. ret = -ENODEV;
  174. dev_err(drm->dev, "Need at least one OVL device\n");
  175. goto err_component_unbind;
  176. }
  177. private->dma_dev = &pdev->dev;
  178. /*
  179. * We don't use the drm_irq_install() helpers provided by the DRM
  180. * core, so we need to set this manually in order to allow the
  181. * DRM_IOCTL_WAIT_VBLANK to operate correctly.
  182. */
  183. drm->irq_enabled = true;
  184. ret = drm_vblank_init(drm, MAX_CRTC);
  185. if (ret < 0)
  186. goto err_component_unbind;
  187. drm_kms_helper_poll_init(drm);
  188. drm_mode_config_reset(drm);
  189. return 0;
  190. err_component_unbind:
  191. component_unbind_all(drm->dev, drm);
  192. err_config_cleanup:
  193. drm_mode_config_cleanup(drm);
  194. return ret;
  195. }
  196. static void mtk_drm_kms_deinit(struct drm_device *drm)
  197. {
  198. drm_kms_helper_poll_fini(drm);
  199. drm_vblank_cleanup(drm);
  200. component_unbind_all(drm->dev, drm);
  201. drm_mode_config_cleanup(drm);
  202. }
  203. static const struct file_operations mtk_drm_fops = {
  204. .owner = THIS_MODULE,
  205. .open = drm_open,
  206. .release = drm_release,
  207. .unlocked_ioctl = drm_ioctl,
  208. .mmap = mtk_drm_gem_mmap,
  209. .poll = drm_poll,
  210. .read = drm_read,
  211. .compat_ioctl = drm_compat_ioctl,
  212. };
  213. static struct drm_driver mtk_drm_driver = {
  214. .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
  215. DRIVER_ATOMIC,
  216. .get_vblank_counter = drm_vblank_no_hw_counter,
  217. .enable_vblank = mtk_drm_crtc_enable_vblank,
  218. .disable_vblank = mtk_drm_crtc_disable_vblank,
  219. .gem_free_object_unlocked = mtk_drm_gem_free_object,
  220. .gem_vm_ops = &drm_gem_cma_vm_ops,
  221. .dumb_create = mtk_drm_gem_dumb_create,
  222. .dumb_map_offset = mtk_drm_gem_dumb_map_offset,
  223. .dumb_destroy = drm_gem_dumb_destroy,
  224. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  225. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  226. .gem_prime_export = drm_gem_prime_export,
  227. .gem_prime_import = drm_gem_prime_import,
  228. .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table,
  229. .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table,
  230. .gem_prime_mmap = mtk_drm_gem_mmap_buf,
  231. .fops = &mtk_drm_fops,
  232. .name = DRIVER_NAME,
  233. .desc = DRIVER_DESC,
  234. .date = DRIVER_DATE,
  235. .major = DRIVER_MAJOR,
  236. .minor = DRIVER_MINOR,
  237. };
  238. static int compare_of(struct device *dev, void *data)
  239. {
  240. return dev->of_node == data;
  241. }
  242. static int mtk_drm_bind(struct device *dev)
  243. {
  244. struct mtk_drm_private *private = dev_get_drvdata(dev);
  245. struct drm_device *drm;
  246. int ret;
  247. drm = drm_dev_alloc(&mtk_drm_driver, dev);
  248. if (IS_ERR(drm))
  249. return PTR_ERR(drm);
  250. drm->dev_private = private;
  251. private->drm = drm;
  252. ret = mtk_drm_kms_init(drm);
  253. if (ret < 0)
  254. goto err_free;
  255. ret = drm_dev_register(drm, 0);
  256. if (ret < 0)
  257. goto err_deinit;
  258. return 0;
  259. err_deinit:
  260. mtk_drm_kms_deinit(drm);
  261. err_free:
  262. drm_dev_unref(drm);
  263. return ret;
  264. }
  265. static void mtk_drm_unbind(struct device *dev)
  266. {
  267. struct mtk_drm_private *private = dev_get_drvdata(dev);
  268. drm_put_dev(private->drm);
  269. private->drm = NULL;
  270. }
  271. static const struct component_master_ops mtk_drm_ops = {
  272. .bind = mtk_drm_bind,
  273. .unbind = mtk_drm_unbind,
  274. };
  275. static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
  276. { .compatible = "mediatek,mt8173-disp-ovl", .data = (void *)MTK_DISP_OVL },
  277. { .compatible = "mediatek,mt8173-disp-rdma", .data = (void *)MTK_DISP_RDMA },
  278. { .compatible = "mediatek,mt8173-disp-wdma", .data = (void *)MTK_DISP_WDMA },
  279. { .compatible = "mediatek,mt8173-disp-color", .data = (void *)MTK_DISP_COLOR },
  280. { .compatible = "mediatek,mt8173-disp-aal", .data = (void *)MTK_DISP_AAL},
  281. { .compatible = "mediatek,mt8173-disp-gamma", .data = (void *)MTK_DISP_GAMMA, },
  282. { .compatible = "mediatek,mt8173-disp-ufoe", .data = (void *)MTK_DISP_UFOE },
  283. { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
  284. { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
  285. { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
  286. { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
  287. { .compatible = "mediatek,mt8173-disp-od", .data = (void *)MTK_DISP_OD },
  288. { }
  289. };
  290. static int mtk_drm_probe(struct platform_device *pdev)
  291. {
  292. struct device *dev = &pdev->dev;
  293. struct mtk_drm_private *private;
  294. struct resource *mem;
  295. struct device_node *node;
  296. struct component_match *match = NULL;
  297. int ret;
  298. int i;
  299. private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
  300. if (!private)
  301. return -ENOMEM;
  302. mutex_init(&private->commit.lock);
  303. INIT_WORK(&private->commit.work, mtk_atomic_work);
  304. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  305. private->config_regs = devm_ioremap_resource(dev, mem);
  306. if (IS_ERR(private->config_regs)) {
  307. ret = PTR_ERR(private->config_regs);
  308. dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
  309. ret);
  310. return ret;
  311. }
  312. /* Iterate over sibling DISP function blocks */
  313. for_each_child_of_node(dev->of_node->parent, node) {
  314. const struct of_device_id *of_id;
  315. enum mtk_ddp_comp_type comp_type;
  316. int comp_id;
  317. of_id = of_match_node(mtk_ddp_comp_dt_ids, node);
  318. if (!of_id)
  319. continue;
  320. if (!of_device_is_available(node)) {
  321. dev_dbg(dev, "Skipping disabled component %s\n",
  322. node->full_name);
  323. continue;
  324. }
  325. comp_type = (enum mtk_ddp_comp_type)of_id->data;
  326. if (comp_type == MTK_DISP_MUTEX) {
  327. private->mutex_node = of_node_get(node);
  328. continue;
  329. }
  330. comp_id = mtk_ddp_comp_get_id(node, comp_type);
  331. if (comp_id < 0) {
  332. dev_warn(dev, "Skipping unknown component %s\n",
  333. node->full_name);
  334. continue;
  335. }
  336. private->comp_node[comp_id] = of_node_get(node);
  337. /*
  338. * Currently only the OVL, RDMA, DSI, and DPI blocks have
  339. * separate component platform drivers and initialize their own
  340. * DDP component structure. The others are initialized here.
  341. */
  342. if (comp_type == MTK_DISP_OVL ||
  343. comp_type == MTK_DISP_RDMA ||
  344. comp_type == MTK_DSI ||
  345. comp_type == MTK_DPI) {
  346. dev_info(dev, "Adding component match for %s\n",
  347. node->full_name);
  348. drm_of_component_match_add(dev, &match, compare_of,
  349. node);
  350. } else {
  351. struct mtk_ddp_comp *comp;
  352. comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
  353. if (!comp) {
  354. ret = -ENOMEM;
  355. goto err_node;
  356. }
  357. ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL);
  358. if (ret)
  359. goto err_node;
  360. private->ddp_comp[comp_id] = comp;
  361. }
  362. }
  363. if (!private->mutex_node) {
  364. dev_err(dev, "Failed to find disp-mutex node\n");
  365. ret = -ENODEV;
  366. goto err_node;
  367. }
  368. pm_runtime_enable(dev);
  369. platform_set_drvdata(pdev, private);
  370. ret = component_master_add_with_match(dev, &mtk_drm_ops, match);
  371. if (ret)
  372. goto err_pm;
  373. return 0;
  374. err_pm:
  375. pm_runtime_disable(dev);
  376. err_node:
  377. of_node_put(private->mutex_node);
  378. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  379. of_node_put(private->comp_node[i]);
  380. return ret;
  381. }
  382. static int mtk_drm_remove(struct platform_device *pdev)
  383. {
  384. struct mtk_drm_private *private = platform_get_drvdata(pdev);
  385. struct drm_device *drm = private->drm;
  386. int i;
  387. drm_dev_unregister(drm);
  388. mtk_drm_kms_deinit(drm);
  389. drm_dev_unref(drm);
  390. component_master_del(&pdev->dev, &mtk_drm_ops);
  391. pm_runtime_disable(&pdev->dev);
  392. of_node_put(private->mutex_node);
  393. for (i = 0; i < DDP_COMPONENT_ID_MAX; i++)
  394. of_node_put(private->comp_node[i]);
  395. return 0;
  396. }
  397. #ifdef CONFIG_PM_SLEEP
  398. static int mtk_drm_sys_suspend(struct device *dev)
  399. {
  400. struct mtk_drm_private *private = dev_get_drvdata(dev);
  401. struct drm_device *drm = private->drm;
  402. drm_kms_helper_poll_disable(drm);
  403. private->suspend_state = drm_atomic_helper_suspend(drm);
  404. if (IS_ERR(private->suspend_state)) {
  405. drm_kms_helper_poll_enable(drm);
  406. return PTR_ERR(private->suspend_state);
  407. }
  408. DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n");
  409. return 0;
  410. }
  411. static int mtk_drm_sys_resume(struct device *dev)
  412. {
  413. struct mtk_drm_private *private = dev_get_drvdata(dev);
  414. struct drm_device *drm = private->drm;
  415. drm_atomic_helper_resume(drm, private->suspend_state);
  416. drm_kms_helper_poll_enable(drm);
  417. DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n");
  418. return 0;
  419. }
  420. #endif
  421. static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
  422. mtk_drm_sys_resume);
  423. static const struct of_device_id mtk_drm_of_ids[] = {
  424. { .compatible = "mediatek,mt8173-mmsys", },
  425. { }
  426. };
  427. static struct platform_driver mtk_drm_platform_driver = {
  428. .probe = mtk_drm_probe,
  429. .remove = mtk_drm_remove,
  430. .driver = {
  431. .name = "mediatek-drm",
  432. .of_match_table = mtk_drm_of_ids,
  433. .pm = &mtk_drm_pm_ops,
  434. },
  435. };
  436. static struct platform_driver * const mtk_drm_drivers[] = {
  437. &mtk_ddp_driver,
  438. &mtk_disp_ovl_driver,
  439. &mtk_disp_rdma_driver,
  440. &mtk_dpi_driver,
  441. &mtk_drm_platform_driver,
  442. &mtk_dsi_driver,
  443. &mtk_mipi_tx_driver,
  444. };
  445. static int __init mtk_drm_init(void)
  446. {
  447. int ret;
  448. int i;
  449. for (i = 0; i < ARRAY_SIZE(mtk_drm_drivers); i++) {
  450. ret = platform_driver_register(mtk_drm_drivers[i]);
  451. if (ret < 0) {
  452. pr_err("Failed to register %s driver: %d\n",
  453. mtk_drm_drivers[i]->driver.name, ret);
  454. goto err;
  455. }
  456. }
  457. return 0;
  458. err:
  459. while (--i >= 0)
  460. platform_driver_unregister(mtk_drm_drivers[i]);
  461. return ret;
  462. }
  463. static void __exit mtk_drm_exit(void)
  464. {
  465. int i;
  466. for (i = ARRAY_SIZE(mtk_drm_drivers) - 1; i >= 0; i--)
  467. platform_driver_unregister(mtk_drm_drivers[i]);
  468. }
  469. module_init(mtk_drm_init);
  470. module_exit(mtk_drm_exit);
  471. MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
  472. MODULE_DESCRIPTION("Mediatek SoC DRM driver");
  473. MODULE_LICENSE("GPL v2");