mtk_disp_ovl.c 8.2 KB

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  1. /*
  2. * Copyright (c) 2015 MediaTek Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <drm/drmP.h>
  14. #include <linux/clk.h>
  15. #include <linux/component.h>
  16. #include <linux/of_device.h>
  17. #include <linux/of_irq.h>
  18. #include <linux/platform_device.h>
  19. #include "mtk_drm_crtc.h"
  20. #include "mtk_drm_ddp_comp.h"
  21. #define DISP_REG_OVL_INTEN 0x0004
  22. #define OVL_FME_CPL_INT BIT(1)
  23. #define DISP_REG_OVL_INTSTA 0x0008
  24. #define DISP_REG_OVL_EN 0x000c
  25. #define DISP_REG_OVL_RST 0x0014
  26. #define DISP_REG_OVL_ROI_SIZE 0x0020
  27. #define DISP_REG_OVL_ROI_BGCLR 0x0028
  28. #define DISP_REG_OVL_SRC_CON 0x002c
  29. #define DISP_REG_OVL_CON(n) (0x0030 + 0x20 * (n))
  30. #define DISP_REG_OVL_SRC_SIZE(n) (0x0038 + 0x20 * (n))
  31. #define DISP_REG_OVL_OFFSET(n) (0x003c + 0x20 * (n))
  32. #define DISP_REG_OVL_PITCH(n) (0x0044 + 0x20 * (n))
  33. #define DISP_REG_OVL_RDMA_CTRL(n) (0x00c0 + 0x20 * (n))
  34. #define DISP_REG_OVL_RDMA_GMC(n) (0x00c8 + 0x20 * (n))
  35. #define DISP_REG_OVL_ADDR(n) (0x0f40 + 0x20 * (n))
  36. #define OVL_RDMA_MEM_GMC 0x40402020
  37. #define OVL_CON_BYTE_SWAP BIT(24)
  38. #define OVL_CON_CLRFMT_RGB565 (0 << 12)
  39. #define OVL_CON_CLRFMT_RGB888 (1 << 12)
  40. #define OVL_CON_CLRFMT_RGBA8888 (2 << 12)
  41. #define OVL_CON_CLRFMT_ARGB8888 (3 << 12)
  42. #define OVL_CON_AEN BIT(8)
  43. #define OVL_CON_ALPHA 0xff
  44. /**
  45. * struct mtk_disp_ovl - DISP_OVL driver structure
  46. * @ddp_comp - structure containing type enum and hardware resources
  47. * @crtc - associated crtc to report vblank events to
  48. */
  49. struct mtk_disp_ovl {
  50. struct mtk_ddp_comp ddp_comp;
  51. struct drm_crtc *crtc;
  52. };
  53. static irqreturn_t mtk_disp_ovl_irq_handler(int irq, void *dev_id)
  54. {
  55. struct mtk_disp_ovl *priv = dev_id;
  56. struct mtk_ddp_comp *ovl = &priv->ddp_comp;
  57. /* Clear frame completion interrupt */
  58. writel(0x0, ovl->regs + DISP_REG_OVL_INTSTA);
  59. if (!priv->crtc)
  60. return IRQ_NONE;
  61. mtk_crtc_ddp_irq(priv->crtc, ovl);
  62. return IRQ_HANDLED;
  63. }
  64. static void mtk_ovl_enable_vblank(struct mtk_ddp_comp *comp,
  65. struct drm_crtc *crtc)
  66. {
  67. struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
  68. ddp_comp);
  69. priv->crtc = crtc;
  70. writel_relaxed(OVL_FME_CPL_INT, comp->regs + DISP_REG_OVL_INTEN);
  71. }
  72. static void mtk_ovl_disable_vblank(struct mtk_ddp_comp *comp)
  73. {
  74. struct mtk_disp_ovl *priv = container_of(comp, struct mtk_disp_ovl,
  75. ddp_comp);
  76. priv->crtc = NULL;
  77. writel_relaxed(0x0, comp->regs + DISP_REG_OVL_INTEN);
  78. }
  79. static void mtk_ovl_start(struct mtk_ddp_comp *comp)
  80. {
  81. writel_relaxed(0x1, comp->regs + DISP_REG_OVL_EN);
  82. }
  83. static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
  84. {
  85. writel_relaxed(0x0, comp->regs + DISP_REG_OVL_EN);
  86. }
  87. static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
  88. unsigned int h, unsigned int vrefresh,
  89. unsigned int bpc)
  90. {
  91. if (w != 0 && h != 0)
  92. writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
  93. writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
  94. writel(0x1, comp->regs + DISP_REG_OVL_RST);
  95. writel(0x0, comp->regs + DISP_REG_OVL_RST);
  96. }
  97. static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
  98. {
  99. unsigned int reg;
  100. writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
  101. writel(OVL_RDMA_MEM_GMC, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
  102. reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
  103. reg = reg | BIT(idx);
  104. writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
  105. }
  106. static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
  107. {
  108. unsigned int reg;
  109. reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
  110. reg = reg & ~BIT(idx);
  111. writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
  112. writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
  113. }
  114. static unsigned int ovl_fmt_convert(unsigned int fmt)
  115. {
  116. switch (fmt) {
  117. default:
  118. case DRM_FORMAT_RGB565:
  119. return OVL_CON_CLRFMT_RGB565;
  120. case DRM_FORMAT_BGR565:
  121. return OVL_CON_CLRFMT_RGB565 | OVL_CON_BYTE_SWAP;
  122. case DRM_FORMAT_RGB888:
  123. return OVL_CON_CLRFMT_RGB888;
  124. case DRM_FORMAT_BGR888:
  125. return OVL_CON_CLRFMT_RGB888 | OVL_CON_BYTE_SWAP;
  126. case DRM_FORMAT_RGBX8888:
  127. case DRM_FORMAT_RGBA8888:
  128. return OVL_CON_CLRFMT_ARGB8888;
  129. case DRM_FORMAT_BGRX8888:
  130. case DRM_FORMAT_BGRA8888:
  131. return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP;
  132. case DRM_FORMAT_XRGB8888:
  133. case DRM_FORMAT_ARGB8888:
  134. return OVL_CON_CLRFMT_RGBA8888;
  135. case DRM_FORMAT_XBGR8888:
  136. case DRM_FORMAT_ABGR8888:
  137. return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP;
  138. }
  139. }
  140. static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
  141. struct mtk_plane_state *state)
  142. {
  143. struct mtk_plane_pending_state *pending = &state->pending;
  144. unsigned int addr = pending->addr;
  145. unsigned int pitch = pending->pitch & 0xffff;
  146. unsigned int fmt = pending->format;
  147. unsigned int offset = (pending->y << 16) | pending->x;
  148. unsigned int src_size = (pending->height << 16) | pending->width;
  149. unsigned int con;
  150. if (!pending->enable)
  151. mtk_ovl_layer_off(comp, idx);
  152. con = ovl_fmt_convert(fmt);
  153. if (idx != 0)
  154. con |= OVL_CON_AEN | OVL_CON_ALPHA;
  155. writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
  156. writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
  157. writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
  158. writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
  159. writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(idx));
  160. if (pending->enable)
  161. mtk_ovl_layer_on(comp, idx);
  162. }
  163. static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
  164. .config = mtk_ovl_config,
  165. .start = mtk_ovl_start,
  166. .stop = mtk_ovl_stop,
  167. .enable_vblank = mtk_ovl_enable_vblank,
  168. .disable_vblank = mtk_ovl_disable_vblank,
  169. .layer_on = mtk_ovl_layer_on,
  170. .layer_off = mtk_ovl_layer_off,
  171. .layer_config = mtk_ovl_layer_config,
  172. };
  173. static int mtk_disp_ovl_bind(struct device *dev, struct device *master,
  174. void *data)
  175. {
  176. struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
  177. struct drm_device *drm_dev = data;
  178. int ret;
  179. ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
  180. if (ret < 0) {
  181. dev_err(dev, "Failed to register component %s: %d\n",
  182. dev->of_node->full_name, ret);
  183. return ret;
  184. }
  185. return 0;
  186. }
  187. static void mtk_disp_ovl_unbind(struct device *dev, struct device *master,
  188. void *data)
  189. {
  190. struct mtk_disp_ovl *priv = dev_get_drvdata(dev);
  191. struct drm_device *drm_dev = data;
  192. mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
  193. }
  194. static const struct component_ops mtk_disp_ovl_component_ops = {
  195. .bind = mtk_disp_ovl_bind,
  196. .unbind = mtk_disp_ovl_unbind,
  197. };
  198. static int mtk_disp_ovl_probe(struct platform_device *pdev)
  199. {
  200. struct device *dev = &pdev->dev;
  201. struct mtk_disp_ovl *priv;
  202. int comp_id;
  203. int irq;
  204. int ret;
  205. priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
  206. if (!priv)
  207. return -ENOMEM;
  208. irq = platform_get_irq(pdev, 0);
  209. if (irq < 0)
  210. return irq;
  211. ret = devm_request_irq(dev, irq, mtk_disp_ovl_irq_handler,
  212. IRQF_TRIGGER_NONE, dev_name(dev), priv);
  213. if (ret < 0) {
  214. dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
  215. return ret;
  216. }
  217. comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_OVL);
  218. if (comp_id < 0) {
  219. dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
  220. return comp_id;
  221. }
  222. ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
  223. &mtk_disp_ovl_funcs);
  224. if (ret) {
  225. dev_err(dev, "Failed to initialize component: %d\n", ret);
  226. return ret;
  227. }
  228. platform_set_drvdata(pdev, priv);
  229. ret = component_add(dev, &mtk_disp_ovl_component_ops);
  230. if (ret)
  231. dev_err(dev, "Failed to add component: %d\n", ret);
  232. return ret;
  233. }
  234. static int mtk_disp_ovl_remove(struct platform_device *pdev)
  235. {
  236. component_del(&pdev->dev, &mtk_disp_ovl_component_ops);
  237. return 0;
  238. }
  239. static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
  240. { .compatible = "mediatek,mt8173-disp-ovl", },
  241. {},
  242. };
  243. MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
  244. struct platform_driver mtk_disp_ovl_driver = {
  245. .probe = mtk_disp_ovl_probe,
  246. .remove = mtk_disp_ovl_remove,
  247. .driver = {
  248. .name = "mediatek-disp-ovl",
  249. .owner = THIS_MODULE,
  250. .of_match_table = mtk_disp_ovl_driver_dt_match,
  251. },
  252. };