intel_uc.c 4.1 KB

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  1. /*
  2. * Copyright © 2016 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. */
  24. #include "i915_drv.h"
  25. #include "intel_uc.h"
  26. void intel_uc_init_early(struct drm_i915_private *dev_priv)
  27. {
  28. mutex_init(&dev_priv->guc.send_mutex);
  29. }
  30. /*
  31. * Read GuC command/status register (SOFT_SCRATCH_0)
  32. * Return true if it contains a response rather than a command
  33. */
  34. bool intel_guc_recv(struct drm_i915_private *dev_priv, u32 *status)
  35. {
  36. u32 val = I915_READ(SOFT_SCRATCH(0));
  37. *status = val;
  38. return INTEL_GUC_RECV_IS_RESPONSE(val);
  39. }
  40. int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
  41. {
  42. struct drm_i915_private *dev_priv = guc_to_i915(guc);
  43. u32 status;
  44. int i;
  45. int ret;
  46. if (WARN_ON(len < 1 || len > 15))
  47. return -EINVAL;
  48. mutex_lock(&guc->send_mutex);
  49. intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
  50. dev_priv->guc.action_count += 1;
  51. dev_priv->guc.action_cmd = action[0];
  52. for (i = 0; i < len; i++)
  53. I915_WRITE(SOFT_SCRATCH(i), action[i]);
  54. POSTING_READ(SOFT_SCRATCH(i - 1));
  55. I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  56. /*
  57. * Fast commands should complete in less than 10us, so sample quickly
  58. * up to that length of time, then switch to a slower sleep-wait loop.
  59. * No inte_guc_send command should ever take longer than 10ms.
  60. */
  61. ret = wait_for_us(intel_guc_recv(dev_priv, &status), 10);
  62. if (ret)
  63. ret = wait_for(intel_guc_recv(dev_priv, &status), 10);
  64. if (status != INTEL_GUC_STATUS_SUCCESS) {
  65. /*
  66. * Either the GuC explicitly returned an error (which
  67. * we convert to -EIO here) or no response at all was
  68. * received within the timeout limit (-ETIMEDOUT)
  69. */
  70. if (ret != -ETIMEDOUT)
  71. ret = -EIO;
  72. DRM_WARN("INTEL_GUC_SEND: Action 0x%X failed;"
  73. " ret=%d status=0x%08X response=0x%08X\n",
  74. action[0], ret, status, I915_READ(SOFT_SCRATCH(15)));
  75. dev_priv->guc.action_fail += 1;
  76. dev_priv->guc.action_err = ret;
  77. }
  78. dev_priv->guc.action_status = status;
  79. intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
  80. mutex_unlock(&guc->send_mutex);
  81. return ret;
  82. }
  83. int intel_guc_sample_forcewake(struct intel_guc *guc)
  84. {
  85. struct drm_i915_private *dev_priv = guc_to_i915(guc);
  86. u32 action[2];
  87. action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
  88. /* WaRsDisableCoarsePowerGating:skl,bxt */
  89. if (!intel_enable_rc6() || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
  90. action[1] = 0;
  91. else
  92. /* bit 0 and 1 are for Render and Media domain separately */
  93. action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
  94. return intel_guc_send(guc, action, ARRAY_SIZE(action));
  95. }
  96. int intel_guc_log_flush_complete(struct intel_guc *guc)
  97. {
  98. u32 action[] = { INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE };
  99. return intel_guc_send(guc, action, ARRAY_SIZE(action));
  100. }
  101. int intel_guc_log_flush(struct intel_guc *guc)
  102. {
  103. u32 action[] = {
  104. INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH,
  105. 0
  106. };
  107. return intel_guc_send(guc, action, ARRAY_SIZE(action));
  108. }
  109. int intel_guc_log_control(struct intel_guc *guc, u32 control_val)
  110. {
  111. u32 action[] = {
  112. INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING,
  113. control_val
  114. };
  115. return intel_guc_send(guc, action, ARRAY_SIZE(action));
  116. }