arcmsr_hba.c 125 KB

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  1. /*
  2. *******************************************************************************
  3. ** O.S : Linux
  4. ** FILE NAME : arcmsr_hba.c
  5. ** BY : Nick Cheng, C.L. Huang
  6. ** Description: SCSI RAID Device Driver for Areca RAID Controller
  7. *******************************************************************************
  8. ** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
  9. **
  10. ** Web site: www.areca.com.tw
  11. ** E-mail: support@areca.com.tw
  12. **
  13. ** This program is free software; you can redistribute it and/or modify
  14. ** it under the terms of the GNU General Public License version 2 as
  15. ** published by the Free Software Foundation.
  16. ** This program is distributed in the hope that it will be useful,
  17. ** but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. ** GNU General Public License for more details.
  20. *******************************************************************************
  21. ** Redistribution and use in source and binary forms, with or without
  22. ** modification, are permitted provided that the following conditions
  23. ** are met:
  24. ** 1. Redistributions of source code must retain the above copyright
  25. ** notice, this list of conditions and the following disclaimer.
  26. ** 2. Redistributions in binary form must reproduce the above copyright
  27. ** notice, this list of conditions and the following disclaimer in the
  28. ** documentation and/or other materials provided with the distribution.
  29. ** 3. The name of the author may not be used to endorse or promote products
  30. ** derived from this software without specific prior written permission.
  31. **
  32. ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  33. ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  34. ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  35. ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  36. ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
  37. ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  38. ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
  39. ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40. ** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
  41. ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42. *******************************************************************************
  43. ** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
  44. ** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
  45. *******************************************************************************
  46. */
  47. #include <linux/module.h>
  48. #include <linux/reboot.h>
  49. #include <linux/spinlock.h>
  50. #include <linux/pci_ids.h>
  51. #include <linux/interrupt.h>
  52. #include <linux/moduleparam.h>
  53. #include <linux/errno.h>
  54. #include <linux/types.h>
  55. #include <linux/delay.h>
  56. #include <linux/dma-mapping.h>
  57. #include <linux/timer.h>
  58. #include <linux/slab.h>
  59. #include <linux/pci.h>
  60. #include <linux/aer.h>
  61. #include <linux/circ_buf.h>
  62. #include <asm/dma.h>
  63. #include <asm/io.h>
  64. #include <asm/uaccess.h>
  65. #include <scsi/scsi_host.h>
  66. #include <scsi/scsi.h>
  67. #include <scsi/scsi_cmnd.h>
  68. #include <scsi/scsi_tcq.h>
  69. #include <scsi/scsi_device.h>
  70. #include <scsi/scsi_transport.h>
  71. #include <scsi/scsicam.h>
  72. #include "arcmsr.h"
  73. MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
  74. MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
  75. MODULE_LICENSE("Dual BSD/GPL");
  76. MODULE_VERSION(ARCMSR_DRIVER_VERSION);
  77. #define ARCMSR_SLEEPTIME 10
  78. #define ARCMSR_RETRYCOUNT 12
  79. static wait_queue_head_t wait_q;
  80. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  81. struct scsi_cmnd *cmd);
  82. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
  83. static int arcmsr_abort(struct scsi_cmnd *);
  84. static int arcmsr_bus_reset(struct scsi_cmnd *);
  85. static int arcmsr_bios_param(struct scsi_device *sdev,
  86. struct block_device *bdev, sector_t capacity, int *info);
  87. static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  88. static int arcmsr_probe(struct pci_dev *pdev,
  89. const struct pci_device_id *id);
  90. static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
  91. static int arcmsr_resume(struct pci_dev *pdev);
  92. static void arcmsr_remove(struct pci_dev *pdev);
  93. static void arcmsr_shutdown(struct pci_dev *pdev);
  94. static void arcmsr_iop_init(struct AdapterControlBlock *acb);
  95. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
  96. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
  97. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  98. u32 intmask_org);
  99. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
  100. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
  101. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
  102. static void arcmsr_request_device_map(unsigned long pacb);
  103. static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb);
  104. static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb);
  105. static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb);
  106. static void arcmsr_message_isr_bh_fn(struct work_struct *work);
  107. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
  108. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
  109. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
  110. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
  111. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
  112. static const char *arcmsr_info(struct Scsi_Host *);
  113. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
  114. static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
  115. static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
  116. int queue_depth, int reason)
  117. {
  118. if (reason != SCSI_QDEPTH_DEFAULT)
  119. return -EOPNOTSUPP;
  120. if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
  121. queue_depth = ARCMSR_MAX_CMD_PERLUN;
  122. scsi_adjust_queue_depth(sdev, queue_depth);
  123. return queue_depth;
  124. }
  125. static struct scsi_host_template arcmsr_scsi_host_template = {
  126. .module = THIS_MODULE,
  127. .name = "Areca SAS/SATA RAID driver",
  128. .info = arcmsr_info,
  129. .queuecommand = arcmsr_queue_command,
  130. .eh_abort_handler = arcmsr_abort,
  131. .eh_bus_reset_handler = arcmsr_bus_reset,
  132. .bios_param = arcmsr_bios_param,
  133. .change_queue_depth = arcmsr_adjust_disk_queue_depth,
  134. .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
  135. .this_id = ARCMSR_SCSI_INITIATOR_ID,
  136. .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
  137. .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
  138. .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
  139. .use_clustering = ENABLE_CLUSTERING,
  140. .shost_attrs = arcmsr_host_attrs,
  141. .no_write_same = 1,
  142. };
  143. static struct pci_device_id arcmsr_device_id_table[] = {
  144. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
  145. .driver_data = ACB_ADAPTER_TYPE_A},
  146. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
  147. .driver_data = ACB_ADAPTER_TYPE_A},
  148. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
  149. .driver_data = ACB_ADAPTER_TYPE_A},
  150. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
  151. .driver_data = ACB_ADAPTER_TYPE_A},
  152. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
  153. .driver_data = ACB_ADAPTER_TYPE_A},
  154. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
  155. .driver_data = ACB_ADAPTER_TYPE_B},
  156. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
  157. .driver_data = ACB_ADAPTER_TYPE_B},
  158. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
  159. .driver_data = ACB_ADAPTER_TYPE_B},
  160. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
  161. .driver_data = ACB_ADAPTER_TYPE_A},
  162. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
  163. .driver_data = ACB_ADAPTER_TYPE_D},
  164. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
  165. .driver_data = ACB_ADAPTER_TYPE_A},
  166. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
  167. .driver_data = ACB_ADAPTER_TYPE_A},
  168. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
  169. .driver_data = ACB_ADAPTER_TYPE_A},
  170. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
  171. .driver_data = ACB_ADAPTER_TYPE_A},
  172. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
  173. .driver_data = ACB_ADAPTER_TYPE_A},
  174. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
  175. .driver_data = ACB_ADAPTER_TYPE_A},
  176. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
  177. .driver_data = ACB_ADAPTER_TYPE_A},
  178. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
  179. .driver_data = ACB_ADAPTER_TYPE_A},
  180. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
  181. .driver_data = ACB_ADAPTER_TYPE_A},
  182. {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
  183. .driver_data = ACB_ADAPTER_TYPE_C},
  184. {0, 0}, /* Terminating entry */
  185. };
  186. MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
  187. static struct pci_driver arcmsr_pci_driver = {
  188. .name = "arcmsr",
  189. .id_table = arcmsr_device_id_table,
  190. .probe = arcmsr_probe,
  191. .remove = arcmsr_remove,
  192. .suspend = arcmsr_suspend,
  193. .resume = arcmsr_resume,
  194. .shutdown = arcmsr_shutdown,
  195. };
  196. /*
  197. ****************************************************************************
  198. ****************************************************************************
  199. */
  200. static void arcmsr_free_mu(struct AdapterControlBlock *acb)
  201. {
  202. switch (acb->adapter_type) {
  203. case ACB_ADAPTER_TYPE_B:
  204. case ACB_ADAPTER_TYPE_D: {
  205. dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
  206. acb->dma_coherent2, acb->dma_coherent_handle2);
  207. break;
  208. }
  209. }
  210. }
  211. static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
  212. {
  213. struct pci_dev *pdev = acb->pdev;
  214. switch (acb->adapter_type){
  215. case ACB_ADAPTER_TYPE_A:{
  216. acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
  217. if (!acb->pmuA) {
  218. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  219. return false;
  220. }
  221. break;
  222. }
  223. case ACB_ADAPTER_TYPE_B:{
  224. void __iomem *mem_base0, *mem_base1;
  225. mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
  226. if (!mem_base0) {
  227. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  228. return false;
  229. }
  230. mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
  231. if (!mem_base1) {
  232. iounmap(mem_base0);
  233. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  234. return false;
  235. }
  236. acb->mem_base0 = mem_base0;
  237. acb->mem_base1 = mem_base1;
  238. break;
  239. }
  240. case ACB_ADAPTER_TYPE_C:{
  241. acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
  242. if (!acb->pmuC) {
  243. printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
  244. return false;
  245. }
  246. if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  247. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
  248. return true;
  249. }
  250. break;
  251. }
  252. case ACB_ADAPTER_TYPE_D: {
  253. void __iomem *mem_base0;
  254. unsigned long addr, range, flags;
  255. addr = (unsigned long)pci_resource_start(pdev, 0);
  256. range = pci_resource_len(pdev, 0);
  257. flags = pci_resource_flags(pdev, 0);
  258. if (flags & IORESOURCE_CACHEABLE)
  259. mem_base0 = ioremap(addr, range);
  260. else
  261. mem_base0 = ioremap_nocache(addr, range);
  262. if (!mem_base0) {
  263. pr_notice("arcmsr%d: memory mapping region fail\n",
  264. acb->host->host_no);
  265. return false;
  266. }
  267. acb->mem_base0 = mem_base0;
  268. break;
  269. }
  270. }
  271. return true;
  272. }
  273. static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
  274. {
  275. switch (acb->adapter_type) {
  276. case ACB_ADAPTER_TYPE_A:{
  277. iounmap(acb->pmuA);
  278. }
  279. break;
  280. case ACB_ADAPTER_TYPE_B:{
  281. iounmap(acb->mem_base0);
  282. iounmap(acb->mem_base1);
  283. }
  284. break;
  285. case ACB_ADAPTER_TYPE_C:{
  286. iounmap(acb->pmuC);
  287. }
  288. break;
  289. case ACB_ADAPTER_TYPE_D:
  290. iounmap(acb->mem_base0);
  291. break;
  292. }
  293. }
  294. static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
  295. {
  296. irqreturn_t handle_state;
  297. struct AdapterControlBlock *acb = dev_id;
  298. handle_state = arcmsr_interrupt(acb);
  299. return handle_state;
  300. }
  301. static int arcmsr_bios_param(struct scsi_device *sdev,
  302. struct block_device *bdev, sector_t capacity, int *geom)
  303. {
  304. int ret, heads, sectors, cylinders, total_capacity;
  305. unsigned char *buffer;/* return copy of block device's partition table */
  306. buffer = scsi_bios_ptable(bdev);
  307. if (buffer) {
  308. ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
  309. kfree(buffer);
  310. if (ret != -1)
  311. return ret;
  312. }
  313. total_capacity = capacity;
  314. heads = 64;
  315. sectors = 32;
  316. cylinders = total_capacity / (heads * sectors);
  317. if (cylinders > 1024) {
  318. heads = 255;
  319. sectors = 63;
  320. cylinders = total_capacity / (heads * sectors);
  321. }
  322. geom[0] = heads;
  323. geom[1] = sectors;
  324. geom[2] = cylinders;
  325. return 0;
  326. }
  327. static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
  328. {
  329. struct MessageUnit_A __iomem *reg = acb->pmuA;
  330. int i;
  331. for (i = 0; i < 2000; i++) {
  332. if (readl(&reg->outbound_intstatus) &
  333. ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
  334. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
  335. &reg->outbound_intstatus);
  336. return true;
  337. }
  338. msleep(10);
  339. } /* max 20 seconds */
  340. return false;
  341. }
  342. static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
  343. {
  344. struct MessageUnit_B *reg = acb->pmuB;
  345. int i;
  346. for (i = 0; i < 2000; i++) {
  347. if (readl(reg->iop2drv_doorbell)
  348. & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
  349. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
  350. reg->iop2drv_doorbell);
  351. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
  352. reg->drv2iop_doorbell);
  353. return true;
  354. }
  355. msleep(10);
  356. } /* max 20 seconds */
  357. return false;
  358. }
  359. static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
  360. {
  361. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  362. int i;
  363. for (i = 0; i < 2000; i++) {
  364. if (readl(&phbcmu->outbound_doorbell)
  365. & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  366. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
  367. &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
  368. return true;
  369. }
  370. msleep(10);
  371. } /* max 20 seconds */
  372. return false;
  373. }
  374. static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
  375. {
  376. struct MessageUnit_D *reg = pACB->pmuD;
  377. int i;
  378. for (i = 0; i < 2000; i++) {
  379. if (readl(reg->outbound_doorbell)
  380. & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  381. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  382. reg->outbound_doorbell);
  383. return true;
  384. }
  385. msleep(10);
  386. } /* max 20 seconds */
  387. return false;
  388. }
  389. static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
  390. {
  391. struct MessageUnit_A __iomem *reg = acb->pmuA;
  392. int retry_count = 30;
  393. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  394. do {
  395. if (arcmsr_hbaA_wait_msgint_ready(acb))
  396. break;
  397. else {
  398. retry_count--;
  399. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  400. timeout, retry count down = %d \n", acb->host->host_no, retry_count);
  401. }
  402. } while (retry_count != 0);
  403. }
  404. static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
  405. {
  406. struct MessageUnit_B *reg = acb->pmuB;
  407. int retry_count = 30;
  408. writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
  409. do {
  410. if (arcmsr_hbaB_wait_msgint_ready(acb))
  411. break;
  412. else {
  413. retry_count--;
  414. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  415. timeout,retry count down = %d \n", acb->host->host_no, retry_count);
  416. }
  417. } while (retry_count != 0);
  418. }
  419. static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
  420. {
  421. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  422. int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
  423. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
  424. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  425. do {
  426. if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
  427. break;
  428. } else {
  429. retry_count--;
  430. printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
  431. timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
  432. }
  433. } while (retry_count != 0);
  434. return;
  435. }
  436. static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
  437. {
  438. int retry_count = 15;
  439. struct MessageUnit_D *reg = pACB->pmuD;
  440. writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
  441. do {
  442. if (arcmsr_hbaD_wait_msgint_ready(pACB))
  443. break;
  444. retry_count--;
  445. pr_notice("arcmsr%d: wait 'flush adapter "
  446. "cache' timeout, retry count down = %d\n",
  447. pACB->host->host_no, retry_count);
  448. } while (retry_count != 0);
  449. }
  450. static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
  451. {
  452. switch (acb->adapter_type) {
  453. case ACB_ADAPTER_TYPE_A: {
  454. arcmsr_hbaA_flush_cache(acb);
  455. }
  456. break;
  457. case ACB_ADAPTER_TYPE_B: {
  458. arcmsr_hbaB_flush_cache(acb);
  459. }
  460. break;
  461. case ACB_ADAPTER_TYPE_C: {
  462. arcmsr_hbaC_flush_cache(acb);
  463. }
  464. break;
  465. case ACB_ADAPTER_TYPE_D:
  466. arcmsr_hbaD_flush_cache(acb);
  467. break;
  468. }
  469. }
  470. static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
  471. {
  472. struct pci_dev *pdev = acb->pdev;
  473. void *dma_coherent;
  474. dma_addr_t dma_coherent_handle;
  475. struct CommandControlBlock *ccb_tmp;
  476. int i = 0, j = 0;
  477. dma_addr_t cdb_phyaddr;
  478. unsigned long roundup_ccbsize;
  479. unsigned long max_xfer_len;
  480. unsigned long max_sg_entrys;
  481. uint32_t firm_config_version;
  482. for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
  483. for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
  484. acb->devstate[i][j] = ARECA_RAID_GONE;
  485. max_xfer_len = ARCMSR_MAX_XFER_LEN;
  486. max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
  487. firm_config_version = acb->firm_cfg_version;
  488. if((firm_config_version & 0xFF) >= 3){
  489. max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
  490. max_sg_entrys = (max_xfer_len/4096);
  491. }
  492. acb->host->max_sectors = max_xfer_len/512;
  493. acb->host->sg_tablesize = max_sg_entrys;
  494. roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
  495. acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
  496. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
  497. if(!dma_coherent){
  498. printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
  499. return -ENOMEM;
  500. }
  501. acb->dma_coherent = dma_coherent;
  502. acb->dma_coherent_handle = dma_coherent_handle;
  503. memset(dma_coherent, 0, acb->uncache_size);
  504. ccb_tmp = dma_coherent;
  505. acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
  506. for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
  507. cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
  508. switch (acb->adapter_type) {
  509. case ACB_ADAPTER_TYPE_A:
  510. case ACB_ADAPTER_TYPE_B:
  511. ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
  512. break;
  513. case ACB_ADAPTER_TYPE_C:
  514. case ACB_ADAPTER_TYPE_D:
  515. ccb_tmp->cdb_phyaddr = cdb_phyaddr;
  516. break;
  517. }
  518. acb->pccb_pool[i] = ccb_tmp;
  519. ccb_tmp->acb = acb;
  520. INIT_LIST_HEAD(&ccb_tmp->list);
  521. list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
  522. ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
  523. dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
  524. }
  525. return 0;
  526. }
  527. static void arcmsr_message_isr_bh_fn(struct work_struct *work)
  528. {
  529. struct AdapterControlBlock *acb = container_of(work,
  530. struct AdapterControlBlock, arcmsr_do_message_isr_bh);
  531. char *acb_dev_map = (char *)acb->device_map;
  532. uint32_t __iomem *signature = NULL;
  533. char __iomem *devicemap = NULL;
  534. int target, lun;
  535. struct scsi_device *psdev;
  536. char diff, temp;
  537. switch (acb->adapter_type) {
  538. case ACB_ADAPTER_TYPE_A: {
  539. struct MessageUnit_A __iomem *reg = acb->pmuA;
  540. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  541. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  542. break;
  543. }
  544. case ACB_ADAPTER_TYPE_B: {
  545. struct MessageUnit_B *reg = acb->pmuB;
  546. signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
  547. devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
  548. break;
  549. }
  550. case ACB_ADAPTER_TYPE_C: {
  551. struct MessageUnit_C __iomem *reg = acb->pmuC;
  552. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  553. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  554. break;
  555. }
  556. case ACB_ADAPTER_TYPE_D: {
  557. struct MessageUnit_D *reg = acb->pmuD;
  558. signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
  559. devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  560. break;
  561. }
  562. }
  563. atomic_inc(&acb->rq_map_token);
  564. if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
  565. return;
  566. for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
  567. target++) {
  568. temp = readb(devicemap);
  569. diff = (*acb_dev_map) ^ temp;
  570. if (diff != 0) {
  571. *acb_dev_map = temp;
  572. for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
  573. lun++) {
  574. if ((diff & 0x01) == 1 &&
  575. (temp & 0x01) == 1) {
  576. scsi_add_device(acb->host,
  577. 0, target, lun);
  578. } else if ((diff & 0x01) == 1
  579. && (temp & 0x01) == 0) {
  580. psdev = scsi_device_lookup(acb->host,
  581. 0, target, lun);
  582. if (psdev != NULL) {
  583. scsi_remove_device(psdev);
  584. scsi_device_put(psdev);
  585. }
  586. }
  587. temp >>= 1;
  588. diff >>= 1;
  589. }
  590. }
  591. devicemap++;
  592. acb_dev_map++;
  593. }
  594. }
  595. static int
  596. arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
  597. {
  598. int i, j, r;
  599. struct msix_entry entries[ARCMST_NUM_MSIX_VECTORS];
  600. for (i = 0; i < ARCMST_NUM_MSIX_VECTORS; i++)
  601. entries[i].entry = i;
  602. r = pci_enable_msix_range(pdev, entries, 1, ARCMST_NUM_MSIX_VECTORS);
  603. if (r < 0)
  604. goto msi_int;
  605. acb->msix_vector_count = r;
  606. for (i = 0; i < r; i++) {
  607. if (request_irq(entries[i].vector,
  608. arcmsr_do_interrupt, 0, "arcmsr", acb)) {
  609. pr_warn("arcmsr%d: request_irq =%d failed!\n",
  610. acb->host->host_no, entries[i].vector);
  611. for (j = 0 ; j < i ; j++)
  612. free_irq(entries[j].vector, acb);
  613. pci_disable_msix(pdev);
  614. goto msi_int;
  615. }
  616. acb->entries[i] = entries[i];
  617. }
  618. acb->acb_flags |= ACB_F_MSIX_ENABLED;
  619. pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
  620. return SUCCESS;
  621. msi_int:
  622. if (pci_enable_msi_exact(pdev, 1) < 0)
  623. goto legacy_int;
  624. if (request_irq(pdev->irq, arcmsr_do_interrupt,
  625. IRQF_SHARED, "arcmsr", acb)) {
  626. pr_warn("arcmsr%d: request_irq =%d failed!\n",
  627. acb->host->host_no, pdev->irq);
  628. pci_disable_msi(pdev);
  629. goto legacy_int;
  630. }
  631. acb->acb_flags |= ACB_F_MSI_ENABLED;
  632. pr_info("arcmsr%d: msi enabled\n", acb->host->host_no);
  633. return SUCCESS;
  634. legacy_int:
  635. if (request_irq(pdev->irq, arcmsr_do_interrupt,
  636. IRQF_SHARED, "arcmsr", acb)) {
  637. pr_warn("arcmsr%d: request_irq = %d failed!\n",
  638. acb->host->host_no, pdev->irq);
  639. return FAILED;
  640. }
  641. return SUCCESS;
  642. }
  643. static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  644. {
  645. struct Scsi_Host *host;
  646. struct AdapterControlBlock *acb;
  647. uint8_t bus,dev_fun;
  648. int error;
  649. error = pci_enable_device(pdev);
  650. if(error){
  651. return -ENODEV;
  652. }
  653. host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
  654. if(!host){
  655. goto pci_disable_dev;
  656. }
  657. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  658. if(error){
  659. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  660. if(error){
  661. printk(KERN_WARNING
  662. "scsi%d: No suitable DMA mask available\n",
  663. host->host_no);
  664. goto scsi_host_release;
  665. }
  666. }
  667. init_waitqueue_head(&wait_q);
  668. bus = pdev->bus->number;
  669. dev_fun = pdev->devfn;
  670. acb = (struct AdapterControlBlock *) host->hostdata;
  671. memset(acb,0,sizeof(struct AdapterControlBlock));
  672. acb->pdev = pdev;
  673. acb->host = host;
  674. host->max_lun = ARCMSR_MAX_TARGETLUN;
  675. host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
  676. host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
  677. host->can_queue = ARCMSR_MAX_OUTSTANDING_CMD;
  678. host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
  679. host->this_id = ARCMSR_SCSI_INITIATOR_ID;
  680. host->unique_id = (bus << 8) | dev_fun;
  681. pci_set_drvdata(pdev, host);
  682. pci_set_master(pdev);
  683. error = pci_request_regions(pdev, "arcmsr");
  684. if(error){
  685. goto scsi_host_release;
  686. }
  687. spin_lock_init(&acb->eh_lock);
  688. spin_lock_init(&acb->ccblist_lock);
  689. spin_lock_init(&acb->postq_lock);
  690. spin_lock_init(&acb->doneq_lock);
  691. spin_lock_init(&acb->rqbuffer_lock);
  692. spin_lock_init(&acb->wqbuffer_lock);
  693. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  694. ACB_F_MESSAGE_RQBUFFER_CLEARED |
  695. ACB_F_MESSAGE_WQBUFFER_READED);
  696. acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
  697. INIT_LIST_HEAD(&acb->ccb_free_list);
  698. acb->adapter_type = id->driver_data;
  699. error = arcmsr_remap_pciregion(acb);
  700. if(!error){
  701. goto pci_release_regs;
  702. }
  703. error = arcmsr_get_firmware_spec(acb);
  704. if(!error){
  705. goto unmap_pci_region;
  706. }
  707. error = arcmsr_alloc_ccb_pool(acb);
  708. if(error){
  709. goto free_hbb_mu;
  710. }
  711. error = scsi_add_host(host, &pdev->dev);
  712. if(error){
  713. goto free_ccb_pool;
  714. }
  715. if (arcmsr_request_irq(pdev, acb) == FAILED)
  716. goto scsi_host_remove;
  717. arcmsr_iop_init(acb);
  718. INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  719. atomic_set(&acb->rq_map_token, 16);
  720. atomic_set(&acb->ante_token_value, 16);
  721. acb->fw_flag = FW_NORMAL;
  722. init_timer(&acb->eternal_timer);
  723. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  724. acb->eternal_timer.data = (unsigned long) acb;
  725. acb->eternal_timer.function = &arcmsr_request_device_map;
  726. add_timer(&acb->eternal_timer);
  727. if(arcmsr_alloc_sysfs_attr(acb))
  728. goto out_free_sysfs;
  729. scsi_scan_host(host);
  730. return 0;
  731. out_free_sysfs:
  732. del_timer_sync(&acb->eternal_timer);
  733. flush_work(&acb->arcmsr_do_message_isr_bh);
  734. arcmsr_stop_adapter_bgrb(acb);
  735. arcmsr_flush_adapter_cache(acb);
  736. arcmsr_free_irq(pdev, acb);
  737. scsi_host_remove:
  738. scsi_remove_host(host);
  739. free_ccb_pool:
  740. arcmsr_free_ccb_pool(acb);
  741. free_hbb_mu:
  742. arcmsr_free_mu(acb);
  743. unmap_pci_region:
  744. arcmsr_unmap_pciregion(acb);
  745. pci_release_regs:
  746. pci_release_regions(pdev);
  747. scsi_host_release:
  748. scsi_host_put(host);
  749. pci_disable_dev:
  750. pci_disable_device(pdev);
  751. return -ENODEV;
  752. }
  753. static void arcmsr_free_irq(struct pci_dev *pdev,
  754. struct AdapterControlBlock *acb)
  755. {
  756. int i;
  757. if (acb->acb_flags & ACB_F_MSI_ENABLED) {
  758. free_irq(pdev->irq, acb);
  759. pci_disable_msi(pdev);
  760. } else if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
  761. for (i = 0; i < acb->msix_vector_count; i++)
  762. free_irq(acb->entries[i].vector, acb);
  763. pci_disable_msix(pdev);
  764. } else
  765. free_irq(pdev->irq, acb);
  766. }
  767. static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
  768. {
  769. uint32_t intmask_org;
  770. struct Scsi_Host *host = pci_get_drvdata(pdev);
  771. struct AdapterControlBlock *acb =
  772. (struct AdapterControlBlock *)host->hostdata;
  773. intmask_org = arcmsr_disable_outbound_ints(acb);
  774. arcmsr_free_irq(pdev, acb);
  775. del_timer_sync(&acb->eternal_timer);
  776. flush_work(&acb->arcmsr_do_message_isr_bh);
  777. arcmsr_stop_adapter_bgrb(acb);
  778. arcmsr_flush_adapter_cache(acb);
  779. pci_set_drvdata(pdev, host);
  780. pci_save_state(pdev);
  781. pci_disable_device(pdev);
  782. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  783. return 0;
  784. }
  785. static int arcmsr_resume(struct pci_dev *pdev)
  786. {
  787. int error;
  788. struct Scsi_Host *host = pci_get_drvdata(pdev);
  789. struct AdapterControlBlock *acb =
  790. (struct AdapterControlBlock *)host->hostdata;
  791. pci_set_power_state(pdev, PCI_D0);
  792. pci_enable_wake(pdev, PCI_D0, 0);
  793. pci_restore_state(pdev);
  794. if (pci_enable_device(pdev)) {
  795. pr_warn("%s: pci_enable_device error\n", __func__);
  796. return -ENODEV;
  797. }
  798. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  799. if (error) {
  800. error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  801. if (error) {
  802. pr_warn("scsi%d: No suitable DMA mask available\n",
  803. host->host_no);
  804. goto controller_unregister;
  805. }
  806. }
  807. pci_set_master(pdev);
  808. if (arcmsr_request_irq(pdev, acb) == FAILED)
  809. goto controller_stop;
  810. arcmsr_iop_init(acb);
  811. INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
  812. atomic_set(&acb->rq_map_token, 16);
  813. atomic_set(&acb->ante_token_value, 16);
  814. acb->fw_flag = FW_NORMAL;
  815. init_timer(&acb->eternal_timer);
  816. acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
  817. acb->eternal_timer.data = (unsigned long) acb;
  818. acb->eternal_timer.function = &arcmsr_request_device_map;
  819. add_timer(&acb->eternal_timer);
  820. return 0;
  821. controller_stop:
  822. arcmsr_stop_adapter_bgrb(acb);
  823. arcmsr_flush_adapter_cache(acb);
  824. controller_unregister:
  825. scsi_remove_host(host);
  826. arcmsr_free_ccb_pool(acb);
  827. arcmsr_unmap_pciregion(acb);
  828. pci_release_regions(pdev);
  829. scsi_host_put(host);
  830. pci_disable_device(pdev);
  831. return -ENODEV;
  832. }
  833. static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
  834. {
  835. struct MessageUnit_A __iomem *reg = acb->pmuA;
  836. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  837. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  838. printk(KERN_NOTICE
  839. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  840. , acb->host->host_no);
  841. return false;
  842. }
  843. return true;
  844. }
  845. static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
  846. {
  847. struct MessageUnit_B *reg = acb->pmuB;
  848. writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
  849. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  850. printk(KERN_NOTICE
  851. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  852. , acb->host->host_no);
  853. return false;
  854. }
  855. return true;
  856. }
  857. static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
  858. {
  859. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  860. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
  861. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  862. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  863. printk(KERN_NOTICE
  864. "arcmsr%d: wait 'abort all outstanding command' timeout\n"
  865. , pACB->host->host_no);
  866. return false;
  867. }
  868. return true;
  869. }
  870. static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
  871. {
  872. struct MessageUnit_D *reg = pACB->pmuD;
  873. writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
  874. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  875. pr_notice("arcmsr%d: wait 'abort all outstanding "
  876. "command' timeout\n", pACB->host->host_no);
  877. return false;
  878. }
  879. return true;
  880. }
  881. static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
  882. {
  883. uint8_t rtnval = 0;
  884. switch (acb->adapter_type) {
  885. case ACB_ADAPTER_TYPE_A: {
  886. rtnval = arcmsr_hbaA_abort_allcmd(acb);
  887. }
  888. break;
  889. case ACB_ADAPTER_TYPE_B: {
  890. rtnval = arcmsr_hbaB_abort_allcmd(acb);
  891. }
  892. break;
  893. case ACB_ADAPTER_TYPE_C: {
  894. rtnval = arcmsr_hbaC_abort_allcmd(acb);
  895. }
  896. break;
  897. case ACB_ADAPTER_TYPE_D:
  898. rtnval = arcmsr_hbaD_abort_allcmd(acb);
  899. break;
  900. }
  901. return rtnval;
  902. }
  903. static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
  904. {
  905. struct scsi_cmnd *pcmd = ccb->pcmd;
  906. scsi_dma_unmap(pcmd);
  907. }
  908. static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
  909. {
  910. struct AdapterControlBlock *acb = ccb->acb;
  911. struct scsi_cmnd *pcmd = ccb->pcmd;
  912. unsigned long flags;
  913. atomic_dec(&acb->ccboutstandingcount);
  914. arcmsr_pci_unmap_dma(ccb);
  915. ccb->startdone = ARCMSR_CCB_DONE;
  916. spin_lock_irqsave(&acb->ccblist_lock, flags);
  917. list_add_tail(&ccb->list, &acb->ccb_free_list);
  918. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  919. pcmd->scsi_done(pcmd);
  920. }
  921. static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
  922. {
  923. struct scsi_cmnd *pcmd = ccb->pcmd;
  924. struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
  925. pcmd->result = DID_OK << 16;
  926. if (sensebuffer) {
  927. int sense_data_length =
  928. sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
  929. ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
  930. memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
  931. memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
  932. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  933. sensebuffer->Valid = 1;
  934. }
  935. }
  936. static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
  937. {
  938. u32 orig_mask = 0;
  939. switch (acb->adapter_type) {
  940. case ACB_ADAPTER_TYPE_A : {
  941. struct MessageUnit_A __iomem *reg = acb->pmuA;
  942. orig_mask = readl(&reg->outbound_intmask);
  943. writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
  944. &reg->outbound_intmask);
  945. }
  946. break;
  947. case ACB_ADAPTER_TYPE_B : {
  948. struct MessageUnit_B *reg = acb->pmuB;
  949. orig_mask = readl(reg->iop2drv_doorbell_mask);
  950. writel(0, reg->iop2drv_doorbell_mask);
  951. }
  952. break;
  953. case ACB_ADAPTER_TYPE_C:{
  954. struct MessageUnit_C __iomem *reg = acb->pmuC;
  955. /* disable all outbound interrupt */
  956. orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
  957. writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  958. }
  959. break;
  960. case ACB_ADAPTER_TYPE_D: {
  961. struct MessageUnit_D *reg = acb->pmuD;
  962. /* disable all outbound interrupt */
  963. writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
  964. }
  965. break;
  966. }
  967. return orig_mask;
  968. }
  969. static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
  970. struct CommandControlBlock *ccb, bool error)
  971. {
  972. uint8_t id, lun;
  973. id = ccb->pcmd->device->id;
  974. lun = ccb->pcmd->device->lun;
  975. if (!error) {
  976. if (acb->devstate[id][lun] == ARECA_RAID_GONE)
  977. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  978. ccb->pcmd->result = DID_OK << 16;
  979. arcmsr_ccb_complete(ccb);
  980. }else{
  981. switch (ccb->arcmsr_cdb.DeviceStatus) {
  982. case ARCMSR_DEV_SELECT_TIMEOUT: {
  983. acb->devstate[id][lun] = ARECA_RAID_GONE;
  984. ccb->pcmd->result = DID_NO_CONNECT << 16;
  985. arcmsr_ccb_complete(ccb);
  986. }
  987. break;
  988. case ARCMSR_DEV_ABORTED:
  989. case ARCMSR_DEV_INIT_FAIL: {
  990. acb->devstate[id][lun] = ARECA_RAID_GONE;
  991. ccb->pcmd->result = DID_BAD_TARGET << 16;
  992. arcmsr_ccb_complete(ccb);
  993. }
  994. break;
  995. case ARCMSR_DEV_CHECK_CONDITION: {
  996. acb->devstate[id][lun] = ARECA_RAID_GOOD;
  997. arcmsr_report_sense_info(ccb);
  998. arcmsr_ccb_complete(ccb);
  999. }
  1000. break;
  1001. default:
  1002. printk(KERN_NOTICE
  1003. "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
  1004. but got unknown DeviceStatus = 0x%x \n"
  1005. , acb->host->host_no
  1006. , id
  1007. , lun
  1008. , ccb->arcmsr_cdb.DeviceStatus);
  1009. acb->devstate[id][lun] = ARECA_RAID_GONE;
  1010. ccb->pcmd->result = DID_NO_CONNECT << 16;
  1011. arcmsr_ccb_complete(ccb);
  1012. break;
  1013. }
  1014. }
  1015. }
  1016. static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
  1017. {
  1018. int id, lun;
  1019. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  1020. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  1021. struct scsi_cmnd *abortcmd = pCCB->pcmd;
  1022. if (abortcmd) {
  1023. id = abortcmd->device->id;
  1024. lun = abortcmd->device->lun;
  1025. abortcmd->result |= DID_ABORT << 16;
  1026. arcmsr_ccb_complete(pCCB);
  1027. printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
  1028. acb->host->host_no, pCCB);
  1029. }
  1030. return;
  1031. }
  1032. printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
  1033. done acb = '0x%p'"
  1034. "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
  1035. " ccboutstandingcount = %d \n"
  1036. , acb->host->host_no
  1037. , acb
  1038. , pCCB
  1039. , pCCB->acb
  1040. , pCCB->startdone
  1041. , atomic_read(&acb->ccboutstandingcount));
  1042. return;
  1043. }
  1044. arcmsr_report_ccb_state(acb, pCCB, error);
  1045. }
  1046. static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
  1047. {
  1048. int i = 0;
  1049. uint32_t flag_ccb, ccb_cdb_phy;
  1050. struct ARCMSR_CDB *pARCMSR_CDB;
  1051. bool error;
  1052. struct CommandControlBlock *pCCB;
  1053. switch (acb->adapter_type) {
  1054. case ACB_ADAPTER_TYPE_A: {
  1055. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1056. uint32_t outbound_intstatus;
  1057. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1058. acb->outbound_int_enable;
  1059. /*clear and abort all outbound posted Q*/
  1060. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  1061. while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
  1062. && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  1063. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1064. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1065. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1066. arcmsr_drain_donequeue(acb, pCCB, error);
  1067. }
  1068. }
  1069. break;
  1070. case ACB_ADAPTER_TYPE_B: {
  1071. struct MessageUnit_B *reg = acb->pmuB;
  1072. /*clear all outbound posted Q*/
  1073. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
  1074. for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
  1075. flag_ccb = reg->done_qbuffer[i];
  1076. if (flag_ccb != 0) {
  1077. reg->done_qbuffer[i] = 0;
  1078. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1079. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1080. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1081. arcmsr_drain_donequeue(acb, pCCB, error);
  1082. }
  1083. reg->post_qbuffer[i] = 0;
  1084. }
  1085. reg->doneq_index = 0;
  1086. reg->postq_index = 0;
  1087. }
  1088. break;
  1089. case ACB_ADAPTER_TYPE_C: {
  1090. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1091. while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
  1092. /*need to do*/
  1093. flag_ccb = readl(&reg->outbound_queueport_low);
  1094. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  1095. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  1096. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1097. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  1098. arcmsr_drain_donequeue(acb, pCCB, error);
  1099. }
  1100. }
  1101. break;
  1102. case ACB_ADAPTER_TYPE_D: {
  1103. struct MessageUnit_D *pmu = acb->pmuD;
  1104. uint32_t outbound_write_pointer;
  1105. uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
  1106. unsigned long flags;
  1107. residual = atomic_read(&acb->ccboutstandingcount);
  1108. for (i = 0; i < residual; i++) {
  1109. spin_lock_irqsave(&acb->doneq_lock, flags);
  1110. outbound_write_pointer =
  1111. pmu->done_qbuffer[0].addressLow + 1;
  1112. doneq_index = pmu->doneq_index;
  1113. if ((doneq_index & 0xFFF) !=
  1114. (outbound_write_pointer & 0xFFF)) {
  1115. toggle = doneq_index & 0x4000;
  1116. index_stripped = (doneq_index & 0xFFF) + 1;
  1117. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  1118. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  1119. ((toggle ^ 0x4000) + 1);
  1120. doneq_index = pmu->doneq_index;
  1121. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1122. addressLow = pmu->done_qbuffer[doneq_index &
  1123. 0xFFF].addressLow;
  1124. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  1125. pARCMSR_CDB = (struct ARCMSR_CDB *)
  1126. (acb->vir2phy_offset + ccb_cdb_phy);
  1127. pCCB = container_of(pARCMSR_CDB,
  1128. struct CommandControlBlock, arcmsr_cdb);
  1129. error = (addressLow &
  1130. ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
  1131. true : false;
  1132. arcmsr_drain_donequeue(acb, pCCB, error);
  1133. writel(doneq_index,
  1134. pmu->outboundlist_read_pointer);
  1135. } else {
  1136. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1137. mdelay(10);
  1138. }
  1139. }
  1140. pmu->postq_index = 0;
  1141. pmu->doneq_index = 0x40FF;
  1142. }
  1143. break;
  1144. }
  1145. }
  1146. static void arcmsr_remove(struct pci_dev *pdev)
  1147. {
  1148. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1149. struct AdapterControlBlock *acb =
  1150. (struct AdapterControlBlock *) host->hostdata;
  1151. int poll_count = 0;
  1152. arcmsr_free_sysfs_attr(acb);
  1153. scsi_remove_host(host);
  1154. flush_work(&acb->arcmsr_do_message_isr_bh);
  1155. del_timer_sync(&acb->eternal_timer);
  1156. arcmsr_disable_outbound_ints(acb);
  1157. arcmsr_stop_adapter_bgrb(acb);
  1158. arcmsr_flush_adapter_cache(acb);
  1159. acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
  1160. acb->acb_flags &= ~ACB_F_IOP_INITED;
  1161. for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
  1162. if (!atomic_read(&acb->ccboutstandingcount))
  1163. break;
  1164. arcmsr_interrupt(acb);/* FIXME: need spinlock */
  1165. msleep(25);
  1166. }
  1167. if (atomic_read(&acb->ccboutstandingcount)) {
  1168. int i;
  1169. arcmsr_abort_allcmd(acb);
  1170. arcmsr_done4abort_postqueue(acb);
  1171. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  1172. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  1173. if (ccb->startdone == ARCMSR_CCB_START) {
  1174. ccb->startdone = ARCMSR_CCB_ABORTED;
  1175. ccb->pcmd->result = DID_ABORT << 16;
  1176. arcmsr_ccb_complete(ccb);
  1177. }
  1178. }
  1179. }
  1180. arcmsr_free_irq(pdev, acb);
  1181. arcmsr_free_ccb_pool(acb);
  1182. arcmsr_free_mu(acb);
  1183. arcmsr_unmap_pciregion(acb);
  1184. pci_release_regions(pdev);
  1185. scsi_host_put(host);
  1186. pci_disable_device(pdev);
  1187. }
  1188. static void arcmsr_shutdown(struct pci_dev *pdev)
  1189. {
  1190. struct Scsi_Host *host = pci_get_drvdata(pdev);
  1191. struct AdapterControlBlock *acb =
  1192. (struct AdapterControlBlock *)host->hostdata;
  1193. del_timer_sync(&acb->eternal_timer);
  1194. arcmsr_disable_outbound_ints(acb);
  1195. arcmsr_free_irq(pdev, acb);
  1196. flush_work(&acb->arcmsr_do_message_isr_bh);
  1197. arcmsr_stop_adapter_bgrb(acb);
  1198. arcmsr_flush_adapter_cache(acb);
  1199. }
  1200. static int arcmsr_module_init(void)
  1201. {
  1202. int error = 0;
  1203. error = pci_register_driver(&arcmsr_pci_driver);
  1204. return error;
  1205. }
  1206. static void arcmsr_module_exit(void)
  1207. {
  1208. pci_unregister_driver(&arcmsr_pci_driver);
  1209. }
  1210. module_init(arcmsr_module_init);
  1211. module_exit(arcmsr_module_exit);
  1212. static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
  1213. u32 intmask_org)
  1214. {
  1215. u32 mask;
  1216. switch (acb->adapter_type) {
  1217. case ACB_ADAPTER_TYPE_A: {
  1218. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1219. mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
  1220. ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
  1221. ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
  1222. writel(mask, &reg->outbound_intmask);
  1223. acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
  1224. }
  1225. break;
  1226. case ACB_ADAPTER_TYPE_B: {
  1227. struct MessageUnit_B *reg = acb->pmuB;
  1228. mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
  1229. ARCMSR_IOP2DRV_DATA_READ_OK |
  1230. ARCMSR_IOP2DRV_CDB_DONE |
  1231. ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
  1232. writel(mask, reg->iop2drv_doorbell_mask);
  1233. acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
  1234. }
  1235. break;
  1236. case ACB_ADAPTER_TYPE_C: {
  1237. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1238. mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
  1239. writel(intmask_org & mask, &reg->host_int_mask);
  1240. acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
  1241. }
  1242. break;
  1243. case ACB_ADAPTER_TYPE_D: {
  1244. struct MessageUnit_D *reg = acb->pmuD;
  1245. mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
  1246. writel(intmask_org | mask, reg->pcief0_int_enable);
  1247. break;
  1248. }
  1249. }
  1250. }
  1251. static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
  1252. struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
  1253. {
  1254. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1255. int8_t *psge = (int8_t *)&arcmsr_cdb->u;
  1256. __le32 address_lo, address_hi;
  1257. int arccdbsize = 0x30;
  1258. __le32 length = 0;
  1259. int i;
  1260. struct scatterlist *sg;
  1261. int nseg;
  1262. ccb->pcmd = pcmd;
  1263. memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
  1264. arcmsr_cdb->TargetID = pcmd->device->id;
  1265. arcmsr_cdb->LUN = pcmd->device->lun;
  1266. arcmsr_cdb->Function = 1;
  1267. arcmsr_cdb->msgContext = 0;
  1268. memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
  1269. nseg = scsi_dma_map(pcmd);
  1270. if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
  1271. return FAILED;
  1272. scsi_for_each_sg(pcmd, sg, nseg, i) {
  1273. /* Get the physical address of the current data pointer */
  1274. length = cpu_to_le32(sg_dma_len(sg));
  1275. address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
  1276. address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
  1277. if (address_hi == 0) {
  1278. struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
  1279. pdma_sg->address = address_lo;
  1280. pdma_sg->length = length;
  1281. psge += sizeof (struct SG32ENTRY);
  1282. arccdbsize += sizeof (struct SG32ENTRY);
  1283. } else {
  1284. struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
  1285. pdma_sg->addresshigh = address_hi;
  1286. pdma_sg->address = address_lo;
  1287. pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
  1288. psge += sizeof (struct SG64ENTRY);
  1289. arccdbsize += sizeof (struct SG64ENTRY);
  1290. }
  1291. }
  1292. arcmsr_cdb->sgcount = (uint8_t)nseg;
  1293. arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
  1294. arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
  1295. if ( arccdbsize > 256)
  1296. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
  1297. if (pcmd->sc_data_direction == DMA_TO_DEVICE)
  1298. arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
  1299. ccb->arc_cdb_size = arccdbsize;
  1300. return SUCCESS;
  1301. }
  1302. static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
  1303. {
  1304. uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
  1305. struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
  1306. atomic_inc(&acb->ccboutstandingcount);
  1307. ccb->startdone = ARCMSR_CCB_START;
  1308. switch (acb->adapter_type) {
  1309. case ACB_ADAPTER_TYPE_A: {
  1310. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1311. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
  1312. writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
  1313. &reg->inbound_queueport);
  1314. else
  1315. writel(cdb_phyaddr, &reg->inbound_queueport);
  1316. break;
  1317. }
  1318. case ACB_ADAPTER_TYPE_B: {
  1319. struct MessageUnit_B *reg = acb->pmuB;
  1320. uint32_t ending_index, index = reg->postq_index;
  1321. ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
  1322. reg->post_qbuffer[ending_index] = 0;
  1323. if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
  1324. reg->post_qbuffer[index] =
  1325. cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
  1326. } else {
  1327. reg->post_qbuffer[index] = cdb_phyaddr;
  1328. }
  1329. index++;
  1330. index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
  1331. reg->postq_index = index;
  1332. writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
  1333. }
  1334. break;
  1335. case ACB_ADAPTER_TYPE_C: {
  1336. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1337. uint32_t ccb_post_stamp, arc_cdb_size;
  1338. arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
  1339. ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
  1340. if (acb->cdb_phyaddr_hi32) {
  1341. writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
  1342. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1343. } else {
  1344. writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
  1345. }
  1346. }
  1347. break;
  1348. case ACB_ADAPTER_TYPE_D: {
  1349. struct MessageUnit_D *pmu = acb->pmuD;
  1350. u16 index_stripped;
  1351. u16 postq_index, toggle;
  1352. unsigned long flags;
  1353. struct InBound_SRB *pinbound_srb;
  1354. spin_lock_irqsave(&acb->postq_lock, flags);
  1355. postq_index = pmu->postq_index;
  1356. pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
  1357. pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
  1358. pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
  1359. pinbound_srb->length = ccb->arc_cdb_size >> 2;
  1360. arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
  1361. toggle = postq_index & 0x4000;
  1362. index_stripped = postq_index + 1;
  1363. index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
  1364. pmu->postq_index = index_stripped ? (index_stripped | toggle) :
  1365. (toggle ^ 0x4000);
  1366. writel(postq_index, pmu->inboundlist_write_pointer);
  1367. spin_unlock_irqrestore(&acb->postq_lock, flags);
  1368. break;
  1369. }
  1370. }
  1371. }
  1372. static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
  1373. {
  1374. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1375. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1376. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1377. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  1378. printk(KERN_NOTICE
  1379. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1380. , acb->host->host_no);
  1381. }
  1382. }
  1383. static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
  1384. {
  1385. struct MessageUnit_B *reg = acb->pmuB;
  1386. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1387. writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
  1388. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  1389. printk(KERN_NOTICE
  1390. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1391. , acb->host->host_no);
  1392. }
  1393. }
  1394. static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
  1395. {
  1396. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1397. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1398. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
  1399. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  1400. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  1401. printk(KERN_NOTICE
  1402. "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
  1403. , pACB->host->host_no);
  1404. }
  1405. return;
  1406. }
  1407. static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
  1408. {
  1409. struct MessageUnit_D *reg = pACB->pmuD;
  1410. pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
  1411. writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
  1412. if (!arcmsr_hbaD_wait_msgint_ready(pACB))
  1413. pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
  1414. "timeout\n", pACB->host->host_no);
  1415. }
  1416. static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
  1417. {
  1418. switch (acb->adapter_type) {
  1419. case ACB_ADAPTER_TYPE_A: {
  1420. arcmsr_hbaA_stop_bgrb(acb);
  1421. }
  1422. break;
  1423. case ACB_ADAPTER_TYPE_B: {
  1424. arcmsr_hbaB_stop_bgrb(acb);
  1425. }
  1426. break;
  1427. case ACB_ADAPTER_TYPE_C: {
  1428. arcmsr_hbaC_stop_bgrb(acb);
  1429. }
  1430. break;
  1431. case ACB_ADAPTER_TYPE_D:
  1432. arcmsr_hbaD_stop_bgrb(acb);
  1433. break;
  1434. }
  1435. }
  1436. static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
  1437. {
  1438. dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
  1439. }
  1440. static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
  1441. {
  1442. switch (acb->adapter_type) {
  1443. case ACB_ADAPTER_TYPE_A: {
  1444. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1445. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  1446. }
  1447. break;
  1448. case ACB_ADAPTER_TYPE_B: {
  1449. struct MessageUnit_B *reg = acb->pmuB;
  1450. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  1451. }
  1452. break;
  1453. case ACB_ADAPTER_TYPE_C: {
  1454. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1455. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  1456. }
  1457. break;
  1458. case ACB_ADAPTER_TYPE_D: {
  1459. struct MessageUnit_D *reg = acb->pmuD;
  1460. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  1461. reg->inbound_doorbell);
  1462. }
  1463. break;
  1464. }
  1465. }
  1466. static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
  1467. {
  1468. switch (acb->adapter_type) {
  1469. case ACB_ADAPTER_TYPE_A: {
  1470. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1471. /*
  1472. ** push inbound doorbell tell iop, driver data write ok
  1473. ** and wait reply on next hwinterrupt for next Qbuffer post
  1474. */
  1475. writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
  1476. }
  1477. break;
  1478. case ACB_ADAPTER_TYPE_B: {
  1479. struct MessageUnit_B *reg = acb->pmuB;
  1480. /*
  1481. ** push inbound doorbell tell iop, driver data write ok
  1482. ** and wait reply on next hwinterrupt for next Qbuffer post
  1483. */
  1484. writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
  1485. }
  1486. break;
  1487. case ACB_ADAPTER_TYPE_C: {
  1488. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1489. /*
  1490. ** push inbound doorbell tell iop, driver data write ok
  1491. ** and wait reply on next hwinterrupt for next Qbuffer post
  1492. */
  1493. writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
  1494. }
  1495. break;
  1496. case ACB_ADAPTER_TYPE_D: {
  1497. struct MessageUnit_D *reg = acb->pmuD;
  1498. writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
  1499. reg->inbound_doorbell);
  1500. }
  1501. break;
  1502. }
  1503. }
  1504. struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
  1505. {
  1506. struct QBUFFER __iomem *qbuffer = NULL;
  1507. switch (acb->adapter_type) {
  1508. case ACB_ADAPTER_TYPE_A: {
  1509. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1510. qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
  1511. }
  1512. break;
  1513. case ACB_ADAPTER_TYPE_B: {
  1514. struct MessageUnit_B *reg = acb->pmuB;
  1515. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1516. }
  1517. break;
  1518. case ACB_ADAPTER_TYPE_C: {
  1519. struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
  1520. qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
  1521. }
  1522. break;
  1523. case ACB_ADAPTER_TYPE_D: {
  1524. struct MessageUnit_D *reg = acb->pmuD;
  1525. qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
  1526. }
  1527. break;
  1528. }
  1529. return qbuffer;
  1530. }
  1531. static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
  1532. {
  1533. struct QBUFFER __iomem *pqbuffer = NULL;
  1534. switch (acb->adapter_type) {
  1535. case ACB_ADAPTER_TYPE_A: {
  1536. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1537. pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
  1538. }
  1539. break;
  1540. case ACB_ADAPTER_TYPE_B: {
  1541. struct MessageUnit_B *reg = acb->pmuB;
  1542. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1543. }
  1544. break;
  1545. case ACB_ADAPTER_TYPE_C: {
  1546. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1547. pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
  1548. }
  1549. break;
  1550. case ACB_ADAPTER_TYPE_D: {
  1551. struct MessageUnit_D *reg = acb->pmuD;
  1552. pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
  1553. }
  1554. break;
  1555. }
  1556. return pqbuffer;
  1557. }
  1558. static uint32_t
  1559. arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
  1560. struct QBUFFER __iomem *prbuffer)
  1561. {
  1562. uint8_t *pQbuffer;
  1563. uint8_t *buf1 = NULL;
  1564. uint32_t __iomem *iop_data;
  1565. uint32_t iop_len, data_len, *buf2 = NULL;
  1566. iop_data = (uint32_t __iomem *)prbuffer->data;
  1567. iop_len = readl(&prbuffer->data_len);
  1568. if (iop_len > 0) {
  1569. buf1 = kmalloc(128, GFP_ATOMIC);
  1570. buf2 = (uint32_t *)buf1;
  1571. if (buf1 == NULL)
  1572. return 0;
  1573. data_len = iop_len;
  1574. while (data_len >= 4) {
  1575. *buf2++ = readl(iop_data);
  1576. iop_data++;
  1577. data_len -= 4;
  1578. }
  1579. if (data_len)
  1580. *buf2 = readl(iop_data);
  1581. buf2 = (uint32_t *)buf1;
  1582. }
  1583. while (iop_len > 0) {
  1584. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  1585. *pQbuffer = *buf1;
  1586. acb->rqbuf_putIndex++;
  1587. /* if last, index number set it to 0 */
  1588. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  1589. buf1++;
  1590. iop_len--;
  1591. }
  1592. kfree(buf2);
  1593. /* let IOP know data has been read */
  1594. arcmsr_iop_message_read(acb);
  1595. return 1;
  1596. }
  1597. uint32_t
  1598. arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
  1599. struct QBUFFER __iomem *prbuffer) {
  1600. uint8_t *pQbuffer;
  1601. uint8_t __iomem *iop_data;
  1602. uint32_t iop_len;
  1603. if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D))
  1604. return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
  1605. iop_data = (uint8_t __iomem *)prbuffer->data;
  1606. iop_len = readl(&prbuffer->data_len);
  1607. while (iop_len > 0) {
  1608. pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
  1609. *pQbuffer = readb(iop_data);
  1610. acb->rqbuf_putIndex++;
  1611. acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  1612. iop_data++;
  1613. iop_len--;
  1614. }
  1615. arcmsr_iop_message_read(acb);
  1616. return 1;
  1617. }
  1618. static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
  1619. {
  1620. unsigned long flags;
  1621. struct QBUFFER __iomem *prbuffer;
  1622. int32_t buf_empty_len;
  1623. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  1624. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  1625. buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
  1626. (ARCMSR_MAX_QBUFFER - 1);
  1627. if (buf_empty_len >= readl(&prbuffer->data_len)) {
  1628. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  1629. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1630. } else
  1631. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  1632. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  1633. }
  1634. static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
  1635. {
  1636. uint8_t *pQbuffer;
  1637. struct QBUFFER __iomem *pwbuffer;
  1638. uint8_t *buf1 = NULL;
  1639. uint32_t __iomem *iop_data;
  1640. uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
  1641. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1642. buf1 = kmalloc(128, GFP_ATOMIC);
  1643. buf2 = (uint32_t *)buf1;
  1644. if (buf1 == NULL)
  1645. return;
  1646. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1647. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1648. iop_data = (uint32_t __iomem *)pwbuffer->data;
  1649. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1650. && (allxfer_len < 124)) {
  1651. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  1652. *buf1 = *pQbuffer;
  1653. acb->wqbuf_getIndex++;
  1654. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  1655. buf1++;
  1656. allxfer_len++;
  1657. }
  1658. data_len = allxfer_len;
  1659. buf1 = (uint8_t *)buf2;
  1660. while (data_len >= 4) {
  1661. data = *buf2++;
  1662. writel(data, iop_data);
  1663. iop_data++;
  1664. data_len -= 4;
  1665. }
  1666. if (data_len) {
  1667. data = *buf2;
  1668. writel(data, iop_data);
  1669. }
  1670. writel(allxfer_len, &pwbuffer->data_len);
  1671. kfree(buf1);
  1672. arcmsr_iop_message_wrote(acb);
  1673. }
  1674. }
  1675. void
  1676. arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
  1677. {
  1678. uint8_t *pQbuffer;
  1679. struct QBUFFER __iomem *pwbuffer;
  1680. uint8_t __iomem *iop_data;
  1681. int32_t allxfer_len = 0;
  1682. if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
  1683. arcmsr_write_ioctldata2iop_in_DWORD(acb);
  1684. return;
  1685. }
  1686. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
  1687. acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
  1688. pwbuffer = arcmsr_get_iop_wqbuffer(acb);
  1689. iop_data = (uint8_t __iomem *)pwbuffer->data;
  1690. while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1691. && (allxfer_len < 124)) {
  1692. pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
  1693. writeb(*pQbuffer, iop_data);
  1694. acb->wqbuf_getIndex++;
  1695. acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
  1696. iop_data++;
  1697. allxfer_len++;
  1698. }
  1699. writel(allxfer_len, &pwbuffer->data_len);
  1700. arcmsr_iop_message_wrote(acb);
  1701. }
  1702. }
  1703. static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
  1704. {
  1705. unsigned long flags;
  1706. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  1707. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
  1708. if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
  1709. arcmsr_write_ioctldata2iop(acb);
  1710. if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
  1711. acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
  1712. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  1713. }
  1714. static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
  1715. {
  1716. uint32_t outbound_doorbell;
  1717. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1718. outbound_doorbell = readl(&reg->outbound_doorbell);
  1719. do {
  1720. writel(outbound_doorbell, &reg->outbound_doorbell);
  1721. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
  1722. arcmsr_iop2drv_data_wrote_handle(acb);
  1723. if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
  1724. arcmsr_iop2drv_data_read_handle(acb);
  1725. outbound_doorbell = readl(&reg->outbound_doorbell);
  1726. } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
  1727. | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
  1728. }
  1729. static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
  1730. {
  1731. uint32_t outbound_doorbell;
  1732. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  1733. /*
  1734. *******************************************************************
  1735. ** Maybe here we need to check wrqbuffer_lock is lock or not
  1736. ** DOORBELL: din! don!
  1737. ** check if there are any mail need to pack from firmware
  1738. *******************************************************************
  1739. */
  1740. outbound_doorbell = readl(&reg->outbound_doorbell);
  1741. do {
  1742. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  1743. readl(&reg->outbound_doorbell_clear);
  1744. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
  1745. arcmsr_iop2drv_data_wrote_handle(pACB);
  1746. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
  1747. arcmsr_iop2drv_data_read_handle(pACB);
  1748. if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
  1749. arcmsr_hbaC_message_isr(pACB);
  1750. outbound_doorbell = readl(&reg->outbound_doorbell);
  1751. } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
  1752. | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
  1753. | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
  1754. }
  1755. static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
  1756. {
  1757. uint32_t outbound_doorbell;
  1758. struct MessageUnit_D *pmu = pACB->pmuD;
  1759. outbound_doorbell = readl(pmu->outbound_doorbell);
  1760. do {
  1761. writel(outbound_doorbell, pmu->outbound_doorbell);
  1762. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
  1763. arcmsr_hbaD_message_isr(pACB);
  1764. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
  1765. arcmsr_iop2drv_data_wrote_handle(pACB);
  1766. if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
  1767. arcmsr_iop2drv_data_read_handle(pACB);
  1768. outbound_doorbell = readl(pmu->outbound_doorbell);
  1769. } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
  1770. | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
  1771. | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
  1772. }
  1773. static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
  1774. {
  1775. uint32_t flag_ccb;
  1776. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1777. struct ARCMSR_CDB *pARCMSR_CDB;
  1778. struct CommandControlBlock *pCCB;
  1779. bool error;
  1780. while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
  1781. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1782. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1783. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1784. arcmsr_drain_donequeue(acb, pCCB, error);
  1785. }
  1786. }
  1787. static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
  1788. {
  1789. uint32_t index;
  1790. uint32_t flag_ccb;
  1791. struct MessageUnit_B *reg = acb->pmuB;
  1792. struct ARCMSR_CDB *pARCMSR_CDB;
  1793. struct CommandControlBlock *pCCB;
  1794. bool error;
  1795. index = reg->doneq_index;
  1796. while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
  1797. reg->done_qbuffer[index] = 0;
  1798. pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
  1799. pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
  1800. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  1801. arcmsr_drain_donequeue(acb, pCCB, error);
  1802. index++;
  1803. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  1804. reg->doneq_index = index;
  1805. }
  1806. }
  1807. static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
  1808. {
  1809. struct MessageUnit_C __iomem *phbcmu;
  1810. struct ARCMSR_CDB *arcmsr_cdb;
  1811. struct CommandControlBlock *ccb;
  1812. uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
  1813. int error;
  1814. phbcmu = acb->pmuC;
  1815. /* areca cdb command done */
  1816. /* Use correct offset and size for syncing */
  1817. while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
  1818. 0xFFFFFFFF) {
  1819. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  1820. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  1821. + ccb_cdb_phy);
  1822. ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
  1823. arcmsr_cdb);
  1824. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  1825. ? true : false;
  1826. /* check if command done with no error */
  1827. arcmsr_drain_donequeue(acb, ccb, error);
  1828. throttling++;
  1829. if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
  1830. writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
  1831. &phbcmu->inbound_doorbell);
  1832. throttling = 0;
  1833. }
  1834. }
  1835. }
  1836. static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
  1837. {
  1838. u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
  1839. uint32_t addressLow, ccb_cdb_phy;
  1840. int error;
  1841. struct MessageUnit_D *pmu;
  1842. struct ARCMSR_CDB *arcmsr_cdb;
  1843. struct CommandControlBlock *ccb;
  1844. unsigned long flags;
  1845. spin_lock_irqsave(&acb->doneq_lock, flags);
  1846. pmu = acb->pmuD;
  1847. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  1848. doneq_index = pmu->doneq_index;
  1849. if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
  1850. do {
  1851. toggle = doneq_index & 0x4000;
  1852. index_stripped = (doneq_index & 0xFFF) + 1;
  1853. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  1854. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  1855. ((toggle ^ 0x4000) + 1);
  1856. doneq_index = pmu->doneq_index;
  1857. addressLow = pmu->done_qbuffer[doneq_index &
  1858. 0xFFF].addressLow;
  1859. ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
  1860. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
  1861. + ccb_cdb_phy);
  1862. ccb = container_of(arcmsr_cdb,
  1863. struct CommandControlBlock, arcmsr_cdb);
  1864. error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  1865. ? true : false;
  1866. arcmsr_drain_donequeue(acb, ccb, error);
  1867. writel(doneq_index, pmu->outboundlist_read_pointer);
  1868. } while ((doneq_index & 0xFFF) !=
  1869. (outbound_write_pointer & 0xFFF));
  1870. }
  1871. writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
  1872. pmu->outboundlist_interrupt_cause);
  1873. readl(pmu->outboundlist_interrupt_cause);
  1874. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  1875. }
  1876. /*
  1877. **********************************************************************************
  1878. ** Handle a message interrupt
  1879. **
  1880. ** The only message interrupt we expect is in response to a query for the current adapter config.
  1881. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1882. **********************************************************************************
  1883. */
  1884. static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
  1885. {
  1886. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1887. /*clear interrupt and message state*/
  1888. writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
  1889. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1890. }
  1891. static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
  1892. {
  1893. struct MessageUnit_B *reg = acb->pmuB;
  1894. /*clear interrupt and message state*/
  1895. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  1896. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1897. }
  1898. /*
  1899. **********************************************************************************
  1900. ** Handle a message interrupt
  1901. **
  1902. ** The only message interrupt we expect is in response to a query for the
  1903. ** current adapter config.
  1904. ** We want this in order to compare the drivemap so that we can detect newly-attached drives.
  1905. **********************************************************************************
  1906. */
  1907. static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
  1908. {
  1909. struct MessageUnit_C __iomem *reg = acb->pmuC;
  1910. /*clear interrupt and message state*/
  1911. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
  1912. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1913. }
  1914. static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
  1915. {
  1916. struct MessageUnit_D *reg = acb->pmuD;
  1917. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
  1918. readl(reg->outbound_doorbell);
  1919. schedule_work(&acb->arcmsr_do_message_isr_bh);
  1920. }
  1921. static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
  1922. {
  1923. uint32_t outbound_intstatus;
  1924. struct MessageUnit_A __iomem *reg = acb->pmuA;
  1925. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1926. acb->outbound_int_enable;
  1927. if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
  1928. return IRQ_NONE;
  1929. do {
  1930. writel(outbound_intstatus, &reg->outbound_intstatus);
  1931. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
  1932. arcmsr_hbaA_doorbell_isr(acb);
  1933. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
  1934. arcmsr_hbaA_postqueue_isr(acb);
  1935. if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
  1936. arcmsr_hbaA_message_isr(acb);
  1937. outbound_intstatus = readl(&reg->outbound_intstatus) &
  1938. acb->outbound_int_enable;
  1939. } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
  1940. | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
  1941. | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
  1942. return IRQ_HANDLED;
  1943. }
  1944. static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
  1945. {
  1946. uint32_t outbound_doorbell;
  1947. struct MessageUnit_B *reg = acb->pmuB;
  1948. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  1949. acb->outbound_int_enable;
  1950. if (!outbound_doorbell)
  1951. return IRQ_NONE;
  1952. do {
  1953. writel(~outbound_doorbell, reg->iop2drv_doorbell);
  1954. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  1955. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
  1956. arcmsr_iop2drv_data_wrote_handle(acb);
  1957. if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
  1958. arcmsr_iop2drv_data_read_handle(acb);
  1959. if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
  1960. arcmsr_hbaB_postqueue_isr(acb);
  1961. if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
  1962. arcmsr_hbaB_message_isr(acb);
  1963. outbound_doorbell = readl(reg->iop2drv_doorbell) &
  1964. acb->outbound_int_enable;
  1965. } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
  1966. | ARCMSR_IOP2DRV_DATA_READ_OK
  1967. | ARCMSR_IOP2DRV_CDB_DONE
  1968. | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
  1969. return IRQ_HANDLED;
  1970. }
  1971. static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
  1972. {
  1973. uint32_t host_interrupt_status;
  1974. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  1975. /*
  1976. *********************************************
  1977. ** check outbound intstatus
  1978. *********************************************
  1979. */
  1980. host_interrupt_status = readl(&phbcmu->host_int_status) &
  1981. (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  1982. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
  1983. if (!host_interrupt_status)
  1984. return IRQ_NONE;
  1985. do {
  1986. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
  1987. arcmsr_hbaC_doorbell_isr(pACB);
  1988. /* MU post queue interrupts*/
  1989. if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
  1990. arcmsr_hbaC_postqueue_isr(pACB);
  1991. host_interrupt_status = readl(&phbcmu->host_int_status);
  1992. } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
  1993. ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
  1994. return IRQ_HANDLED;
  1995. }
  1996. static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
  1997. {
  1998. u32 host_interrupt_status;
  1999. struct MessageUnit_D *pmu = pACB->pmuD;
  2000. host_interrupt_status = readl(pmu->host_int_status) &
  2001. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2002. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
  2003. if (!host_interrupt_status)
  2004. return IRQ_NONE;
  2005. do {
  2006. /* MU post queue interrupts*/
  2007. if (host_interrupt_status &
  2008. ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
  2009. arcmsr_hbaD_postqueue_isr(pACB);
  2010. if (host_interrupt_status &
  2011. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
  2012. arcmsr_hbaD_doorbell_isr(pACB);
  2013. host_interrupt_status = readl(pmu->host_int_status);
  2014. } while (host_interrupt_status &
  2015. (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
  2016. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
  2017. return IRQ_HANDLED;
  2018. }
  2019. static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
  2020. {
  2021. switch (acb->adapter_type) {
  2022. case ACB_ADAPTER_TYPE_A:
  2023. return arcmsr_hbaA_handle_isr(acb);
  2024. break;
  2025. case ACB_ADAPTER_TYPE_B:
  2026. return arcmsr_hbaB_handle_isr(acb);
  2027. break;
  2028. case ACB_ADAPTER_TYPE_C:
  2029. return arcmsr_hbaC_handle_isr(acb);
  2030. case ACB_ADAPTER_TYPE_D:
  2031. return arcmsr_hbaD_handle_isr(acb);
  2032. default:
  2033. return IRQ_NONE;
  2034. }
  2035. }
  2036. static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
  2037. {
  2038. if (acb) {
  2039. /* stop adapter background rebuild */
  2040. if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
  2041. uint32_t intmask_org;
  2042. acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
  2043. intmask_org = arcmsr_disable_outbound_ints(acb);
  2044. arcmsr_stop_adapter_bgrb(acb);
  2045. arcmsr_flush_adapter_cache(acb);
  2046. arcmsr_enable_outbound_ints(acb, intmask_org);
  2047. }
  2048. }
  2049. }
  2050. void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
  2051. {
  2052. uint32_t i;
  2053. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2054. for (i = 0; i < 15; i++) {
  2055. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2056. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2057. acb->rqbuf_getIndex = 0;
  2058. acb->rqbuf_putIndex = 0;
  2059. arcmsr_iop_message_read(acb);
  2060. mdelay(30);
  2061. } else if (acb->rqbuf_getIndex !=
  2062. acb->rqbuf_putIndex) {
  2063. acb->rqbuf_getIndex = 0;
  2064. acb->rqbuf_putIndex = 0;
  2065. mdelay(30);
  2066. } else
  2067. break;
  2068. }
  2069. }
  2070. }
  2071. static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
  2072. struct scsi_cmnd *cmd)
  2073. {
  2074. char *buffer;
  2075. unsigned short use_sg;
  2076. int retvalue = 0, transfer_len = 0;
  2077. unsigned long flags;
  2078. struct CMD_MESSAGE_FIELD *pcmdmessagefld;
  2079. uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
  2080. (uint32_t)cmd->cmnd[6] << 16 |
  2081. (uint32_t)cmd->cmnd[7] << 8 |
  2082. (uint32_t)cmd->cmnd[8];
  2083. struct scatterlist *sg;
  2084. use_sg = scsi_sg_count(cmd);
  2085. sg = scsi_sglist(cmd);
  2086. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2087. if (use_sg > 1) {
  2088. retvalue = ARCMSR_MESSAGE_FAIL;
  2089. goto message_out;
  2090. }
  2091. transfer_len += sg->length;
  2092. if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
  2093. retvalue = ARCMSR_MESSAGE_FAIL;
  2094. pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
  2095. goto message_out;
  2096. }
  2097. pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
  2098. switch (controlcode) {
  2099. case ARCMSR_MESSAGE_READ_RQBUFFER: {
  2100. unsigned char *ver_addr;
  2101. uint8_t *ptmpQbuffer;
  2102. uint32_t allxfer_len = 0;
  2103. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2104. if (!ver_addr) {
  2105. retvalue = ARCMSR_MESSAGE_FAIL;
  2106. pr_info("%s: memory not enough!\n", __func__);
  2107. goto message_out;
  2108. }
  2109. ptmpQbuffer = ver_addr;
  2110. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2111. if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
  2112. unsigned int tail = acb->rqbuf_getIndex;
  2113. unsigned int head = acb->rqbuf_putIndex;
  2114. unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
  2115. allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
  2116. if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
  2117. allxfer_len = ARCMSR_API_DATA_BUFLEN;
  2118. if (allxfer_len <= cnt_to_end)
  2119. memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
  2120. else {
  2121. memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
  2122. memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
  2123. }
  2124. acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
  2125. }
  2126. memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
  2127. allxfer_len);
  2128. if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
  2129. struct QBUFFER __iomem *prbuffer;
  2130. acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
  2131. prbuffer = arcmsr_get_iop_rqbuffer(acb);
  2132. if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
  2133. acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
  2134. }
  2135. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2136. kfree(ver_addr);
  2137. pcmdmessagefld->cmdmessage.Length = allxfer_len;
  2138. if (acb->fw_flag == FW_DEADLOCK)
  2139. pcmdmessagefld->cmdmessage.ReturnCode =
  2140. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2141. else
  2142. pcmdmessagefld->cmdmessage.ReturnCode =
  2143. ARCMSR_MESSAGE_RETURNCODE_OK;
  2144. break;
  2145. }
  2146. case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
  2147. unsigned char *ver_addr;
  2148. int32_t user_len, cnt2end;
  2149. uint8_t *pQbuffer, *ptmpuserbuffer;
  2150. ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
  2151. if (!ver_addr) {
  2152. retvalue = ARCMSR_MESSAGE_FAIL;
  2153. goto message_out;
  2154. }
  2155. ptmpuserbuffer = ver_addr;
  2156. user_len = pcmdmessagefld->cmdmessage.Length;
  2157. memcpy(ptmpuserbuffer,
  2158. pcmdmessagefld->messagedatabuffer, user_len);
  2159. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2160. if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
  2161. struct SENSE_DATA *sensebuffer =
  2162. (struct SENSE_DATA *)cmd->sense_buffer;
  2163. arcmsr_write_ioctldata2iop(acb);
  2164. /* has error report sensedata */
  2165. sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
  2166. sensebuffer->SenseKey = ILLEGAL_REQUEST;
  2167. sensebuffer->AdditionalSenseLength = 0x0A;
  2168. sensebuffer->AdditionalSenseCode = 0x20;
  2169. sensebuffer->Valid = 1;
  2170. retvalue = ARCMSR_MESSAGE_FAIL;
  2171. } else {
  2172. pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
  2173. cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
  2174. if (user_len > cnt2end) {
  2175. memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
  2176. ptmpuserbuffer += cnt2end;
  2177. user_len -= cnt2end;
  2178. acb->wqbuf_putIndex = 0;
  2179. pQbuffer = acb->wqbuffer;
  2180. }
  2181. memcpy(pQbuffer, ptmpuserbuffer, user_len);
  2182. acb->wqbuf_putIndex += user_len;
  2183. acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
  2184. if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
  2185. acb->acb_flags &=
  2186. ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
  2187. arcmsr_write_ioctldata2iop(acb);
  2188. }
  2189. }
  2190. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2191. kfree(ver_addr);
  2192. if (acb->fw_flag == FW_DEADLOCK)
  2193. pcmdmessagefld->cmdmessage.ReturnCode =
  2194. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2195. else
  2196. pcmdmessagefld->cmdmessage.ReturnCode =
  2197. ARCMSR_MESSAGE_RETURNCODE_OK;
  2198. break;
  2199. }
  2200. case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
  2201. uint8_t *pQbuffer = acb->rqbuffer;
  2202. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2203. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2204. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2205. acb->rqbuf_getIndex = 0;
  2206. acb->rqbuf_putIndex = 0;
  2207. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2208. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2209. if (acb->fw_flag == FW_DEADLOCK)
  2210. pcmdmessagefld->cmdmessage.ReturnCode =
  2211. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2212. else
  2213. pcmdmessagefld->cmdmessage.ReturnCode =
  2214. ARCMSR_MESSAGE_RETURNCODE_OK;
  2215. break;
  2216. }
  2217. case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
  2218. uint8_t *pQbuffer = acb->wqbuffer;
  2219. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2220. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2221. ACB_F_MESSAGE_WQBUFFER_READED);
  2222. acb->wqbuf_getIndex = 0;
  2223. acb->wqbuf_putIndex = 0;
  2224. memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
  2225. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2226. if (acb->fw_flag == FW_DEADLOCK)
  2227. pcmdmessagefld->cmdmessage.ReturnCode =
  2228. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2229. else
  2230. pcmdmessagefld->cmdmessage.ReturnCode =
  2231. ARCMSR_MESSAGE_RETURNCODE_OK;
  2232. break;
  2233. }
  2234. case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
  2235. uint8_t *pQbuffer;
  2236. arcmsr_clear_iop2drv_rqueue_buffer(acb);
  2237. spin_lock_irqsave(&acb->rqbuffer_lock, flags);
  2238. acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
  2239. acb->rqbuf_getIndex = 0;
  2240. acb->rqbuf_putIndex = 0;
  2241. pQbuffer = acb->rqbuffer;
  2242. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2243. spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
  2244. spin_lock_irqsave(&acb->wqbuffer_lock, flags);
  2245. acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
  2246. ACB_F_MESSAGE_WQBUFFER_READED);
  2247. acb->wqbuf_getIndex = 0;
  2248. acb->wqbuf_putIndex = 0;
  2249. pQbuffer = acb->wqbuffer;
  2250. memset(pQbuffer, 0, sizeof(struct QBUFFER));
  2251. spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
  2252. if (acb->fw_flag == FW_DEADLOCK)
  2253. pcmdmessagefld->cmdmessage.ReturnCode =
  2254. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2255. else
  2256. pcmdmessagefld->cmdmessage.ReturnCode =
  2257. ARCMSR_MESSAGE_RETURNCODE_OK;
  2258. break;
  2259. }
  2260. case ARCMSR_MESSAGE_RETURN_CODE_3F: {
  2261. if (acb->fw_flag == FW_DEADLOCK)
  2262. pcmdmessagefld->cmdmessage.ReturnCode =
  2263. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2264. else
  2265. pcmdmessagefld->cmdmessage.ReturnCode =
  2266. ARCMSR_MESSAGE_RETURNCODE_3F;
  2267. break;
  2268. }
  2269. case ARCMSR_MESSAGE_SAY_HELLO: {
  2270. int8_t *hello_string = "Hello! I am ARCMSR";
  2271. if (acb->fw_flag == FW_DEADLOCK)
  2272. pcmdmessagefld->cmdmessage.ReturnCode =
  2273. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2274. else
  2275. pcmdmessagefld->cmdmessage.ReturnCode =
  2276. ARCMSR_MESSAGE_RETURNCODE_OK;
  2277. memcpy(pcmdmessagefld->messagedatabuffer,
  2278. hello_string, (int16_t)strlen(hello_string));
  2279. break;
  2280. }
  2281. case ARCMSR_MESSAGE_SAY_GOODBYE: {
  2282. if (acb->fw_flag == FW_DEADLOCK)
  2283. pcmdmessagefld->cmdmessage.ReturnCode =
  2284. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2285. else
  2286. pcmdmessagefld->cmdmessage.ReturnCode =
  2287. ARCMSR_MESSAGE_RETURNCODE_OK;
  2288. arcmsr_iop_parking(acb);
  2289. break;
  2290. }
  2291. case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
  2292. if (acb->fw_flag == FW_DEADLOCK)
  2293. pcmdmessagefld->cmdmessage.ReturnCode =
  2294. ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
  2295. else
  2296. pcmdmessagefld->cmdmessage.ReturnCode =
  2297. ARCMSR_MESSAGE_RETURNCODE_OK;
  2298. arcmsr_flush_adapter_cache(acb);
  2299. break;
  2300. }
  2301. default:
  2302. retvalue = ARCMSR_MESSAGE_FAIL;
  2303. pr_info("%s: unknown controlcode!\n", __func__);
  2304. }
  2305. message_out:
  2306. if (use_sg) {
  2307. struct scatterlist *sg = scsi_sglist(cmd);
  2308. kunmap_atomic(buffer - sg->offset);
  2309. }
  2310. return retvalue;
  2311. }
  2312. static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
  2313. {
  2314. struct list_head *head = &acb->ccb_free_list;
  2315. struct CommandControlBlock *ccb = NULL;
  2316. unsigned long flags;
  2317. spin_lock_irqsave(&acb->ccblist_lock, flags);
  2318. if (!list_empty(head)) {
  2319. ccb = list_entry(head->next, struct CommandControlBlock, list);
  2320. list_del_init(&ccb->list);
  2321. }else{
  2322. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2323. return NULL;
  2324. }
  2325. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  2326. return ccb;
  2327. }
  2328. static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
  2329. struct scsi_cmnd *cmd)
  2330. {
  2331. switch (cmd->cmnd[0]) {
  2332. case INQUIRY: {
  2333. unsigned char inqdata[36];
  2334. char *buffer;
  2335. struct scatterlist *sg;
  2336. if (cmd->device->lun) {
  2337. cmd->result = (DID_TIME_OUT << 16);
  2338. cmd->scsi_done(cmd);
  2339. return;
  2340. }
  2341. inqdata[0] = TYPE_PROCESSOR;
  2342. /* Periph Qualifier & Periph Dev Type */
  2343. inqdata[1] = 0;
  2344. /* rem media bit & Dev Type Modifier */
  2345. inqdata[2] = 0;
  2346. /* ISO, ECMA, & ANSI versions */
  2347. inqdata[4] = 31;
  2348. /* length of additional data */
  2349. strncpy(&inqdata[8], "Areca ", 8);
  2350. /* Vendor Identification */
  2351. strncpy(&inqdata[16], "RAID controller ", 16);
  2352. /* Product Identification */
  2353. strncpy(&inqdata[32], "R001", 4); /* Product Revision */
  2354. sg = scsi_sglist(cmd);
  2355. buffer = kmap_atomic(sg_page(sg)) + sg->offset;
  2356. memcpy(buffer, inqdata, sizeof(inqdata));
  2357. sg = scsi_sglist(cmd);
  2358. kunmap_atomic(buffer - sg->offset);
  2359. cmd->scsi_done(cmd);
  2360. }
  2361. break;
  2362. case WRITE_BUFFER:
  2363. case READ_BUFFER: {
  2364. if (arcmsr_iop_message_xfer(acb, cmd))
  2365. cmd->result = (DID_ERROR << 16);
  2366. cmd->scsi_done(cmd);
  2367. }
  2368. break;
  2369. default:
  2370. cmd->scsi_done(cmd);
  2371. }
  2372. }
  2373. static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
  2374. void (* done)(struct scsi_cmnd *))
  2375. {
  2376. struct Scsi_Host *host = cmd->device->host;
  2377. struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
  2378. struct CommandControlBlock *ccb;
  2379. int target = cmd->device->id;
  2380. int lun = cmd->device->lun;
  2381. uint8_t scsicmd = cmd->cmnd[0];
  2382. cmd->scsi_done = done;
  2383. cmd->host_scribble = NULL;
  2384. cmd->result = 0;
  2385. if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
  2386. if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
  2387. cmd->result = (DID_NO_CONNECT << 16);
  2388. }
  2389. cmd->scsi_done(cmd);
  2390. return 0;
  2391. }
  2392. if (target == 16) {
  2393. /* virtual device for iop message transfer */
  2394. arcmsr_handle_virtual_command(acb, cmd);
  2395. return 0;
  2396. }
  2397. ccb = arcmsr_get_freeccb(acb);
  2398. if (!ccb)
  2399. return SCSI_MLQUEUE_HOST_BUSY;
  2400. if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
  2401. cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
  2402. cmd->scsi_done(cmd);
  2403. return 0;
  2404. }
  2405. arcmsr_post_ccb(acb, ccb);
  2406. return 0;
  2407. }
  2408. static DEF_SCSI_QCMD(arcmsr_queue_command)
  2409. static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
  2410. {
  2411. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2412. char *acb_firm_model = acb->firm_model;
  2413. char *acb_firm_version = acb->firm_version;
  2414. char *acb_device_map = acb->device_map;
  2415. char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
  2416. char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
  2417. char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
  2418. int count;
  2419. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2420. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  2421. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2422. miscellaneous data' timeout \n", acb->host->host_no);
  2423. return false;
  2424. }
  2425. count = 8;
  2426. while (count){
  2427. *acb_firm_model = readb(iop_firm_model);
  2428. acb_firm_model++;
  2429. iop_firm_model++;
  2430. count--;
  2431. }
  2432. count = 16;
  2433. while (count){
  2434. *acb_firm_version = readb(iop_firm_version);
  2435. acb_firm_version++;
  2436. iop_firm_version++;
  2437. count--;
  2438. }
  2439. count=16;
  2440. while(count){
  2441. *acb_device_map = readb(iop_device_map);
  2442. acb_device_map++;
  2443. iop_device_map++;
  2444. count--;
  2445. }
  2446. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2447. acb->host->host_no,
  2448. acb->firm_model,
  2449. acb->firm_version);
  2450. acb->signature = readl(&reg->message_rwbuffer[0]);
  2451. acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
  2452. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
  2453. acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
  2454. acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
  2455. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2456. return true;
  2457. }
  2458. static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
  2459. {
  2460. struct MessageUnit_B *reg = acb->pmuB;
  2461. struct pci_dev *pdev = acb->pdev;
  2462. void *dma_coherent;
  2463. dma_addr_t dma_coherent_handle;
  2464. char *acb_firm_model = acb->firm_model;
  2465. char *acb_firm_version = acb->firm_version;
  2466. char *acb_device_map = acb->device_map;
  2467. char __iomem *iop_firm_model;
  2468. /*firm_model,15,60-67*/
  2469. char __iomem *iop_firm_version;
  2470. /*firm_version,17,68-83*/
  2471. char __iomem *iop_device_map;
  2472. /*firm_version,21,84-99*/
  2473. int count;
  2474. acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
  2475. dma_coherent = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  2476. &dma_coherent_handle, GFP_KERNEL);
  2477. if (!dma_coherent){
  2478. printk(KERN_NOTICE
  2479. "arcmsr%d: dma_alloc_coherent got error for hbb mu\n",
  2480. acb->host->host_no);
  2481. return false;
  2482. }
  2483. acb->dma_coherent_handle2 = dma_coherent_handle;
  2484. acb->dma_coherent2 = dma_coherent;
  2485. reg = (struct MessageUnit_B *)dma_coherent;
  2486. acb->pmuB = reg;
  2487. reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
  2488. reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
  2489. reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
  2490. reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
  2491. reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
  2492. reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
  2493. reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
  2494. iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
  2495. iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
  2496. iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
  2497. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  2498. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  2499. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2500. miscellaneous data' timeout \n", acb->host->host_no);
  2501. return false;
  2502. }
  2503. count = 8;
  2504. while (count){
  2505. *acb_firm_model = readb(iop_firm_model);
  2506. acb_firm_model++;
  2507. iop_firm_model++;
  2508. count--;
  2509. }
  2510. count = 16;
  2511. while (count){
  2512. *acb_firm_version = readb(iop_firm_version);
  2513. acb_firm_version++;
  2514. iop_firm_version++;
  2515. count--;
  2516. }
  2517. count = 16;
  2518. while(count){
  2519. *acb_device_map = readb(iop_device_map);
  2520. acb_device_map++;
  2521. iop_device_map++;
  2522. count--;
  2523. }
  2524. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2525. acb->host->host_no,
  2526. acb->firm_model,
  2527. acb->firm_version);
  2528. acb->signature = readl(&reg->message_rwbuffer[1]);
  2529. /*firm_signature,1,00-03*/
  2530. acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
  2531. /*firm_request_len,1,04-07*/
  2532. acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
  2533. /*firm_numbers_queue,2,08-11*/
  2534. acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
  2535. /*firm_sdram_size,3,12-15*/
  2536. acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
  2537. /*firm_ide_channels,4,16-19*/
  2538. acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2539. /*firm_ide_channels,4,16-19*/
  2540. return true;
  2541. }
  2542. static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
  2543. {
  2544. uint32_t intmask_org, Index, firmware_state = 0;
  2545. struct MessageUnit_C __iomem *reg = pACB->pmuC;
  2546. char *acb_firm_model = pACB->firm_model;
  2547. char *acb_firm_version = pACB->firm_version;
  2548. char __iomem *iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
  2549. char __iomem *iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
  2550. int count;
  2551. /* disable all outbound interrupt */
  2552. intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
  2553. writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
  2554. /* wait firmware ready */
  2555. do {
  2556. firmware_state = readl(&reg->outbound_msgaddr1);
  2557. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  2558. /* post "get config" instruction */
  2559. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  2560. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  2561. /* wait message ready */
  2562. for (Index = 0; Index < 2000; Index++) {
  2563. if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
  2564. writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
  2565. break;
  2566. }
  2567. udelay(10);
  2568. } /*max 1 seconds*/
  2569. if (Index >= 2000) {
  2570. printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
  2571. miscellaneous data' timeout \n", pACB->host->host_no);
  2572. return false;
  2573. }
  2574. count = 8;
  2575. while (count) {
  2576. *acb_firm_model = readb(iop_firm_model);
  2577. acb_firm_model++;
  2578. iop_firm_model++;
  2579. count--;
  2580. }
  2581. count = 16;
  2582. while (count) {
  2583. *acb_firm_version = readb(iop_firm_version);
  2584. acb_firm_version++;
  2585. iop_firm_version++;
  2586. count--;
  2587. }
  2588. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2589. pACB->host->host_no,
  2590. pACB->firm_model,
  2591. pACB->firm_version);
  2592. pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
  2593. pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
  2594. pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
  2595. pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
  2596. pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
  2597. /*all interrupt service will be enable at arcmsr_iop_init*/
  2598. return true;
  2599. }
  2600. static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
  2601. {
  2602. char *acb_firm_model = acb->firm_model;
  2603. char *acb_firm_version = acb->firm_version;
  2604. char *acb_device_map = acb->device_map;
  2605. char __iomem *iop_firm_model;
  2606. char __iomem *iop_firm_version;
  2607. char __iomem *iop_device_map;
  2608. u32 count;
  2609. struct MessageUnit_D *reg;
  2610. void *dma_coherent2;
  2611. dma_addr_t dma_coherent_handle2;
  2612. struct pci_dev *pdev = acb->pdev;
  2613. acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
  2614. dma_coherent2 = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
  2615. &dma_coherent_handle2, GFP_KERNEL);
  2616. if (!dma_coherent2) {
  2617. pr_notice("DMA allocation failed...\n");
  2618. return false;
  2619. }
  2620. memset(dma_coherent2, 0, acb->roundup_ccbsize);
  2621. acb->dma_coherent_handle2 = dma_coherent_handle2;
  2622. acb->dma_coherent2 = dma_coherent2;
  2623. reg = (struct MessageUnit_D *)dma_coherent2;
  2624. acb->pmuD = reg;
  2625. reg->chip_id = acb->mem_base0 + ARCMSR_ARC1214_CHIP_ID;
  2626. reg->cpu_mem_config = acb->mem_base0 +
  2627. ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION;
  2628. reg->i2o_host_interrupt_mask = acb->mem_base0 +
  2629. ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK;
  2630. reg->sample_at_reset = acb->mem_base0 + ARCMSR_ARC1214_SAMPLE_RESET;
  2631. reg->reset_request = acb->mem_base0 + ARCMSR_ARC1214_RESET_REQUEST;
  2632. reg->host_int_status = acb->mem_base0 +
  2633. ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS;
  2634. reg->pcief0_int_enable = acb->mem_base0 +
  2635. ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE;
  2636. reg->inbound_msgaddr0 = acb->mem_base0 +
  2637. ARCMSR_ARC1214_INBOUND_MESSAGE0;
  2638. reg->inbound_msgaddr1 = acb->mem_base0 +
  2639. ARCMSR_ARC1214_INBOUND_MESSAGE1;
  2640. reg->outbound_msgaddr0 = acb->mem_base0 +
  2641. ARCMSR_ARC1214_OUTBOUND_MESSAGE0;
  2642. reg->outbound_msgaddr1 = acb->mem_base0 +
  2643. ARCMSR_ARC1214_OUTBOUND_MESSAGE1;
  2644. reg->inbound_doorbell = acb->mem_base0 +
  2645. ARCMSR_ARC1214_INBOUND_DOORBELL;
  2646. reg->outbound_doorbell = acb->mem_base0 +
  2647. ARCMSR_ARC1214_OUTBOUND_DOORBELL;
  2648. reg->outbound_doorbell_enable = acb->mem_base0 +
  2649. ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE;
  2650. reg->inboundlist_base_low = acb->mem_base0 +
  2651. ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW;
  2652. reg->inboundlist_base_high = acb->mem_base0 +
  2653. ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH;
  2654. reg->inboundlist_write_pointer = acb->mem_base0 +
  2655. ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER;
  2656. reg->outboundlist_base_low = acb->mem_base0 +
  2657. ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW;
  2658. reg->outboundlist_base_high = acb->mem_base0 +
  2659. ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH;
  2660. reg->outboundlist_copy_pointer = acb->mem_base0 +
  2661. ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER;
  2662. reg->outboundlist_read_pointer = acb->mem_base0 +
  2663. ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER;
  2664. reg->outboundlist_interrupt_cause = acb->mem_base0 +
  2665. ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE;
  2666. reg->outboundlist_interrupt_enable = acb->mem_base0 +
  2667. ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE;
  2668. reg->message_wbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_WBUFFER;
  2669. reg->message_rbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_RBUFFER;
  2670. reg->msgcode_rwbuffer = acb->mem_base0 +
  2671. ARCMSR_ARC1214_MESSAGE_RWBUFFER;
  2672. iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]);
  2673. iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]);
  2674. iop_device_map = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
  2675. if (readl(acb->pmuD->outbound_doorbell) &
  2676. ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
  2677. writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
  2678. acb->pmuD->outbound_doorbell);/*clear interrupt*/
  2679. }
  2680. /* post "get config" instruction */
  2681. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
  2682. /* wait message ready */
  2683. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  2684. pr_notice("arcmsr%d: wait get adapter firmware "
  2685. "miscellaneous data timeout\n", acb->host->host_no);
  2686. dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
  2687. acb->dma_coherent2, acb->dma_coherent_handle2);
  2688. return false;
  2689. }
  2690. count = 8;
  2691. while (count) {
  2692. *acb_firm_model = readb(iop_firm_model);
  2693. acb_firm_model++;
  2694. iop_firm_model++;
  2695. count--;
  2696. }
  2697. count = 16;
  2698. while (count) {
  2699. *acb_firm_version = readb(iop_firm_version);
  2700. acb_firm_version++;
  2701. iop_firm_version++;
  2702. count--;
  2703. }
  2704. count = 16;
  2705. while (count) {
  2706. *acb_device_map = readb(iop_device_map);
  2707. acb_device_map++;
  2708. iop_device_map++;
  2709. count--;
  2710. }
  2711. acb->signature = readl(&reg->msgcode_rwbuffer[1]);
  2712. /*firm_signature,1,00-03*/
  2713. acb->firm_request_len = readl(&reg->msgcode_rwbuffer[2]);
  2714. /*firm_request_len,1,04-07*/
  2715. acb->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[3]);
  2716. /*firm_numbers_queue,2,08-11*/
  2717. acb->firm_sdram_size = readl(&reg->msgcode_rwbuffer[4]);
  2718. /*firm_sdram_size,3,12-15*/
  2719. acb->firm_hd_channels = readl(&reg->msgcode_rwbuffer[5]);
  2720. /*firm_hd_channels,4,16-19*/
  2721. acb->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]);
  2722. pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
  2723. acb->host->host_no,
  2724. acb->firm_model,
  2725. acb->firm_version);
  2726. return true;
  2727. }
  2728. static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
  2729. {
  2730. bool rtn = false;
  2731. switch (acb->adapter_type) {
  2732. case ACB_ADAPTER_TYPE_A:
  2733. rtn = arcmsr_hbaA_get_config(acb);
  2734. break;
  2735. case ACB_ADAPTER_TYPE_B:
  2736. rtn = arcmsr_hbaB_get_config(acb);
  2737. break;
  2738. case ACB_ADAPTER_TYPE_C:
  2739. rtn = arcmsr_hbaC_get_config(acb);
  2740. break;
  2741. case ACB_ADAPTER_TYPE_D:
  2742. rtn = arcmsr_hbaD_get_config(acb);
  2743. break;
  2744. default:
  2745. break;
  2746. }
  2747. if (acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
  2748. acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD;
  2749. else
  2750. acb->maxOutstanding = acb->firm_numbers_queue - 1;
  2751. acb->host->can_queue = acb->maxOutstanding;
  2752. return rtn;
  2753. }
  2754. static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
  2755. struct CommandControlBlock *poll_ccb)
  2756. {
  2757. struct MessageUnit_A __iomem *reg = acb->pmuA;
  2758. struct CommandControlBlock *ccb;
  2759. struct ARCMSR_CDB *arcmsr_cdb;
  2760. uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
  2761. int rtn;
  2762. bool error;
  2763. polling_hba_ccb_retry:
  2764. poll_count++;
  2765. outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
  2766. writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
  2767. while (1) {
  2768. if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
  2769. if (poll_ccb_done){
  2770. rtn = SUCCESS;
  2771. break;
  2772. }else {
  2773. msleep(25);
  2774. if (poll_count > 100){
  2775. rtn = FAILED;
  2776. break;
  2777. }
  2778. goto polling_hba_ccb_retry;
  2779. }
  2780. }
  2781. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2782. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2783. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  2784. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2785. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2786. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2787. " poll command abort successfully \n"
  2788. , acb->host->host_no
  2789. , ccb->pcmd->device->id
  2790. , (u32)ccb->pcmd->device->lun
  2791. , ccb);
  2792. ccb->pcmd->result = DID_ABORT << 16;
  2793. arcmsr_ccb_complete(ccb);
  2794. continue;
  2795. }
  2796. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2797. " command done ccb = '0x%p'"
  2798. "ccboutstandingcount = %d \n"
  2799. , acb->host->host_no
  2800. , ccb
  2801. , atomic_read(&acb->ccboutstandingcount));
  2802. continue;
  2803. }
  2804. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2805. arcmsr_report_ccb_state(acb, ccb, error);
  2806. }
  2807. return rtn;
  2808. }
  2809. static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
  2810. struct CommandControlBlock *poll_ccb)
  2811. {
  2812. struct MessageUnit_B *reg = acb->pmuB;
  2813. struct ARCMSR_CDB *arcmsr_cdb;
  2814. struct CommandControlBlock *ccb;
  2815. uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
  2816. int index, rtn;
  2817. bool error;
  2818. polling_hbb_ccb_retry:
  2819. poll_count++;
  2820. /* clear doorbell interrupt */
  2821. writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  2822. while(1){
  2823. index = reg->doneq_index;
  2824. flag_ccb = reg->done_qbuffer[index];
  2825. if (flag_ccb == 0) {
  2826. if (poll_ccb_done){
  2827. rtn = SUCCESS;
  2828. break;
  2829. }else {
  2830. msleep(25);
  2831. if (poll_count > 100){
  2832. rtn = FAILED;
  2833. break;
  2834. }
  2835. goto polling_hbb_ccb_retry;
  2836. }
  2837. }
  2838. reg->done_qbuffer[index] = 0;
  2839. index++;
  2840. /*if last index number set it to 0 */
  2841. index %= ARCMSR_MAX_HBB_POSTQUEUE;
  2842. reg->doneq_index = index;
  2843. /* check if command done with no error*/
  2844. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
  2845. ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2846. poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
  2847. if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
  2848. if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
  2849. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2850. " poll command abort successfully \n"
  2851. ,acb->host->host_no
  2852. ,ccb->pcmd->device->id
  2853. ,(u32)ccb->pcmd->device->lun
  2854. ,ccb);
  2855. ccb->pcmd->result = DID_ABORT << 16;
  2856. arcmsr_ccb_complete(ccb);
  2857. continue;
  2858. }
  2859. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2860. " command done ccb = '0x%p'"
  2861. "ccboutstandingcount = %d \n"
  2862. , acb->host->host_no
  2863. , ccb
  2864. , atomic_read(&acb->ccboutstandingcount));
  2865. continue;
  2866. }
  2867. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
  2868. arcmsr_report_ccb_state(acb, ccb, error);
  2869. }
  2870. return rtn;
  2871. }
  2872. static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
  2873. struct CommandControlBlock *poll_ccb)
  2874. {
  2875. struct MessageUnit_C __iomem *reg = acb->pmuC;
  2876. uint32_t flag_ccb, ccb_cdb_phy;
  2877. struct ARCMSR_CDB *arcmsr_cdb;
  2878. bool error;
  2879. struct CommandControlBlock *pCCB;
  2880. uint32_t poll_ccb_done = 0, poll_count = 0;
  2881. int rtn;
  2882. polling_hbc_ccb_retry:
  2883. poll_count++;
  2884. while (1) {
  2885. if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
  2886. if (poll_ccb_done) {
  2887. rtn = SUCCESS;
  2888. break;
  2889. } else {
  2890. msleep(25);
  2891. if (poll_count > 100) {
  2892. rtn = FAILED;
  2893. break;
  2894. }
  2895. goto polling_hbc_ccb_retry;
  2896. }
  2897. }
  2898. flag_ccb = readl(&reg->outbound_queueport_low);
  2899. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2900. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
  2901. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
  2902. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  2903. /* check ifcommand done with no error*/
  2904. if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
  2905. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  2906. printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
  2907. " poll command abort successfully \n"
  2908. , acb->host->host_no
  2909. , pCCB->pcmd->device->id
  2910. , (u32)pCCB->pcmd->device->lun
  2911. , pCCB);
  2912. pCCB->pcmd->result = DID_ABORT << 16;
  2913. arcmsr_ccb_complete(pCCB);
  2914. continue;
  2915. }
  2916. printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
  2917. " command done ccb = '0x%p'"
  2918. "ccboutstandingcount = %d \n"
  2919. , acb->host->host_no
  2920. , pCCB
  2921. , atomic_read(&acb->ccboutstandingcount));
  2922. continue;
  2923. }
  2924. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
  2925. arcmsr_report_ccb_state(acb, pCCB, error);
  2926. }
  2927. return rtn;
  2928. }
  2929. static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
  2930. struct CommandControlBlock *poll_ccb)
  2931. {
  2932. bool error;
  2933. uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
  2934. int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
  2935. unsigned long flags;
  2936. struct ARCMSR_CDB *arcmsr_cdb;
  2937. struct CommandControlBlock *pCCB;
  2938. struct MessageUnit_D *pmu = acb->pmuD;
  2939. polling_hbaD_ccb_retry:
  2940. poll_count++;
  2941. while (1) {
  2942. spin_lock_irqsave(&acb->doneq_lock, flags);
  2943. outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
  2944. doneq_index = pmu->doneq_index;
  2945. if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
  2946. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2947. if (poll_ccb_done) {
  2948. rtn = SUCCESS;
  2949. break;
  2950. } else {
  2951. msleep(25);
  2952. if (poll_count > 40) {
  2953. rtn = FAILED;
  2954. break;
  2955. }
  2956. goto polling_hbaD_ccb_retry;
  2957. }
  2958. }
  2959. toggle = doneq_index & 0x4000;
  2960. index_stripped = (doneq_index & 0xFFF) + 1;
  2961. index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
  2962. pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
  2963. ((toggle ^ 0x4000) + 1);
  2964. doneq_index = pmu->doneq_index;
  2965. spin_unlock_irqrestore(&acb->doneq_lock, flags);
  2966. flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
  2967. ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
  2968. arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
  2969. ccb_cdb_phy);
  2970. pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
  2971. arcmsr_cdb);
  2972. poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
  2973. if ((pCCB->acb != acb) ||
  2974. (pCCB->startdone != ARCMSR_CCB_START)) {
  2975. if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
  2976. pr_notice("arcmsr%d: scsi id = %d "
  2977. "lun = %d ccb = '0x%p' poll command "
  2978. "abort successfully\n"
  2979. , acb->host->host_no
  2980. , pCCB->pcmd->device->id
  2981. , (u32)pCCB->pcmd->device->lun
  2982. , pCCB);
  2983. pCCB->pcmd->result = DID_ABORT << 16;
  2984. arcmsr_ccb_complete(pCCB);
  2985. continue;
  2986. }
  2987. pr_notice("arcmsr%d: polling an illegal "
  2988. "ccb command done ccb = '0x%p' "
  2989. "ccboutstandingcount = %d\n"
  2990. , acb->host->host_no
  2991. , pCCB
  2992. , atomic_read(&acb->ccboutstandingcount));
  2993. continue;
  2994. }
  2995. error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
  2996. ? true : false;
  2997. arcmsr_report_ccb_state(acb, pCCB, error);
  2998. }
  2999. return rtn;
  3000. }
  3001. static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
  3002. struct CommandControlBlock *poll_ccb)
  3003. {
  3004. int rtn = 0;
  3005. switch (acb->adapter_type) {
  3006. case ACB_ADAPTER_TYPE_A: {
  3007. rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
  3008. }
  3009. break;
  3010. case ACB_ADAPTER_TYPE_B: {
  3011. rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
  3012. }
  3013. break;
  3014. case ACB_ADAPTER_TYPE_C: {
  3015. rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
  3016. }
  3017. break;
  3018. case ACB_ADAPTER_TYPE_D:
  3019. rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
  3020. break;
  3021. }
  3022. return rtn;
  3023. }
  3024. static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
  3025. {
  3026. uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
  3027. dma_addr_t dma_coherent_handle;
  3028. /*
  3029. ********************************************************************
  3030. ** here we need to tell iop 331 our freeccb.HighPart
  3031. ** if freeccb.HighPart is not zero
  3032. ********************************************************************
  3033. */
  3034. switch (acb->adapter_type) {
  3035. case ACB_ADAPTER_TYPE_B:
  3036. case ACB_ADAPTER_TYPE_D:
  3037. dma_coherent_handle = acb->dma_coherent_handle2;
  3038. break;
  3039. default:
  3040. dma_coherent_handle = acb->dma_coherent_handle;
  3041. break;
  3042. }
  3043. cdb_phyaddr = lower_32_bits(dma_coherent_handle);
  3044. cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
  3045. acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
  3046. /*
  3047. ***********************************************************************
  3048. ** if adapter type B, set window of "post command Q"
  3049. ***********************************************************************
  3050. */
  3051. switch (acb->adapter_type) {
  3052. case ACB_ADAPTER_TYPE_A: {
  3053. if (cdb_phyaddr_hi32 != 0) {
  3054. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3055. writel(ARCMSR_SIGNATURE_SET_CONFIG, \
  3056. &reg->message_rwbuffer[0]);
  3057. writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
  3058. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
  3059. &reg->inbound_msgaddr0);
  3060. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3061. printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
  3062. part physical address timeout\n",
  3063. acb->host->host_no);
  3064. return 1;
  3065. }
  3066. }
  3067. }
  3068. break;
  3069. case ACB_ADAPTER_TYPE_B: {
  3070. uint32_t __iomem *rwbuffer;
  3071. struct MessageUnit_B *reg = acb->pmuB;
  3072. reg->postq_index = 0;
  3073. reg->doneq_index = 0;
  3074. writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
  3075. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3076. printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
  3077. acb->host->host_no);
  3078. return 1;
  3079. }
  3080. rwbuffer = reg->message_rwbuffer;
  3081. /* driver "set config" signature */
  3082. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3083. /* normal should be zero */
  3084. writel(cdb_phyaddr_hi32, rwbuffer++);
  3085. /* postQ size (256 + 8)*4 */
  3086. writel(cdb_phyaddr, rwbuffer++);
  3087. /* doneQ size (256 + 8)*4 */
  3088. writel(cdb_phyaddr + 1056, rwbuffer++);
  3089. /* ccb maxQ size must be --> [(256 + 8)*4]*/
  3090. writel(1056, rwbuffer);
  3091. writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
  3092. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3093. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3094. timeout \n",acb->host->host_no);
  3095. return 1;
  3096. }
  3097. writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
  3098. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3099. pr_err("arcmsr%d: can't set driver mode.\n",
  3100. acb->host->host_no);
  3101. return 1;
  3102. }
  3103. }
  3104. break;
  3105. case ACB_ADAPTER_TYPE_C: {
  3106. if (cdb_phyaddr_hi32 != 0) {
  3107. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3108. printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
  3109. acb->adapter_index, cdb_phyaddr_hi32);
  3110. writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
  3111. writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
  3112. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
  3113. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3114. if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
  3115. printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
  3116. timeout \n", acb->host->host_no);
  3117. return 1;
  3118. }
  3119. }
  3120. }
  3121. break;
  3122. case ACB_ADAPTER_TYPE_D: {
  3123. uint32_t __iomem *rwbuffer;
  3124. struct MessageUnit_D *reg = acb->pmuD;
  3125. reg->postq_index = 0;
  3126. reg->doneq_index = 0;
  3127. rwbuffer = reg->msgcode_rwbuffer;
  3128. writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
  3129. writel(cdb_phyaddr_hi32, rwbuffer++);
  3130. writel(cdb_phyaddr, rwbuffer++);
  3131. writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
  3132. sizeof(struct InBound_SRB)), rwbuffer++);
  3133. writel(0x100, rwbuffer);
  3134. writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
  3135. if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
  3136. pr_notice("arcmsr%d: 'set command Q window' timeout\n",
  3137. acb->host->host_no);
  3138. return 1;
  3139. }
  3140. }
  3141. break;
  3142. }
  3143. return 0;
  3144. }
  3145. static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
  3146. {
  3147. uint32_t firmware_state = 0;
  3148. switch (acb->adapter_type) {
  3149. case ACB_ADAPTER_TYPE_A: {
  3150. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3151. do {
  3152. firmware_state = readl(&reg->outbound_msgaddr1);
  3153. } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
  3154. }
  3155. break;
  3156. case ACB_ADAPTER_TYPE_B: {
  3157. struct MessageUnit_B *reg = acb->pmuB;
  3158. do {
  3159. firmware_state = readl(reg->iop2drv_doorbell);
  3160. } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
  3161. writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
  3162. }
  3163. break;
  3164. case ACB_ADAPTER_TYPE_C: {
  3165. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3166. do {
  3167. firmware_state = readl(&reg->outbound_msgaddr1);
  3168. } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
  3169. }
  3170. break;
  3171. case ACB_ADAPTER_TYPE_D: {
  3172. struct MessageUnit_D *reg = acb->pmuD;
  3173. do {
  3174. firmware_state = readl(reg->outbound_msgaddr1);
  3175. } while ((firmware_state &
  3176. ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
  3177. }
  3178. break;
  3179. }
  3180. }
  3181. static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb)
  3182. {
  3183. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3184. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  3185. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3186. return;
  3187. } else {
  3188. acb->fw_flag = FW_NORMAL;
  3189. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
  3190. atomic_set(&acb->rq_map_token, 16);
  3191. }
  3192. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  3193. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3194. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3195. return;
  3196. }
  3197. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3198. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3199. }
  3200. return;
  3201. }
  3202. static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb)
  3203. {
  3204. struct MessageUnit_B *reg = acb->pmuB;
  3205. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
  3206. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3207. return;
  3208. } else {
  3209. acb->fw_flag = FW_NORMAL;
  3210. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  3211. atomic_set(&acb->rq_map_token, 16);
  3212. }
  3213. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  3214. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3215. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3216. return;
  3217. }
  3218. writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
  3219. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3220. }
  3221. return;
  3222. }
  3223. static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb)
  3224. {
  3225. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3226. if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
  3227. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3228. return;
  3229. } else {
  3230. acb->fw_flag = FW_NORMAL;
  3231. if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
  3232. atomic_set(&acb->rq_map_token, 16);
  3233. }
  3234. atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
  3235. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3236. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3237. return;
  3238. }
  3239. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
  3240. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
  3241. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3242. }
  3243. return;
  3244. }
  3245. static void arcmsr_hbaD_request_device_map(struct AdapterControlBlock *acb)
  3246. {
  3247. struct MessageUnit_D *reg = acb->pmuD;
  3248. if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
  3249. ((acb->acb_flags & ACB_F_BUS_RESET) != 0) ||
  3250. ((acb->acb_flags & ACB_F_ABORT) != 0)) {
  3251. mod_timer(&acb->eternal_timer,
  3252. jiffies + msecs_to_jiffies(6 * HZ));
  3253. } else {
  3254. acb->fw_flag = FW_NORMAL;
  3255. if (atomic_read(&acb->ante_token_value) ==
  3256. atomic_read(&acb->rq_map_token)) {
  3257. atomic_set(&acb->rq_map_token, 16);
  3258. }
  3259. atomic_set(&acb->ante_token_value,
  3260. atomic_read(&acb->rq_map_token));
  3261. if (atomic_dec_and_test(&acb->rq_map_token)) {
  3262. mod_timer(&acb->eternal_timer, jiffies +
  3263. msecs_to_jiffies(6 * HZ));
  3264. return;
  3265. }
  3266. writel(ARCMSR_INBOUND_MESG0_GET_CONFIG,
  3267. reg->inbound_msgaddr0);
  3268. mod_timer(&acb->eternal_timer, jiffies +
  3269. msecs_to_jiffies(6 * HZ));
  3270. }
  3271. }
  3272. static void arcmsr_request_device_map(unsigned long pacb)
  3273. {
  3274. struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
  3275. switch (acb->adapter_type) {
  3276. case ACB_ADAPTER_TYPE_A: {
  3277. arcmsr_hbaA_request_device_map(acb);
  3278. }
  3279. break;
  3280. case ACB_ADAPTER_TYPE_B: {
  3281. arcmsr_hbaB_request_device_map(acb);
  3282. }
  3283. break;
  3284. case ACB_ADAPTER_TYPE_C: {
  3285. arcmsr_hbaC_request_device_map(acb);
  3286. }
  3287. break;
  3288. case ACB_ADAPTER_TYPE_D:
  3289. arcmsr_hbaD_request_device_map(acb);
  3290. break;
  3291. }
  3292. }
  3293. static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
  3294. {
  3295. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3296. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3297. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
  3298. if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
  3299. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3300. rebulid' timeout \n", acb->host->host_no);
  3301. }
  3302. }
  3303. static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
  3304. {
  3305. struct MessageUnit_B *reg = acb->pmuB;
  3306. acb->acb_flags |= ACB_F_MSG_START_BGRB;
  3307. writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
  3308. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3309. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3310. rebulid' timeout \n",acb->host->host_no);
  3311. }
  3312. }
  3313. static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
  3314. {
  3315. struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
  3316. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3317. writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
  3318. writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
  3319. if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
  3320. printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
  3321. rebulid' timeout \n", pACB->host->host_no);
  3322. }
  3323. return;
  3324. }
  3325. static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
  3326. {
  3327. struct MessageUnit_D *pmu = pACB->pmuD;
  3328. pACB->acb_flags |= ACB_F_MSG_START_BGRB;
  3329. writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
  3330. if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
  3331. pr_notice("arcmsr%d: wait 'start adapter "
  3332. "background rebulid' timeout\n", pACB->host->host_no);
  3333. }
  3334. }
  3335. static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
  3336. {
  3337. switch (acb->adapter_type) {
  3338. case ACB_ADAPTER_TYPE_A:
  3339. arcmsr_hbaA_start_bgrb(acb);
  3340. break;
  3341. case ACB_ADAPTER_TYPE_B:
  3342. arcmsr_hbaB_start_bgrb(acb);
  3343. break;
  3344. case ACB_ADAPTER_TYPE_C:
  3345. arcmsr_hbaC_start_bgrb(acb);
  3346. break;
  3347. case ACB_ADAPTER_TYPE_D:
  3348. arcmsr_hbaD_start_bgrb(acb);
  3349. break;
  3350. }
  3351. }
  3352. static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
  3353. {
  3354. switch (acb->adapter_type) {
  3355. case ACB_ADAPTER_TYPE_A: {
  3356. struct MessageUnit_A __iomem *reg = acb->pmuA;
  3357. uint32_t outbound_doorbell;
  3358. /* empty doorbell Qbuffer if door bell ringed */
  3359. outbound_doorbell = readl(&reg->outbound_doorbell);
  3360. /*clear doorbell interrupt */
  3361. writel(outbound_doorbell, &reg->outbound_doorbell);
  3362. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  3363. }
  3364. break;
  3365. case ACB_ADAPTER_TYPE_B: {
  3366. struct MessageUnit_B *reg = acb->pmuB;
  3367. /*clear interrupt and message state*/
  3368. writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
  3369. writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
  3370. /* let IOP know data has been read */
  3371. }
  3372. break;
  3373. case ACB_ADAPTER_TYPE_C: {
  3374. struct MessageUnit_C __iomem *reg = acb->pmuC;
  3375. uint32_t outbound_doorbell, i;
  3376. /* empty doorbell Qbuffer if door bell ringed */
  3377. outbound_doorbell = readl(&reg->outbound_doorbell);
  3378. writel(outbound_doorbell, &reg->outbound_doorbell_clear);
  3379. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
  3380. for (i = 0; i < 200; i++) {
  3381. msleep(20);
  3382. outbound_doorbell = readl(&reg->outbound_doorbell);
  3383. if (outbound_doorbell &
  3384. ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
  3385. writel(outbound_doorbell,
  3386. &reg->outbound_doorbell_clear);
  3387. writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
  3388. &reg->inbound_doorbell);
  3389. } else
  3390. break;
  3391. }
  3392. }
  3393. break;
  3394. case ACB_ADAPTER_TYPE_D: {
  3395. struct MessageUnit_D *reg = acb->pmuD;
  3396. uint32_t outbound_doorbell, i;
  3397. /* empty doorbell Qbuffer if door bell ringed */
  3398. outbound_doorbell = readl(reg->outbound_doorbell);
  3399. writel(outbound_doorbell, reg->outbound_doorbell);
  3400. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  3401. reg->inbound_doorbell);
  3402. for (i = 0; i < 200; i++) {
  3403. msleep(20);
  3404. outbound_doorbell = readl(reg->outbound_doorbell);
  3405. if (outbound_doorbell &
  3406. ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
  3407. writel(outbound_doorbell,
  3408. reg->outbound_doorbell);
  3409. writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
  3410. reg->inbound_doorbell);
  3411. } else
  3412. break;
  3413. }
  3414. }
  3415. break;
  3416. }
  3417. }
  3418. static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
  3419. {
  3420. switch (acb->adapter_type) {
  3421. case ACB_ADAPTER_TYPE_A:
  3422. return;
  3423. case ACB_ADAPTER_TYPE_B:
  3424. {
  3425. struct MessageUnit_B *reg = acb->pmuB;
  3426. writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
  3427. if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
  3428. printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
  3429. return;
  3430. }
  3431. }
  3432. break;
  3433. case ACB_ADAPTER_TYPE_C:
  3434. return;
  3435. }
  3436. return;
  3437. }
  3438. static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
  3439. {
  3440. uint8_t value[64];
  3441. int i, count = 0;
  3442. struct MessageUnit_A __iomem *pmuA = acb->pmuA;
  3443. struct MessageUnit_C __iomem *pmuC = acb->pmuC;
  3444. struct MessageUnit_D *pmuD = acb->pmuD;
  3445. /* backup pci config data */
  3446. printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
  3447. for (i = 0; i < 64; i++) {
  3448. pci_read_config_byte(acb->pdev, i, &value[i]);
  3449. }
  3450. /* hardware reset signal */
  3451. if ((acb->dev_id == 0x1680)) {
  3452. writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
  3453. } else if ((acb->dev_id == 0x1880)) {
  3454. do {
  3455. count++;
  3456. writel(0xF, &pmuC->write_sequence);
  3457. writel(0x4, &pmuC->write_sequence);
  3458. writel(0xB, &pmuC->write_sequence);
  3459. writel(0x2, &pmuC->write_sequence);
  3460. writel(0x7, &pmuC->write_sequence);
  3461. writel(0xD, &pmuC->write_sequence);
  3462. } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
  3463. writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
  3464. } else if ((acb->dev_id == 0x1214)) {
  3465. writel(0x20, pmuD->reset_request);
  3466. } else {
  3467. pci_write_config_byte(acb->pdev, 0x84, 0x20);
  3468. }
  3469. msleep(2000);
  3470. /* write back pci config data */
  3471. for (i = 0; i < 64; i++) {
  3472. pci_write_config_byte(acb->pdev, i, value[i]);
  3473. }
  3474. msleep(1000);
  3475. return;
  3476. }
  3477. static void arcmsr_iop_init(struct AdapterControlBlock *acb)
  3478. {
  3479. uint32_t intmask_org;
  3480. /* disable all outbound interrupt */
  3481. intmask_org = arcmsr_disable_outbound_ints(acb);
  3482. arcmsr_wait_firmware_ready(acb);
  3483. arcmsr_iop_confirm(acb);
  3484. /*start background rebuild*/
  3485. arcmsr_start_adapter_bgrb(acb);
  3486. /* empty doorbell Qbuffer if door bell ringed */
  3487. arcmsr_clear_doorbell_queue_buffer(acb);
  3488. arcmsr_enable_eoi_mode(acb);
  3489. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3490. arcmsr_enable_outbound_ints(acb, intmask_org);
  3491. acb->acb_flags |= ACB_F_IOP_INITED;
  3492. }
  3493. static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
  3494. {
  3495. struct CommandControlBlock *ccb;
  3496. uint32_t intmask_org;
  3497. uint8_t rtnval = 0x00;
  3498. int i = 0;
  3499. unsigned long flags;
  3500. if (atomic_read(&acb->ccboutstandingcount) != 0) {
  3501. /* disable all outbound interrupt */
  3502. intmask_org = arcmsr_disable_outbound_ints(acb);
  3503. /* talk to iop 331 outstanding command aborted */
  3504. rtnval = arcmsr_abort_allcmd(acb);
  3505. /* clear all outbound posted Q */
  3506. arcmsr_done4abort_postqueue(acb);
  3507. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  3508. ccb = acb->pccb_pool[i];
  3509. if (ccb->startdone == ARCMSR_CCB_START) {
  3510. scsi_dma_unmap(ccb->pcmd);
  3511. ccb->startdone = ARCMSR_CCB_DONE;
  3512. ccb->ccb_flags = 0;
  3513. spin_lock_irqsave(&acb->ccblist_lock, flags);
  3514. list_add_tail(&ccb->list, &acb->ccb_free_list);
  3515. spin_unlock_irqrestore(&acb->ccblist_lock, flags);
  3516. }
  3517. }
  3518. atomic_set(&acb->ccboutstandingcount, 0);
  3519. /* enable all outbound interrupt */
  3520. arcmsr_enable_outbound_ints(acb, intmask_org);
  3521. return rtnval;
  3522. }
  3523. return rtnval;
  3524. }
  3525. static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
  3526. {
  3527. struct AdapterControlBlock *acb;
  3528. uint32_t intmask_org, outbound_doorbell;
  3529. int retry_count = 0;
  3530. int rtn = FAILED;
  3531. acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
  3532. printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
  3533. acb->num_resets++;
  3534. switch(acb->adapter_type){
  3535. case ACB_ADAPTER_TYPE_A:{
  3536. if (acb->acb_flags & ACB_F_BUS_RESET){
  3537. long timeout;
  3538. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  3539. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  3540. if (timeout) {
  3541. return SUCCESS;
  3542. }
  3543. }
  3544. acb->acb_flags |= ACB_F_BUS_RESET;
  3545. if (!arcmsr_iop_reset(acb)) {
  3546. struct MessageUnit_A __iomem *reg;
  3547. reg = acb->pmuA;
  3548. arcmsr_hardware_reset(acb);
  3549. acb->acb_flags &= ~ACB_F_IOP_INITED;
  3550. sleep_again:
  3551. ssleep(ARCMSR_SLEEPTIME);
  3552. if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
  3553. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
  3554. if (retry_count > ARCMSR_RETRYCOUNT) {
  3555. acb->fw_flag = FW_DEADLOCK;
  3556. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
  3557. return FAILED;
  3558. }
  3559. retry_count++;
  3560. goto sleep_again;
  3561. }
  3562. acb->acb_flags |= ACB_F_IOP_INITED;
  3563. /* disable all outbound interrupt */
  3564. intmask_org = arcmsr_disable_outbound_ints(acb);
  3565. arcmsr_get_firmware_spec(acb);
  3566. arcmsr_start_adapter_bgrb(acb);
  3567. /* clear Qbuffer if door bell ringed */
  3568. outbound_doorbell = readl(&reg->outbound_doorbell);
  3569. writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
  3570. writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
  3571. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3572. arcmsr_enable_outbound_ints(acb, intmask_org);
  3573. atomic_set(&acb->rq_map_token, 16);
  3574. atomic_set(&acb->ante_token_value, 16);
  3575. acb->fw_flag = FW_NORMAL;
  3576. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3577. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3578. rtn = SUCCESS;
  3579. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  3580. } else {
  3581. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3582. atomic_set(&acb->rq_map_token, 16);
  3583. atomic_set(&acb->ante_token_value, 16);
  3584. acb->fw_flag = FW_NORMAL;
  3585. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  3586. rtn = SUCCESS;
  3587. }
  3588. break;
  3589. }
  3590. case ACB_ADAPTER_TYPE_B:{
  3591. acb->acb_flags |= ACB_F_BUS_RESET;
  3592. if (!arcmsr_iop_reset(acb)) {
  3593. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3594. rtn = FAILED;
  3595. } else {
  3596. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3597. atomic_set(&acb->rq_map_token, 16);
  3598. atomic_set(&acb->ante_token_value, 16);
  3599. acb->fw_flag = FW_NORMAL;
  3600. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3601. rtn = SUCCESS;
  3602. }
  3603. break;
  3604. }
  3605. case ACB_ADAPTER_TYPE_C:{
  3606. if (acb->acb_flags & ACB_F_BUS_RESET) {
  3607. long timeout;
  3608. printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
  3609. timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
  3610. if (timeout) {
  3611. return SUCCESS;
  3612. }
  3613. }
  3614. acb->acb_flags |= ACB_F_BUS_RESET;
  3615. if (!arcmsr_iop_reset(acb)) {
  3616. struct MessageUnit_C __iomem *reg;
  3617. reg = acb->pmuC;
  3618. arcmsr_hardware_reset(acb);
  3619. acb->acb_flags &= ~ACB_F_IOP_INITED;
  3620. sleep:
  3621. ssleep(ARCMSR_SLEEPTIME);
  3622. if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
  3623. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
  3624. if (retry_count > ARCMSR_RETRYCOUNT) {
  3625. acb->fw_flag = FW_DEADLOCK;
  3626. printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
  3627. return FAILED;
  3628. }
  3629. retry_count++;
  3630. goto sleep;
  3631. }
  3632. acb->acb_flags |= ACB_F_IOP_INITED;
  3633. /* disable all outbound interrupt */
  3634. intmask_org = arcmsr_disable_outbound_ints(acb);
  3635. arcmsr_get_firmware_spec(acb);
  3636. arcmsr_start_adapter_bgrb(acb);
  3637. /* clear Qbuffer if door bell ringed */
  3638. arcmsr_clear_doorbell_queue_buffer(acb);
  3639. /* enable outbound Post Queue,outbound doorbell Interrupt */
  3640. arcmsr_enable_outbound_ints(acb, intmask_org);
  3641. atomic_set(&acb->rq_map_token, 16);
  3642. atomic_set(&acb->ante_token_value, 16);
  3643. acb->fw_flag = FW_NORMAL;
  3644. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
  3645. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3646. rtn = SUCCESS;
  3647. printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
  3648. } else {
  3649. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3650. atomic_set(&acb->rq_map_token, 16);
  3651. atomic_set(&acb->ante_token_value, 16);
  3652. acb->fw_flag = FW_NORMAL;
  3653. mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
  3654. rtn = SUCCESS;
  3655. }
  3656. break;
  3657. }
  3658. case ACB_ADAPTER_TYPE_D: {
  3659. if (acb->acb_flags & ACB_F_BUS_RESET) {
  3660. long timeout;
  3661. pr_notice("arcmsr: there is an bus reset"
  3662. " eh proceeding.......\n");
  3663. timeout = wait_event_timeout(wait_q, (acb->acb_flags
  3664. & ACB_F_BUS_RESET) == 0, 220 * HZ);
  3665. if (timeout)
  3666. return SUCCESS;
  3667. }
  3668. acb->acb_flags |= ACB_F_BUS_RESET;
  3669. if (!arcmsr_iop_reset(acb)) {
  3670. struct MessageUnit_D *reg;
  3671. reg = acb->pmuD;
  3672. arcmsr_hardware_reset(acb);
  3673. acb->acb_flags &= ~ACB_F_IOP_INITED;
  3674. nap:
  3675. ssleep(ARCMSR_SLEEPTIME);
  3676. if ((readl(reg->sample_at_reset) & 0x80) != 0) {
  3677. pr_err("arcmsr%d: waiting for "
  3678. "hw bus reset return, retry=%d\n",
  3679. acb->host->host_no, retry_count);
  3680. if (retry_count > ARCMSR_RETRYCOUNT) {
  3681. acb->fw_flag = FW_DEADLOCK;
  3682. pr_err("arcmsr%d: waiting for hw bus"
  3683. " reset return, "
  3684. "RETRY TERMINATED!!\n",
  3685. acb->host->host_no);
  3686. return FAILED;
  3687. }
  3688. retry_count++;
  3689. goto nap;
  3690. }
  3691. acb->acb_flags |= ACB_F_IOP_INITED;
  3692. /* disable all outbound interrupt */
  3693. intmask_org = arcmsr_disable_outbound_ints(acb);
  3694. arcmsr_get_firmware_spec(acb);
  3695. arcmsr_start_adapter_bgrb(acb);
  3696. arcmsr_clear_doorbell_queue_buffer(acb);
  3697. arcmsr_enable_outbound_ints(acb, intmask_org);
  3698. atomic_set(&acb->rq_map_token, 16);
  3699. atomic_set(&acb->ante_token_value, 16);
  3700. acb->fw_flag = FW_NORMAL;
  3701. mod_timer(&acb->eternal_timer,
  3702. jiffies + msecs_to_jiffies(6 * HZ));
  3703. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3704. rtn = SUCCESS;
  3705. pr_err("arcmsr: scsi bus reset "
  3706. "eh returns with success\n");
  3707. } else {
  3708. acb->acb_flags &= ~ACB_F_BUS_RESET;
  3709. atomic_set(&acb->rq_map_token, 16);
  3710. atomic_set(&acb->ante_token_value, 16);
  3711. acb->fw_flag = FW_NORMAL;
  3712. mod_timer(&acb->eternal_timer,
  3713. jiffies + msecs_to_jiffies(6 * HZ));
  3714. rtn = SUCCESS;
  3715. }
  3716. break;
  3717. }
  3718. }
  3719. return rtn;
  3720. }
  3721. static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
  3722. struct CommandControlBlock *ccb)
  3723. {
  3724. int rtn;
  3725. rtn = arcmsr_polling_ccbdone(acb, ccb);
  3726. return rtn;
  3727. }
  3728. static int arcmsr_abort(struct scsi_cmnd *cmd)
  3729. {
  3730. struct AdapterControlBlock *acb =
  3731. (struct AdapterControlBlock *)cmd->device->host->hostdata;
  3732. int i = 0;
  3733. int rtn = FAILED;
  3734. uint32_t intmask_org;
  3735. printk(KERN_NOTICE
  3736. "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
  3737. acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
  3738. acb->acb_flags |= ACB_F_ABORT;
  3739. acb->num_aborts++;
  3740. /*
  3741. ************************************************
  3742. ** the all interrupt service routine is locked
  3743. ** we need to handle it as soon as possible and exit
  3744. ************************************************
  3745. */
  3746. if (!atomic_read(&acb->ccboutstandingcount)) {
  3747. acb->acb_flags &= ~ACB_F_ABORT;
  3748. return rtn;
  3749. }
  3750. intmask_org = arcmsr_disable_outbound_ints(acb);
  3751. for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
  3752. struct CommandControlBlock *ccb = acb->pccb_pool[i];
  3753. if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
  3754. ccb->startdone = ARCMSR_CCB_ABORTED;
  3755. rtn = arcmsr_abort_one_cmd(acb, ccb);
  3756. break;
  3757. }
  3758. }
  3759. acb->acb_flags &= ~ACB_F_ABORT;
  3760. arcmsr_enable_outbound_ints(acb, intmask_org);
  3761. return rtn;
  3762. }
  3763. static const char *arcmsr_info(struct Scsi_Host *host)
  3764. {
  3765. struct AdapterControlBlock *acb =
  3766. (struct AdapterControlBlock *) host->hostdata;
  3767. static char buf[256];
  3768. char *type;
  3769. int raid6 = 1;
  3770. switch (acb->pdev->device) {
  3771. case PCI_DEVICE_ID_ARECA_1110:
  3772. case PCI_DEVICE_ID_ARECA_1200:
  3773. case PCI_DEVICE_ID_ARECA_1202:
  3774. case PCI_DEVICE_ID_ARECA_1210:
  3775. raid6 = 0;
  3776. /*FALLTHRU*/
  3777. case PCI_DEVICE_ID_ARECA_1120:
  3778. case PCI_DEVICE_ID_ARECA_1130:
  3779. case PCI_DEVICE_ID_ARECA_1160:
  3780. case PCI_DEVICE_ID_ARECA_1170:
  3781. case PCI_DEVICE_ID_ARECA_1201:
  3782. case PCI_DEVICE_ID_ARECA_1220:
  3783. case PCI_DEVICE_ID_ARECA_1230:
  3784. case PCI_DEVICE_ID_ARECA_1260:
  3785. case PCI_DEVICE_ID_ARECA_1270:
  3786. case PCI_DEVICE_ID_ARECA_1280:
  3787. type = "SATA";
  3788. break;
  3789. case PCI_DEVICE_ID_ARECA_1214:
  3790. case PCI_DEVICE_ID_ARECA_1380:
  3791. case PCI_DEVICE_ID_ARECA_1381:
  3792. case PCI_DEVICE_ID_ARECA_1680:
  3793. case PCI_DEVICE_ID_ARECA_1681:
  3794. case PCI_DEVICE_ID_ARECA_1880:
  3795. type = "SAS/SATA";
  3796. break;
  3797. default:
  3798. type = "unknown";
  3799. raid6 = 0;
  3800. break;
  3801. }
  3802. sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
  3803. type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
  3804. return buf;
  3805. }