parport_serial.c 20 KB

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  1. /*
  2. * Support for common PCI multi-I/O cards (which is most of them)
  3. *
  4. * Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. *
  12. * Multi-function PCI cards are supposed to present separate logical
  13. * devices on the bus. A common thing to do seems to be to just use
  14. * one logical device with lots of base address registers for both
  15. * parallel ports and serial ports. This driver is for dealing with
  16. * that.
  17. *
  18. */
  19. #include <linux/types.h>
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/slab.h>
  23. #include <linux/pci.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/parport.h>
  26. #include <linux/parport_pc.h>
  27. #include <linux/8250_pci.h>
  28. enum parport_pc_pci_cards {
  29. titan_110l = 0,
  30. titan_210l,
  31. netmos_9xx5_combo,
  32. netmos_9855,
  33. netmos_9855_2p,
  34. netmos_9900,
  35. netmos_9900_2p,
  36. netmos_99xx_1p,
  37. avlab_1s1p,
  38. avlab_1s2p,
  39. avlab_2s1p,
  40. siig_1s1p_10x,
  41. siig_2s1p_10x,
  42. siig_2p1s_20x,
  43. siig_1s1p_20x,
  44. siig_2s1p_20x,
  45. timedia_4078a,
  46. timedia_4079h,
  47. timedia_4085h,
  48. timedia_4088a,
  49. timedia_4089a,
  50. timedia_4095a,
  51. timedia_4096a,
  52. timedia_4078u,
  53. timedia_4079a,
  54. timedia_4085u,
  55. timedia_4079r,
  56. timedia_4079s,
  57. timedia_4079d,
  58. timedia_4079e,
  59. timedia_4079f,
  60. timedia_9079a,
  61. timedia_9079b,
  62. timedia_9079c,
  63. wch_ch353_1s1p,
  64. wch_ch353_2s1p,
  65. sunix_2s1p,
  66. };
  67. /* each element directly indexed from enum list, above */
  68. struct parport_pc_pci {
  69. int numports;
  70. struct { /* BAR (base address registers) numbers in the config
  71. space header */
  72. int lo;
  73. int hi; /* -1 if not there, >6 for offset-method (max
  74. BAR is 6) */
  75. } addr[4];
  76. /* If set, this is called immediately after pci_enable_device.
  77. * If it returns non-zero, no probing will take place and the
  78. * ports will not be used. */
  79. int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
  80. int autoirq, int autodma);
  81. /* If set, this is called after probing for ports. If 'failed'
  82. * is non-zero we couldn't use any of the ports. */
  83. void (*postinit_hook) (struct pci_dev *pdev,
  84. struct parport_pc_pci *card, int failed);
  85. };
  86. static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
  87. int autoirq, int autodma)
  88. {
  89. /* the rule described below doesn't hold for this device */
  90. if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
  91. dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  92. dev->subsystem_device == 0x0299)
  93. return -ENODEV;
  94. if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
  95. par->numports = 1;
  96. } else {
  97. /*
  98. * Netmos uses the subdevice ID to indicate the number of parallel
  99. * and serial ports. The form is 0x00PS, where <P> is the number of
  100. * parallel ports and <S> is the number of serial ports.
  101. */
  102. par->numports = (dev->subsystem_device & 0xf0) >> 4;
  103. if (par->numports > ARRAY_SIZE(par->addr))
  104. par->numports = ARRAY_SIZE(par->addr);
  105. }
  106. return 0;
  107. }
  108. static struct parport_pc_pci cards[] = {
  109. /* titan_110l */ { 1, { { 3, -1 }, } },
  110. /* titan_210l */ { 1, { { 3, -1 }, } },
  111. /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
  112. /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
  113. /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
  114. /* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
  115. /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
  116. /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
  117. /* avlab_1s1p */ { 1, { { 1, 2}, } },
  118. /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
  119. /* avlab_2s1p */ { 1, { { 2, 3}, } },
  120. /* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
  121. /* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
  122. /* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
  123. /* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
  124. /* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
  125. /* timedia_4078a */ { 1, { { 2, -1 }, } },
  126. /* timedia_4079h */ { 1, { { 2, 3 }, } },
  127. /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
  128. /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  129. /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  130. /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  131. /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  132. /* timedia_4078u */ { 1, { { 2, -1 }, } },
  133. /* timedia_4079a */ { 1, { { 2, 3 }, } },
  134. /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
  135. /* timedia_4079r */ { 1, { { 2, 3 }, } },
  136. /* timedia_4079s */ { 1, { { 2, 3 }, } },
  137. /* timedia_4079d */ { 1, { { 2, 3 }, } },
  138. /* timedia_4079e */ { 1, { { 2, 3 }, } },
  139. /* timedia_4079f */ { 1, { { 2, 3 }, } },
  140. /* timedia_9079a */ { 1, { { 2, 3 }, } },
  141. /* timedia_9079b */ { 1, { { 2, 3 }, } },
  142. /* timedia_9079c */ { 1, { { 2, 3 }, } },
  143. /* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
  144. /* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
  145. /* sunix_2s1p */ { 1, { { 3, -1 }, } },
  146. };
  147. #define PCI_VENDOR_ID_SUNIX 0x1fd4
  148. #define PCI_DEVICE_ID_SUNIX_1999 0x1999
  149. static struct pci_device_id parport_serial_pci_tbl[] = {
  150. /* PCI cards */
  151. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
  152. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
  153. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
  154. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
  155. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
  156. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  157. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
  158. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  159. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
  160. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  161. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
  162. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  163. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  164. 0x1000, 0x0020, 0, 0, netmos_9855_2p },
  165. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  166. 0x1000, 0x0022, 0, 0, netmos_9855_2p },
  167. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  168. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
  169. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  170. 0xA000, 0x3011, 0, 0, netmos_9900 },
  171. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  172. 0xA000, 0x3012, 0, 0, netmos_9900 },
  173. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  174. 0xA000, 0x3020, 0, 0, netmos_9900_2p },
  175. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  176. 0xA000, 0x2000, 0, 0, netmos_99xx_1p },
  177. /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
  178. { PCI_VENDOR_ID_AFAVLAB, 0x2110,
  179. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  180. { PCI_VENDOR_ID_AFAVLAB, 0x2111,
  181. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  182. { PCI_VENDOR_ID_AFAVLAB, 0x2112,
  183. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  184. { PCI_VENDOR_ID_AFAVLAB, 0x2140,
  185. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  186. { PCI_VENDOR_ID_AFAVLAB, 0x2141,
  187. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  188. { PCI_VENDOR_ID_AFAVLAB, 0x2142,
  189. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  190. { PCI_VENDOR_ID_AFAVLAB, 0x2160,
  191. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  192. { PCI_VENDOR_ID_AFAVLAB, 0x2161,
  193. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  194. { PCI_VENDOR_ID_AFAVLAB, 0x2162,
  195. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  196. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
  197. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  198. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
  199. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  200. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
  201. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  202. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
  203. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  204. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
  205. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  206. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
  207. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  208. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
  209. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  210. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
  211. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  212. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
  213. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  214. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
  215. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  216. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
  217. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  218. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
  219. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  220. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
  221. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  222. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
  223. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  224. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
  225. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  226. /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
  227. { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
  228. { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
  229. { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
  230. { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
  231. { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
  232. { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
  233. { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
  234. { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
  235. { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
  236. { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
  237. { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
  238. { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
  239. { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
  240. { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
  241. { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
  242. { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
  243. { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
  244. { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
  245. /* WCH CARDS */
  246. { 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
  247. { 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
  248. /*
  249. * More SUNIX variations. At least one of these has part number
  250. * '5079A but subdevice 0x102. That board reports 0x0708 as
  251. * its PCI Class.
  252. */
  253. { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
  254. 0x0102, 0, 0, sunix_2s1p },
  255. { 0, } /* terminate list */
  256. };
  257. MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
  258. /*
  259. * This table describes the serial "geometry" of these boards. Any
  260. * quirks for these can be found in drivers/serial/8250_pci.c
  261. *
  262. * Cards not tested are marked n/t
  263. * If you have one of these cards and it works for you, please tell me..
  264. */
  265. static struct pciserial_board pci_parport_serial_boards[] = {
  266. [titan_110l] = {
  267. .flags = FL_BASE1 | FL_BASE_BARS,
  268. .num_ports = 1,
  269. .base_baud = 921600,
  270. .uart_offset = 8,
  271. },
  272. [titan_210l] = {
  273. .flags = FL_BASE1 | FL_BASE_BARS,
  274. .num_ports = 2,
  275. .base_baud = 921600,
  276. .uart_offset = 8,
  277. },
  278. [netmos_9xx5_combo] = {
  279. .flags = FL_BASE0 | FL_BASE_BARS,
  280. .num_ports = 1,
  281. .base_baud = 115200,
  282. .uart_offset = 8,
  283. },
  284. [netmos_9855] = {
  285. .flags = FL_BASE2 | FL_BASE_BARS,
  286. .num_ports = 1,
  287. .base_baud = 115200,
  288. .uart_offset = 8,
  289. },
  290. [netmos_9855_2p] = {
  291. .flags = FL_BASE4 | FL_BASE_BARS,
  292. .num_ports = 1,
  293. .base_baud = 115200,
  294. .uart_offset = 8,
  295. },
  296. [netmos_9900] = { /* n/t */
  297. .flags = FL_BASE0 | FL_BASE_BARS,
  298. .num_ports = 1,
  299. .base_baud = 115200,
  300. .uart_offset = 8,
  301. },
  302. [netmos_9900_2p] = { /* parallel only */ /* n/t */
  303. .flags = FL_BASE0,
  304. .num_ports = 0,
  305. .base_baud = 115200,
  306. .uart_offset = 8,
  307. },
  308. [netmos_99xx_1p] = { /* parallel only */ /* n/t */
  309. .flags = FL_BASE0,
  310. .num_ports = 0,
  311. .base_baud = 115200,
  312. .uart_offset = 8,
  313. },
  314. [avlab_1s1p] = { /* n/t */
  315. .flags = FL_BASE0 | FL_BASE_BARS,
  316. .num_ports = 1,
  317. .base_baud = 115200,
  318. .uart_offset = 8,
  319. },
  320. [avlab_1s2p] = { /* n/t */
  321. .flags = FL_BASE0 | FL_BASE_BARS,
  322. .num_ports = 1,
  323. .base_baud = 115200,
  324. .uart_offset = 8,
  325. },
  326. [avlab_2s1p] = { /* n/t */
  327. .flags = FL_BASE0 | FL_BASE_BARS,
  328. .num_ports = 2,
  329. .base_baud = 115200,
  330. .uart_offset = 8,
  331. },
  332. [siig_1s1p_10x] = {
  333. .flags = FL_BASE2,
  334. .num_ports = 1,
  335. .base_baud = 460800,
  336. .uart_offset = 8,
  337. },
  338. [siig_2s1p_10x] = {
  339. .flags = FL_BASE2,
  340. .num_ports = 1,
  341. .base_baud = 921600,
  342. .uart_offset = 8,
  343. },
  344. [siig_2p1s_20x] = {
  345. .flags = FL_BASE0,
  346. .num_ports = 1,
  347. .base_baud = 921600,
  348. .uart_offset = 8,
  349. },
  350. [siig_1s1p_20x] = {
  351. .flags = FL_BASE0,
  352. .num_ports = 1,
  353. .base_baud = 921600,
  354. .uart_offset = 8,
  355. },
  356. [siig_2s1p_20x] = {
  357. .flags = FL_BASE0,
  358. .num_ports = 1,
  359. .base_baud = 921600,
  360. .uart_offset = 8,
  361. },
  362. [timedia_4078a] = {
  363. .flags = FL_BASE0|FL_BASE_BARS,
  364. .num_ports = 1,
  365. .base_baud = 921600,
  366. .uart_offset = 8,
  367. },
  368. [timedia_4079h] = {
  369. .flags = FL_BASE0|FL_BASE_BARS,
  370. .num_ports = 1,
  371. .base_baud = 921600,
  372. .uart_offset = 8,
  373. },
  374. [timedia_4085h] = {
  375. .flags = FL_BASE0|FL_BASE_BARS,
  376. .num_ports = 1,
  377. .base_baud = 921600,
  378. .uart_offset = 8,
  379. },
  380. [timedia_4088a] = {
  381. .flags = FL_BASE0|FL_BASE_BARS,
  382. .num_ports = 1,
  383. .base_baud = 921600,
  384. .uart_offset = 8,
  385. },
  386. [timedia_4089a] = {
  387. .flags = FL_BASE0|FL_BASE_BARS,
  388. .num_ports = 1,
  389. .base_baud = 921600,
  390. .uart_offset = 8,
  391. },
  392. [timedia_4095a] = {
  393. .flags = FL_BASE0|FL_BASE_BARS,
  394. .num_ports = 1,
  395. .base_baud = 921600,
  396. .uart_offset = 8,
  397. },
  398. [timedia_4096a] = {
  399. .flags = FL_BASE0|FL_BASE_BARS,
  400. .num_ports = 1,
  401. .base_baud = 921600,
  402. .uart_offset = 8,
  403. },
  404. [timedia_4078u] = {
  405. .flags = FL_BASE0|FL_BASE_BARS,
  406. .num_ports = 1,
  407. .base_baud = 921600,
  408. .uart_offset = 8,
  409. },
  410. [timedia_4079a] = {
  411. .flags = FL_BASE0|FL_BASE_BARS,
  412. .num_ports = 1,
  413. .base_baud = 921600,
  414. .uart_offset = 8,
  415. },
  416. [timedia_4085u] = {
  417. .flags = FL_BASE0|FL_BASE_BARS,
  418. .num_ports = 1,
  419. .base_baud = 921600,
  420. .uart_offset = 8,
  421. },
  422. [timedia_4079r] = {
  423. .flags = FL_BASE0|FL_BASE_BARS,
  424. .num_ports = 1,
  425. .base_baud = 921600,
  426. .uart_offset = 8,
  427. },
  428. [timedia_4079s] = {
  429. .flags = FL_BASE0|FL_BASE_BARS,
  430. .num_ports = 1,
  431. .base_baud = 921600,
  432. .uart_offset = 8,
  433. },
  434. [timedia_4079d] = {
  435. .flags = FL_BASE0|FL_BASE_BARS,
  436. .num_ports = 1,
  437. .base_baud = 921600,
  438. .uart_offset = 8,
  439. },
  440. [timedia_4079e] = {
  441. .flags = FL_BASE0|FL_BASE_BARS,
  442. .num_ports = 1,
  443. .base_baud = 921600,
  444. .uart_offset = 8,
  445. },
  446. [timedia_4079f] = {
  447. .flags = FL_BASE0|FL_BASE_BARS,
  448. .num_ports = 1,
  449. .base_baud = 921600,
  450. .uart_offset = 8,
  451. },
  452. [timedia_9079a] = {
  453. .flags = FL_BASE0|FL_BASE_BARS,
  454. .num_ports = 1,
  455. .base_baud = 921600,
  456. .uart_offset = 8,
  457. },
  458. [timedia_9079b] = {
  459. .flags = FL_BASE0|FL_BASE_BARS,
  460. .num_ports = 1,
  461. .base_baud = 921600,
  462. .uart_offset = 8,
  463. },
  464. [timedia_9079c] = {
  465. .flags = FL_BASE0|FL_BASE_BARS,
  466. .num_ports = 1,
  467. .base_baud = 921600,
  468. .uart_offset = 8,
  469. },
  470. [wch_ch353_1s1p] = {
  471. .flags = FL_BASE0|FL_BASE_BARS,
  472. .num_ports = 1,
  473. .base_baud = 115200,
  474. .uart_offset = 8,
  475. },
  476. [wch_ch353_2s1p] = {
  477. .flags = FL_BASE0|FL_BASE_BARS,
  478. .num_ports = 2,
  479. .base_baud = 115200,
  480. .uart_offset = 8,
  481. },
  482. [sunix_2s1p] = {
  483. .flags = FL_BASE0|FL_BASE_BARS,
  484. .num_ports = 2,
  485. .base_baud = 921600,
  486. .uart_offset = 8,
  487. },
  488. };
  489. struct parport_serial_private {
  490. struct serial_private *serial;
  491. int num_par;
  492. struct parport *port[PARPORT_MAX];
  493. struct parport_pc_pci par;
  494. };
  495. /* Register the serial port(s) of a PCI card. */
  496. static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
  497. {
  498. struct parport_serial_private *priv = pci_get_drvdata (dev);
  499. struct pciserial_board *board;
  500. struct serial_private *serial;
  501. board = &pci_parport_serial_boards[id->driver_data];
  502. if (board->num_ports == 0)
  503. return 0;
  504. serial = pciserial_init_ports(dev, board);
  505. if (IS_ERR(serial))
  506. return PTR_ERR(serial);
  507. priv->serial = serial;
  508. return 0;
  509. }
  510. /* Register the parallel port(s) of a PCI card. */
  511. static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
  512. {
  513. struct parport_pc_pci *card;
  514. struct parport_serial_private *priv = pci_get_drvdata (dev);
  515. int n, success = 0;
  516. priv->par = cards[id->driver_data];
  517. card = &priv->par;
  518. if (card->preinit_hook &&
  519. card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
  520. return -ENODEV;
  521. for (n = 0; n < card->numports; n++) {
  522. struct parport *port;
  523. int lo = card->addr[n].lo;
  524. int hi = card->addr[n].hi;
  525. unsigned long io_lo, io_hi;
  526. int irq;
  527. if (priv->num_par == ARRAY_SIZE (priv->port)) {
  528. printk (KERN_WARNING
  529. "parport_serial: %s: only %zu parallel ports "
  530. "supported (%d reported)\n", pci_name (dev),
  531. ARRAY_SIZE(priv->port), card->numports);
  532. break;
  533. }
  534. io_lo = pci_resource_start (dev, lo);
  535. io_hi = 0;
  536. if ((hi >= 0) && (hi <= 6))
  537. io_hi = pci_resource_start (dev, hi);
  538. else if (hi > 6)
  539. io_lo += hi; /* Reinterpret the meaning of
  540. "hi" as an offset (see SYBA
  541. def.) */
  542. /* TODO: test if sharing interrupts works */
  543. irq = dev->irq;
  544. if (irq == IRQ_NONE) {
  545. dev_dbg(&dev->dev,
  546. "PCI parallel port detected: I/O at %#lx(%#lx)\n",
  547. io_lo, io_hi);
  548. irq = PARPORT_IRQ_NONE;
  549. } else {
  550. dev_dbg(&dev->dev,
  551. "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
  552. io_lo, io_hi, irq);
  553. }
  554. port = parport_pc_probe_port (io_lo, io_hi, irq,
  555. PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
  556. if (port) {
  557. priv->port[priv->num_par++] = port;
  558. success = 1;
  559. }
  560. }
  561. if (card->postinit_hook)
  562. card->postinit_hook (dev, card, !success);
  563. return 0;
  564. }
  565. static int parport_serial_pci_probe(struct pci_dev *dev,
  566. const struct pci_device_id *id)
  567. {
  568. struct parport_serial_private *priv;
  569. int err;
  570. priv = kzalloc (sizeof *priv, GFP_KERNEL);
  571. if (!priv)
  572. return -ENOMEM;
  573. pci_set_drvdata (dev, priv);
  574. err = pci_enable_device (dev);
  575. if (err) {
  576. kfree (priv);
  577. return err;
  578. }
  579. if (parport_register (dev, id)) {
  580. kfree (priv);
  581. return -ENODEV;
  582. }
  583. if (serial_register (dev, id)) {
  584. int i;
  585. for (i = 0; i < priv->num_par; i++)
  586. parport_pc_unregister_port (priv->port[i]);
  587. kfree (priv);
  588. return -ENODEV;
  589. }
  590. return 0;
  591. }
  592. static void parport_serial_pci_remove(struct pci_dev *dev)
  593. {
  594. struct parport_serial_private *priv = pci_get_drvdata (dev);
  595. int i;
  596. // Serial ports
  597. if (priv->serial)
  598. pciserial_remove_ports(priv->serial);
  599. // Parallel ports
  600. for (i = 0; i < priv->num_par; i++)
  601. parport_pc_unregister_port (priv->port[i]);
  602. kfree (priv);
  603. return;
  604. }
  605. #ifdef CONFIG_PM
  606. static int parport_serial_pci_suspend(struct pci_dev *dev, pm_message_t state)
  607. {
  608. struct parport_serial_private *priv = pci_get_drvdata(dev);
  609. if (priv->serial)
  610. pciserial_suspend_ports(priv->serial);
  611. /* FIXME: What about parport? */
  612. pci_save_state(dev);
  613. pci_set_power_state(dev, pci_choose_state(dev, state));
  614. return 0;
  615. }
  616. static int parport_serial_pci_resume(struct pci_dev *dev)
  617. {
  618. struct parport_serial_private *priv = pci_get_drvdata(dev);
  619. int err;
  620. pci_set_power_state(dev, PCI_D0);
  621. pci_restore_state(dev);
  622. /*
  623. * The device may have been disabled. Re-enable it.
  624. */
  625. err = pci_enable_device(dev);
  626. if (err) {
  627. printk(KERN_ERR "parport_serial: %s: error enabling "
  628. "device for resume (%d)\n", pci_name(dev), err);
  629. return err;
  630. }
  631. if (priv->serial)
  632. pciserial_resume_ports(priv->serial);
  633. /* FIXME: What about parport? */
  634. return 0;
  635. }
  636. #endif
  637. static struct pci_driver parport_serial_pci_driver = {
  638. .name = "parport_serial",
  639. .id_table = parport_serial_pci_tbl,
  640. .probe = parport_serial_pci_probe,
  641. .remove = parport_serial_pci_remove,
  642. #ifdef CONFIG_PM
  643. .suspend = parport_serial_pci_suspend,
  644. .resume = parport_serial_pci_resume,
  645. #endif
  646. };
  647. static int __init parport_serial_init (void)
  648. {
  649. return pci_register_driver (&parport_serial_pci_driver);
  650. }
  651. static void __exit parport_serial_exit (void)
  652. {
  653. pci_unregister_driver (&parport_serial_pci_driver);
  654. return;
  655. }
  656. MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
  657. MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
  658. MODULE_LICENSE("GPL");
  659. module_init(parport_serial_init);
  660. module_exit(parport_serial_exit);