htt_rx.c 46 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include "core.h"
  18. #include "htc.h"
  19. #include "htt.h"
  20. #include "txrx.h"
  21. #include "debug.h"
  22. #include "trace.h"
  23. #include "mac.h"
  24. #include <linux/log2.h>
  25. /* slightly larger than one large A-MPDU */
  26. #define HTT_RX_RING_SIZE_MIN 128
  27. /* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
  28. #define HTT_RX_RING_SIZE_MAX 2048
  29. #define HTT_RX_AVG_FRM_BYTES 1000
  30. /* ms, very conservative */
  31. #define HTT_RX_HOST_LATENCY_MAX_MS 20
  32. /* ms, conservative */
  33. #define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
  34. /* when under memory pressure rx ring refill may fail and needs a retry */
  35. #define HTT_RX_RING_REFILL_RETRY_MS 50
  36. static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
  37. static void ath10k_htt_txrx_compl_task(unsigned long ptr);
  38. static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
  39. {
  40. int size;
  41. /*
  42. * It is expected that the host CPU will typically be able to
  43. * service the rx indication from one A-MPDU before the rx
  44. * indication from the subsequent A-MPDU happens, roughly 1-2 ms
  45. * later. However, the rx ring should be sized very conservatively,
  46. * to accomodate the worst reasonable delay before the host CPU
  47. * services a rx indication interrupt.
  48. *
  49. * The rx ring need not be kept full of empty buffers. In theory,
  50. * the htt host SW can dynamically track the low-water mark in the
  51. * rx ring, and dynamically adjust the level to which the rx ring
  52. * is filled with empty buffers, to dynamically meet the desired
  53. * low-water mark.
  54. *
  55. * In contrast, it's difficult to resize the rx ring itself, once
  56. * it's in use. Thus, the ring itself should be sized very
  57. * conservatively, while the degree to which the ring is filled
  58. * with empty buffers should be sized moderately conservatively.
  59. */
  60. /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
  61. size =
  62. htt->max_throughput_mbps +
  63. 1000 /
  64. (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
  65. if (size < HTT_RX_RING_SIZE_MIN)
  66. size = HTT_RX_RING_SIZE_MIN;
  67. if (size > HTT_RX_RING_SIZE_MAX)
  68. size = HTT_RX_RING_SIZE_MAX;
  69. size = roundup_pow_of_two(size);
  70. return size;
  71. }
  72. static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
  73. {
  74. int size;
  75. /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
  76. size =
  77. htt->max_throughput_mbps *
  78. 1000 /
  79. (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
  80. /*
  81. * Make sure the fill level is at least 1 less than the ring size.
  82. * Leaving 1 element empty allows the SW to easily distinguish
  83. * between a full ring vs. an empty ring.
  84. */
  85. if (size >= htt->rx_ring.size)
  86. size = htt->rx_ring.size - 1;
  87. return size;
  88. }
  89. static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
  90. {
  91. struct sk_buff *skb;
  92. struct ath10k_skb_cb *cb;
  93. int i;
  94. for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
  95. skb = htt->rx_ring.netbufs_ring[i];
  96. cb = ATH10K_SKB_CB(skb);
  97. dma_unmap_single(htt->ar->dev, cb->paddr,
  98. skb->len + skb_tailroom(skb),
  99. DMA_FROM_DEVICE);
  100. dev_kfree_skb_any(skb);
  101. }
  102. htt->rx_ring.fill_cnt = 0;
  103. }
  104. static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
  105. {
  106. struct htt_rx_desc *rx_desc;
  107. struct sk_buff *skb;
  108. dma_addr_t paddr;
  109. int ret = 0, idx;
  110. idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
  111. while (num > 0) {
  112. skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
  113. if (!skb) {
  114. ret = -ENOMEM;
  115. goto fail;
  116. }
  117. if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
  118. skb_pull(skb,
  119. PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
  120. skb->data);
  121. /* Clear rx_desc attention word before posting to Rx ring */
  122. rx_desc = (struct htt_rx_desc *)skb->data;
  123. rx_desc->attention.flags = __cpu_to_le32(0);
  124. paddr = dma_map_single(htt->ar->dev, skb->data,
  125. skb->len + skb_tailroom(skb),
  126. DMA_FROM_DEVICE);
  127. if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
  128. dev_kfree_skb_any(skb);
  129. ret = -ENOMEM;
  130. goto fail;
  131. }
  132. ATH10K_SKB_CB(skb)->paddr = paddr;
  133. htt->rx_ring.netbufs_ring[idx] = skb;
  134. htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
  135. htt->rx_ring.fill_cnt++;
  136. num--;
  137. idx++;
  138. idx &= htt->rx_ring.size_mask;
  139. }
  140. fail:
  141. *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx);
  142. return ret;
  143. }
  144. static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
  145. {
  146. lockdep_assert_held(&htt->rx_ring.lock);
  147. return __ath10k_htt_rx_ring_fill_n(htt, num);
  148. }
  149. static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
  150. {
  151. int ret, num_deficit, num_to_fill;
  152. /* Refilling the whole RX ring buffer proves to be a bad idea. The
  153. * reason is RX may take up significant amount of CPU cycles and starve
  154. * other tasks, e.g. TX on an ethernet device while acting as a bridge
  155. * with ath10k wlan interface. This ended up with very poor performance
  156. * once CPU the host system was overwhelmed with RX on ath10k.
  157. *
  158. * By limiting the number of refills the replenishing occurs
  159. * progressively. This in turns makes use of the fact tasklets are
  160. * processed in FIFO order. This means actual RX processing can starve
  161. * out refilling. If there's not enough buffers on RX ring FW will not
  162. * report RX until it is refilled with enough buffers. This
  163. * automatically balances load wrt to CPU power.
  164. *
  165. * This probably comes at a cost of lower maximum throughput but
  166. * improves the avarage and stability. */
  167. spin_lock_bh(&htt->rx_ring.lock);
  168. num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
  169. num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
  170. num_deficit -= num_to_fill;
  171. ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
  172. if (ret == -ENOMEM) {
  173. /*
  174. * Failed to fill it to the desired level -
  175. * we'll start a timer and try again next time.
  176. * As long as enough buffers are left in the ring for
  177. * another A-MPDU rx, no special recovery is needed.
  178. */
  179. mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
  180. msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
  181. } else if (num_deficit > 0) {
  182. tasklet_schedule(&htt->rx_replenish_task);
  183. }
  184. spin_unlock_bh(&htt->rx_ring.lock);
  185. }
  186. static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
  187. {
  188. struct ath10k_htt *htt = (struct ath10k_htt *)arg;
  189. ath10k_htt_rx_msdu_buff_replenish(htt);
  190. }
  191. static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt)
  192. {
  193. struct sk_buff *skb;
  194. int i;
  195. for (i = 0; i < htt->rx_ring.size; i++) {
  196. skb = htt->rx_ring.netbufs_ring[i];
  197. if (!skb)
  198. continue;
  199. dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr,
  200. skb->len + skb_tailroom(skb),
  201. DMA_FROM_DEVICE);
  202. dev_kfree_skb_any(skb);
  203. htt->rx_ring.netbufs_ring[i] = NULL;
  204. }
  205. }
  206. void ath10k_htt_rx_free(struct ath10k_htt *htt)
  207. {
  208. del_timer_sync(&htt->rx_ring.refill_retry_timer);
  209. tasklet_kill(&htt->rx_replenish_task);
  210. tasklet_kill(&htt->txrx_compl_task);
  211. skb_queue_purge(&htt->tx_compl_q);
  212. skb_queue_purge(&htt->rx_compl_q);
  213. ath10k_htt_rx_ring_clean_up(htt);
  214. dma_free_coherent(htt->ar->dev,
  215. (htt->rx_ring.size *
  216. sizeof(htt->rx_ring.paddrs_ring)),
  217. htt->rx_ring.paddrs_ring,
  218. htt->rx_ring.base_paddr);
  219. dma_free_coherent(htt->ar->dev,
  220. sizeof(*htt->rx_ring.alloc_idx.vaddr),
  221. htt->rx_ring.alloc_idx.vaddr,
  222. htt->rx_ring.alloc_idx.paddr);
  223. kfree(htt->rx_ring.netbufs_ring);
  224. }
  225. static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
  226. {
  227. struct ath10k *ar = htt->ar;
  228. int idx;
  229. struct sk_buff *msdu;
  230. lockdep_assert_held(&htt->rx_ring.lock);
  231. if (htt->rx_ring.fill_cnt == 0) {
  232. ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n");
  233. return NULL;
  234. }
  235. idx = htt->rx_ring.sw_rd_idx.msdu_payld;
  236. msdu = htt->rx_ring.netbufs_ring[idx];
  237. htt->rx_ring.netbufs_ring[idx] = NULL;
  238. idx++;
  239. idx &= htt->rx_ring.size_mask;
  240. htt->rx_ring.sw_rd_idx.msdu_payld = idx;
  241. htt->rx_ring.fill_cnt--;
  242. return msdu;
  243. }
  244. static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
  245. {
  246. struct sk_buff *next;
  247. while (skb) {
  248. next = skb->next;
  249. dev_kfree_skb_any(skb);
  250. skb = next;
  251. }
  252. }
  253. /* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */
  254. static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
  255. u8 **fw_desc, int *fw_desc_len,
  256. struct sk_buff **head_msdu,
  257. struct sk_buff **tail_msdu,
  258. u32 *attention)
  259. {
  260. struct ath10k *ar = htt->ar;
  261. int msdu_len, msdu_chaining = 0;
  262. struct sk_buff *msdu, *next;
  263. struct htt_rx_desc *rx_desc;
  264. lockdep_assert_held(&htt->rx_ring.lock);
  265. if (htt->rx_confused) {
  266. ath10k_warn(ar, "htt is confused. refusing rx\n");
  267. return -1;
  268. }
  269. msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
  270. while (msdu) {
  271. int last_msdu, msdu_len_invalid, msdu_chained;
  272. dma_unmap_single(htt->ar->dev,
  273. ATH10K_SKB_CB(msdu)->paddr,
  274. msdu->len + skb_tailroom(msdu),
  275. DMA_FROM_DEVICE);
  276. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
  277. msdu->data, msdu->len + skb_tailroom(msdu));
  278. rx_desc = (struct htt_rx_desc *)msdu->data;
  279. /* FIXME: we must report msdu payload since this is what caller
  280. * expects now */
  281. skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
  282. skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
  283. /*
  284. * Sanity check - confirm the HW is finished filling in the
  285. * rx data.
  286. * If the HW and SW are working correctly, then it's guaranteed
  287. * that the HW's MAC DMA is done before this point in the SW.
  288. * To prevent the case that we handle a stale Rx descriptor,
  289. * just assert for now until we have a way to recover.
  290. */
  291. if (!(__le32_to_cpu(rx_desc->attention.flags)
  292. & RX_ATTENTION_FLAGS_MSDU_DONE)) {
  293. ath10k_htt_rx_free_msdu_chain(*head_msdu);
  294. *head_msdu = NULL;
  295. msdu = NULL;
  296. ath10k_err(ar, "htt rx stopped. cannot recover\n");
  297. htt->rx_confused = true;
  298. break;
  299. }
  300. *attention |= __le32_to_cpu(rx_desc->attention.flags) &
  301. (RX_ATTENTION_FLAGS_TKIP_MIC_ERR |
  302. RX_ATTENTION_FLAGS_DECRYPT_ERR |
  303. RX_ATTENTION_FLAGS_FCS_ERR |
  304. RX_ATTENTION_FLAGS_MGMT_TYPE);
  305. /*
  306. * Copy the FW rx descriptor for this MSDU from the rx
  307. * indication message into the MSDU's netbuf. HL uses the
  308. * same rx indication message definition as LL, and simply
  309. * appends new info (fields from the HW rx desc, and the
  310. * MSDU payload itself). So, the offset into the rx
  311. * indication message only has to account for the standard
  312. * offset of the per-MSDU FW rx desc info within the
  313. * message, and how many bytes of the per-MSDU FW rx desc
  314. * info have already been consumed. (And the endianness of
  315. * the host, since for a big-endian host, the rx ind
  316. * message contents, including the per-MSDU rx desc bytes,
  317. * were byteswapped during upload.)
  318. */
  319. if (*fw_desc_len > 0) {
  320. rx_desc->fw_desc.info0 = **fw_desc;
  321. /*
  322. * The target is expected to only provide the basic
  323. * per-MSDU rx descriptors. Just to be sure, verify
  324. * that the target has not attached extension data
  325. * (e.g. LRO flow ID).
  326. */
  327. /* or more, if there's extension data */
  328. (*fw_desc)++;
  329. (*fw_desc_len)--;
  330. } else {
  331. /*
  332. * When an oversized AMSDU happened, FW will lost
  333. * some of MSDU status - in this case, the FW
  334. * descriptors provided will be less than the
  335. * actual MSDUs inside this MPDU. Mark the FW
  336. * descriptors so that it will still deliver to
  337. * upper stack, if no CRC error for this MPDU.
  338. *
  339. * FIX THIS - the FW descriptors are actually for
  340. * MSDUs in the end of this A-MSDU instead of the
  341. * beginning.
  342. */
  343. rx_desc->fw_desc.info0 = 0;
  344. }
  345. msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
  346. & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
  347. RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
  348. msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
  349. RX_MSDU_START_INFO0_MSDU_LENGTH);
  350. msdu_chained = rx_desc->frag_info.ring2_more_count;
  351. if (msdu_len_invalid)
  352. msdu_len = 0;
  353. skb_trim(msdu, 0);
  354. skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
  355. msdu_len -= msdu->len;
  356. /* FIXME: Do chained buffers include htt_rx_desc or not? */
  357. while (msdu_chained--) {
  358. struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
  359. dma_unmap_single(htt->ar->dev,
  360. ATH10K_SKB_CB(next)->paddr,
  361. next->len + skb_tailroom(next),
  362. DMA_FROM_DEVICE);
  363. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL,
  364. "htt rx chained: ", next->data,
  365. next->len + skb_tailroom(next));
  366. skb_trim(next, 0);
  367. skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
  368. msdu_len -= next->len;
  369. msdu->next = next;
  370. msdu = next;
  371. msdu_chaining = 1;
  372. }
  373. last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
  374. RX_MSDU_END_INFO0_LAST_MSDU;
  375. if (last_msdu) {
  376. msdu->next = NULL;
  377. break;
  378. }
  379. next = ath10k_htt_rx_netbuf_pop(htt);
  380. msdu->next = next;
  381. msdu = next;
  382. }
  383. *tail_msdu = msdu;
  384. if (*head_msdu == NULL)
  385. msdu_chaining = -1;
  386. /*
  387. * Don't refill the ring yet.
  388. *
  389. * First, the elements popped here are still in use - it is not
  390. * safe to overwrite them until the matching call to
  391. * mpdu_desc_list_next. Second, for efficiency it is preferable to
  392. * refill the rx ring with 1 PPDU's worth of rx buffers (something
  393. * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
  394. * (something like 3 buffers). Consequently, we'll rely on the txrx
  395. * SW to tell us when it is done pulling all the PPDU's rx buffers
  396. * out of the rx ring, and then refill it just once.
  397. */
  398. return msdu_chaining;
  399. }
  400. static void ath10k_htt_rx_replenish_task(unsigned long ptr)
  401. {
  402. struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
  403. ath10k_htt_rx_msdu_buff_replenish(htt);
  404. }
  405. int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
  406. {
  407. struct ath10k *ar = htt->ar;
  408. dma_addr_t paddr;
  409. void *vaddr;
  410. size_t size;
  411. struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
  412. htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
  413. if (!is_power_of_2(htt->rx_ring.size)) {
  414. ath10k_warn(ar, "htt rx ring size is not power of 2\n");
  415. return -EINVAL;
  416. }
  417. htt->rx_ring.size_mask = htt->rx_ring.size - 1;
  418. /*
  419. * Set the initial value for the level to which the rx ring
  420. * should be filled, based on the max throughput and the
  421. * worst likely latency for the host to fill the rx ring
  422. * with new buffers. In theory, this fill level can be
  423. * dynamically adjusted from the initial value set here, to
  424. * reflect the actual host latency rather than a
  425. * conservative assumption about the host latency.
  426. */
  427. htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
  428. htt->rx_ring.netbufs_ring =
  429. kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
  430. GFP_KERNEL);
  431. if (!htt->rx_ring.netbufs_ring)
  432. goto err_netbuf;
  433. size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring);
  434. vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA);
  435. if (!vaddr)
  436. goto err_dma_ring;
  437. htt->rx_ring.paddrs_ring = vaddr;
  438. htt->rx_ring.base_paddr = paddr;
  439. vaddr = dma_alloc_coherent(htt->ar->dev,
  440. sizeof(*htt->rx_ring.alloc_idx.vaddr),
  441. &paddr, GFP_DMA);
  442. if (!vaddr)
  443. goto err_dma_idx;
  444. htt->rx_ring.alloc_idx.vaddr = vaddr;
  445. htt->rx_ring.alloc_idx.paddr = paddr;
  446. htt->rx_ring.sw_rd_idx.msdu_payld = 0;
  447. *htt->rx_ring.alloc_idx.vaddr = 0;
  448. /* Initialize the Rx refill retry timer */
  449. setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
  450. spin_lock_init(&htt->rx_ring.lock);
  451. htt->rx_ring.fill_cnt = 0;
  452. if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
  453. goto err_fill_ring;
  454. tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
  455. (unsigned long)htt);
  456. skb_queue_head_init(&htt->tx_compl_q);
  457. skb_queue_head_init(&htt->rx_compl_q);
  458. tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
  459. (unsigned long)htt);
  460. ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
  461. htt->rx_ring.size, htt->rx_ring.fill_level);
  462. return 0;
  463. err_fill_ring:
  464. ath10k_htt_rx_ring_free(htt);
  465. dma_free_coherent(htt->ar->dev,
  466. sizeof(*htt->rx_ring.alloc_idx.vaddr),
  467. htt->rx_ring.alloc_idx.vaddr,
  468. htt->rx_ring.alloc_idx.paddr);
  469. err_dma_idx:
  470. dma_free_coherent(htt->ar->dev,
  471. (htt->rx_ring.size *
  472. sizeof(htt->rx_ring.paddrs_ring)),
  473. htt->rx_ring.paddrs_ring,
  474. htt->rx_ring.base_paddr);
  475. err_dma_ring:
  476. kfree(htt->rx_ring.netbufs_ring);
  477. err_netbuf:
  478. return -ENOMEM;
  479. }
  480. static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar,
  481. enum htt_rx_mpdu_encrypt_type type)
  482. {
  483. switch (type) {
  484. case HTT_RX_MPDU_ENCRYPT_WEP40:
  485. case HTT_RX_MPDU_ENCRYPT_WEP104:
  486. return 4;
  487. case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
  488. case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */
  489. case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
  490. case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */
  491. case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
  492. return 8;
  493. case HTT_RX_MPDU_ENCRYPT_NONE:
  494. return 0;
  495. }
  496. ath10k_warn(ar, "unknown encryption type %d\n", type);
  497. return 0;
  498. }
  499. static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar,
  500. enum htt_rx_mpdu_encrypt_type type)
  501. {
  502. switch (type) {
  503. case HTT_RX_MPDU_ENCRYPT_NONE:
  504. case HTT_RX_MPDU_ENCRYPT_WEP40:
  505. case HTT_RX_MPDU_ENCRYPT_WEP104:
  506. case HTT_RX_MPDU_ENCRYPT_WEP128:
  507. case HTT_RX_MPDU_ENCRYPT_WAPI:
  508. return 0;
  509. case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
  510. case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
  511. return 4;
  512. case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
  513. return 8;
  514. }
  515. ath10k_warn(ar, "unknown encryption type %d\n", type);
  516. return 0;
  517. }
  518. /* Applies for first msdu in chain, before altering it. */
  519. static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
  520. {
  521. struct htt_rx_desc *rxd;
  522. enum rx_msdu_decap_format fmt;
  523. rxd = (void *)skb->data - sizeof(*rxd);
  524. fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
  525. RX_MSDU_START_INFO1_DECAP_FORMAT);
  526. if (fmt == RX_MSDU_DECAP_RAW)
  527. return (void *)skb->data;
  528. return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
  529. }
  530. /* This function only applies for first msdu in an msdu chain */
  531. static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
  532. {
  533. u8 *qc;
  534. if (ieee80211_is_data_qos(hdr->frame_control)) {
  535. qc = ieee80211_get_qos_ctl(hdr);
  536. if (qc[0] & 0x80)
  537. return true;
  538. }
  539. return false;
  540. }
  541. struct rfc1042_hdr {
  542. u8 llc_dsap;
  543. u8 llc_ssap;
  544. u8 llc_ctrl;
  545. u8 snap_oui[3];
  546. __be16 snap_type;
  547. } __packed;
  548. struct amsdu_subframe_hdr {
  549. u8 dst[ETH_ALEN];
  550. u8 src[ETH_ALEN];
  551. __be16 len;
  552. } __packed;
  553. static const u8 rx_legacy_rate_idx[] = {
  554. 3, /* 0x00 - 11Mbps */
  555. 2, /* 0x01 - 5.5Mbps */
  556. 1, /* 0x02 - 2Mbps */
  557. 0, /* 0x03 - 1Mbps */
  558. 3, /* 0x04 - 11Mbps */
  559. 2, /* 0x05 - 5.5Mbps */
  560. 1, /* 0x06 - 2Mbps */
  561. 0, /* 0x07 - 1Mbps */
  562. 10, /* 0x08 - 48Mbps */
  563. 8, /* 0x09 - 24Mbps */
  564. 6, /* 0x0A - 12Mbps */
  565. 4, /* 0x0B - 6Mbps */
  566. 11, /* 0x0C - 54Mbps */
  567. 9, /* 0x0D - 36Mbps */
  568. 7, /* 0x0E - 18Mbps */
  569. 5, /* 0x0F - 9Mbps */
  570. };
  571. static void ath10k_htt_rx_h_rates(struct ath10k *ar,
  572. enum ieee80211_band band,
  573. u8 info0, u32 info1, u32 info2,
  574. struct ieee80211_rx_status *status)
  575. {
  576. u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
  577. u8 preamble = 0;
  578. /* Check if valid fields */
  579. if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
  580. return;
  581. preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
  582. switch (preamble) {
  583. case HTT_RX_LEGACY:
  584. cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
  585. rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
  586. rate_idx = 0;
  587. if (rate < 0x08 || rate > 0x0F)
  588. break;
  589. switch (band) {
  590. case IEEE80211_BAND_2GHZ:
  591. if (cck)
  592. rate &= ~BIT(3);
  593. rate_idx = rx_legacy_rate_idx[rate];
  594. break;
  595. case IEEE80211_BAND_5GHZ:
  596. rate_idx = rx_legacy_rate_idx[rate];
  597. /* We are using same rate table registering
  598. HW - ath10k_rates[]. In case of 5GHz skip
  599. CCK rates, so -4 here */
  600. rate_idx -= 4;
  601. break;
  602. default:
  603. break;
  604. }
  605. status->rate_idx = rate_idx;
  606. break;
  607. case HTT_RX_HT:
  608. case HTT_RX_HT_WITH_TXBF:
  609. /* HT-SIG - Table 20-11 in info1 and info2 */
  610. mcs = info1 & 0x1F;
  611. nss = mcs >> 3;
  612. bw = (info1 >> 7) & 1;
  613. sgi = (info2 >> 7) & 1;
  614. status->rate_idx = mcs;
  615. status->flag |= RX_FLAG_HT;
  616. if (sgi)
  617. status->flag |= RX_FLAG_SHORT_GI;
  618. if (bw)
  619. status->flag |= RX_FLAG_40MHZ;
  620. break;
  621. case HTT_RX_VHT:
  622. case HTT_RX_VHT_WITH_TXBF:
  623. /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
  624. TODO check this */
  625. mcs = (info2 >> 4) & 0x0F;
  626. nss = ((info1 >> 10) & 0x07) + 1;
  627. bw = info1 & 3;
  628. sgi = info2 & 1;
  629. status->rate_idx = mcs;
  630. status->vht_nss = nss;
  631. if (sgi)
  632. status->flag |= RX_FLAG_SHORT_GI;
  633. switch (bw) {
  634. /* 20MHZ */
  635. case 0:
  636. break;
  637. /* 40MHZ */
  638. case 1:
  639. status->flag |= RX_FLAG_40MHZ;
  640. break;
  641. /* 80MHZ */
  642. case 2:
  643. status->vht_flag |= RX_VHT_FLAG_80MHZ;
  644. }
  645. status->flag |= RX_FLAG_VHT;
  646. break;
  647. default:
  648. break;
  649. }
  650. }
  651. static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
  652. struct ieee80211_rx_status *rx_status,
  653. struct sk_buff *skb,
  654. enum htt_rx_mpdu_encrypt_type enctype,
  655. enum rx_msdu_decap_format fmt,
  656. bool dot11frag)
  657. {
  658. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  659. rx_status->flag &= ~(RX_FLAG_DECRYPTED |
  660. RX_FLAG_IV_STRIPPED |
  661. RX_FLAG_MMIC_STRIPPED);
  662. if (enctype == HTT_RX_MPDU_ENCRYPT_NONE)
  663. return;
  664. /*
  665. * There's no explicit rx descriptor flag to indicate whether a given
  666. * frame has been decrypted or not. We're forced to use the decap
  667. * format as an implicit indication. However fragmentation rx is always
  668. * raw and it probably never reports undecrypted raws.
  669. *
  670. * This makes sure sniffed frames are reported as-is without stripping
  671. * the protected flag.
  672. */
  673. if (fmt == RX_MSDU_DECAP_RAW && !dot11frag)
  674. return;
  675. rx_status->flag |= RX_FLAG_DECRYPTED |
  676. RX_FLAG_IV_STRIPPED |
  677. RX_FLAG_MMIC_STRIPPED;
  678. hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
  679. ~IEEE80211_FCTL_PROTECTED);
  680. }
  681. static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
  682. struct ieee80211_rx_status *status)
  683. {
  684. struct ieee80211_channel *ch;
  685. spin_lock_bh(&ar->data_lock);
  686. ch = ar->scan_channel;
  687. if (!ch)
  688. ch = ar->rx_channel;
  689. spin_unlock_bh(&ar->data_lock);
  690. if (!ch)
  691. return false;
  692. status->band = ch->band;
  693. status->freq = ch->center_freq;
  694. return true;
  695. }
  696. static const char * const tid_to_ac[] = {
  697. "BE",
  698. "BK",
  699. "BK",
  700. "BE",
  701. "VI",
  702. "VI",
  703. "VO",
  704. "VO",
  705. };
  706. static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size)
  707. {
  708. u8 *qc;
  709. int tid;
  710. if (!ieee80211_is_data_qos(hdr->frame_control))
  711. return "";
  712. qc = ieee80211_get_qos_ctl(hdr);
  713. tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
  714. if (tid < 8)
  715. snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]);
  716. else
  717. snprintf(out, size, "tid %d", tid);
  718. return out;
  719. }
  720. static void ath10k_process_rx(struct ath10k *ar,
  721. struct ieee80211_rx_status *rx_status,
  722. struct sk_buff *skb)
  723. {
  724. struct ieee80211_rx_status *status;
  725. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
  726. char tid[32];
  727. status = IEEE80211_SKB_RXCB(skb);
  728. *status = *rx_status;
  729. ath10k_dbg(ar, ATH10K_DBG_DATA,
  730. "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
  731. skb,
  732. skb->len,
  733. ieee80211_get_SA(hdr),
  734. ath10k_get_tid(hdr, tid, sizeof(tid)),
  735. is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
  736. "mcast" : "ucast",
  737. (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
  738. status->flag == 0 ? "legacy" : "",
  739. status->flag & RX_FLAG_HT ? "ht" : "",
  740. status->flag & RX_FLAG_VHT ? "vht" : "",
  741. status->flag & RX_FLAG_40MHZ ? "40" : "",
  742. status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
  743. status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
  744. status->rate_idx,
  745. status->vht_nss,
  746. status->freq,
  747. status->band, status->flag,
  748. !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
  749. !!(status->flag & RX_FLAG_MMIC_ERROR),
  750. !!(status->flag & RX_FLAG_AMSDU_MORE));
  751. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
  752. skb->data, skb->len);
  753. ieee80211_rx(ar->hw, skb);
  754. }
  755. static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
  756. {
  757. /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
  758. return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
  759. }
  760. static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
  761. struct ieee80211_rx_status *rx_status,
  762. struct sk_buff *skb_in)
  763. {
  764. struct ath10k *ar = htt->ar;
  765. struct htt_rx_desc *rxd;
  766. struct sk_buff *skb = skb_in;
  767. struct sk_buff *first;
  768. enum rx_msdu_decap_format fmt;
  769. enum htt_rx_mpdu_encrypt_type enctype;
  770. struct ieee80211_hdr *hdr;
  771. u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos;
  772. unsigned int hdr_len;
  773. rxd = (void *)skb->data - sizeof(*rxd);
  774. enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
  775. RX_MPDU_START_INFO0_ENCRYPT_TYPE);
  776. hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
  777. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  778. memcpy(hdr_buf, hdr, hdr_len);
  779. hdr = (struct ieee80211_hdr *)hdr_buf;
  780. first = skb;
  781. while (skb) {
  782. void *decap_hdr;
  783. int len;
  784. rxd = (void *)skb->data - sizeof(*rxd);
  785. fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
  786. RX_MSDU_START_INFO1_DECAP_FORMAT);
  787. decap_hdr = (void *)rxd->rx_hdr_status;
  788. skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
  789. /* First frame in an A-MSDU chain has more decapped data. */
  790. if (skb == first) {
  791. len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
  792. len += round_up(ath10k_htt_rx_crypto_param_len(ar,
  793. enctype), 4);
  794. decap_hdr += len;
  795. }
  796. switch (fmt) {
  797. case RX_MSDU_DECAP_RAW:
  798. /* remove trailing FCS */
  799. skb_trim(skb, skb->len - FCS_LEN);
  800. break;
  801. case RX_MSDU_DECAP_NATIVE_WIFI:
  802. /* pull decapped header and copy SA & DA */
  803. hdr = (struct ieee80211_hdr *)skb->data;
  804. hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
  805. ether_addr_copy(da, ieee80211_get_DA(hdr));
  806. ether_addr_copy(sa, ieee80211_get_SA(hdr));
  807. skb_pull(skb, hdr_len);
  808. /* push original 802.11 header */
  809. hdr = (struct ieee80211_hdr *)hdr_buf;
  810. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  811. memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
  812. /* original A-MSDU header has the bit set but we're
  813. * not including A-MSDU subframe header */
  814. hdr = (struct ieee80211_hdr *)skb->data;
  815. qos = ieee80211_get_qos_ctl(hdr);
  816. qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
  817. /* original 802.11 header has a different DA and in
  818. * case of 4addr it may also have different SA
  819. */
  820. ether_addr_copy(ieee80211_get_DA(hdr), da);
  821. ether_addr_copy(ieee80211_get_SA(hdr), sa);
  822. break;
  823. case RX_MSDU_DECAP_ETHERNET2_DIX:
  824. /* strip ethernet header and insert decapped 802.11
  825. * header, amsdu subframe header and rfc1042 header */
  826. len = 0;
  827. len += sizeof(struct rfc1042_hdr);
  828. len += sizeof(struct amsdu_subframe_hdr);
  829. skb_pull(skb, sizeof(struct ethhdr));
  830. memcpy(skb_push(skb, len), decap_hdr, len);
  831. memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
  832. break;
  833. case RX_MSDU_DECAP_8023_SNAP_LLC:
  834. /* insert decapped 802.11 header making a singly
  835. * A-MSDU */
  836. memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
  837. break;
  838. }
  839. skb_in = skb;
  840. ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype, fmt,
  841. false);
  842. skb = skb->next;
  843. skb_in->next = NULL;
  844. if (skb)
  845. rx_status->flag |= RX_FLAG_AMSDU_MORE;
  846. else
  847. rx_status->flag &= ~RX_FLAG_AMSDU_MORE;
  848. ath10k_process_rx(htt->ar, rx_status, skb_in);
  849. }
  850. /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
  851. * monitor interface active for sniffing purposes. */
  852. }
  853. static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
  854. struct ieee80211_rx_status *rx_status,
  855. struct sk_buff *skb)
  856. {
  857. struct ath10k *ar = htt->ar;
  858. struct htt_rx_desc *rxd;
  859. struct ieee80211_hdr *hdr;
  860. enum rx_msdu_decap_format fmt;
  861. enum htt_rx_mpdu_encrypt_type enctype;
  862. int hdr_len;
  863. void *rfc1042;
  864. /* This shouldn't happen. If it does than it may be a FW bug. */
  865. if (skb->next) {
  866. ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n");
  867. ath10k_htt_rx_free_msdu_chain(skb->next);
  868. skb->next = NULL;
  869. }
  870. rxd = (void *)skb->data - sizeof(*rxd);
  871. fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
  872. RX_MSDU_START_INFO1_DECAP_FORMAT);
  873. enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
  874. RX_MPDU_START_INFO0_ENCRYPT_TYPE);
  875. hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
  876. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  877. skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
  878. switch (fmt) {
  879. case RX_MSDU_DECAP_RAW:
  880. /* remove trailing FCS */
  881. skb_trim(skb, skb->len - FCS_LEN);
  882. break;
  883. case RX_MSDU_DECAP_NATIVE_WIFI:
  884. /* Pull decapped header */
  885. hdr = (struct ieee80211_hdr *)skb->data;
  886. hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
  887. skb_pull(skb, hdr_len);
  888. /* Push original header */
  889. hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
  890. hdr_len = ieee80211_hdrlen(hdr->frame_control);
  891. memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
  892. break;
  893. case RX_MSDU_DECAP_ETHERNET2_DIX:
  894. /* strip ethernet header and insert decapped 802.11 header and
  895. * rfc1042 header */
  896. rfc1042 = hdr;
  897. rfc1042 += roundup(hdr_len, 4);
  898. rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar,
  899. enctype), 4);
  900. skb_pull(skb, sizeof(struct ethhdr));
  901. memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
  902. rfc1042, sizeof(struct rfc1042_hdr));
  903. memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
  904. break;
  905. case RX_MSDU_DECAP_8023_SNAP_LLC:
  906. /* remove A-MSDU subframe header and insert
  907. * decapped 802.11 header. rfc1042 header is already there */
  908. skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
  909. memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
  910. break;
  911. }
  912. ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false);
  913. ath10k_process_rx(htt->ar, rx_status, skb);
  914. }
  915. static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
  916. {
  917. struct htt_rx_desc *rxd;
  918. u32 flags, info;
  919. bool is_ip4, is_ip6;
  920. bool is_tcp, is_udp;
  921. bool ip_csum_ok, tcpudp_csum_ok;
  922. rxd = (void *)skb->data - sizeof(*rxd);
  923. flags = __le32_to_cpu(rxd->attention.flags);
  924. info = __le32_to_cpu(rxd->msdu_start.info1);
  925. is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
  926. is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
  927. is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
  928. is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
  929. ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
  930. tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
  931. if (!is_ip4 && !is_ip6)
  932. return CHECKSUM_NONE;
  933. if (!is_tcp && !is_udp)
  934. return CHECKSUM_NONE;
  935. if (!ip_csum_ok)
  936. return CHECKSUM_NONE;
  937. if (!tcpudp_csum_ok)
  938. return CHECKSUM_NONE;
  939. return CHECKSUM_UNNECESSARY;
  940. }
  941. static int ath10k_unchain_msdu(struct sk_buff *msdu_head)
  942. {
  943. struct sk_buff *next = msdu_head->next;
  944. struct sk_buff *to_free = next;
  945. int space;
  946. int total_len = 0;
  947. /* TODO: Might could optimize this by using
  948. * skb_try_coalesce or similar method to
  949. * decrease copying, or maybe get mac80211 to
  950. * provide a way to just receive a list of
  951. * skb?
  952. */
  953. msdu_head->next = NULL;
  954. /* Allocate total length all at once. */
  955. while (next) {
  956. total_len += next->len;
  957. next = next->next;
  958. }
  959. space = total_len - skb_tailroom(msdu_head);
  960. if ((space > 0) &&
  961. (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) {
  962. /* TODO: bump some rx-oom error stat */
  963. /* put it back together so we can free the
  964. * whole list at once.
  965. */
  966. msdu_head->next = to_free;
  967. return -1;
  968. }
  969. /* Walk list again, copying contents into
  970. * msdu_head
  971. */
  972. next = to_free;
  973. while (next) {
  974. skb_copy_from_linear_data(next, skb_put(msdu_head, next->len),
  975. next->len);
  976. next = next->next;
  977. }
  978. /* If here, we have consolidated skb. Free the
  979. * fragments and pass the main skb on up the
  980. * stack.
  981. */
  982. ath10k_htt_rx_free_msdu_chain(to_free);
  983. return 0;
  984. }
  985. static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
  986. struct sk_buff *head,
  987. enum htt_rx_mpdu_status status,
  988. bool channel_set,
  989. u32 attention)
  990. {
  991. struct ath10k *ar = htt->ar;
  992. if (head->len == 0) {
  993. ath10k_dbg(ar, ATH10K_DBG_HTT,
  994. "htt rx dropping due to zero-len\n");
  995. return false;
  996. }
  997. if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
  998. ath10k_dbg(ar, ATH10K_DBG_HTT,
  999. "htt rx dropping due to decrypt-err\n");
  1000. return false;
  1001. }
  1002. if (!channel_set) {
  1003. ath10k_warn(ar, "no channel configured; ignoring frame!\n");
  1004. return false;
  1005. }
  1006. /* Skip mgmt frames while we handle this in WMI */
  1007. if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL ||
  1008. attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
  1009. ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
  1010. return false;
  1011. }
  1012. if (status != HTT_RX_IND_MPDU_STATUS_OK &&
  1013. status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
  1014. status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER &&
  1015. !htt->ar->monitor_started) {
  1016. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1017. "htt rx ignoring frame w/ status %d\n",
  1018. status);
  1019. return false;
  1020. }
  1021. if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
  1022. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1023. "htt rx CAC running\n");
  1024. return false;
  1025. }
  1026. return true;
  1027. }
  1028. static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
  1029. struct htt_rx_indication *rx)
  1030. {
  1031. struct ath10k *ar = htt->ar;
  1032. struct ieee80211_rx_status *rx_status = &htt->rx_status;
  1033. struct htt_rx_indication_mpdu_range *mpdu_ranges;
  1034. struct htt_rx_desc *rxd;
  1035. enum htt_rx_mpdu_status status;
  1036. struct ieee80211_hdr *hdr;
  1037. int num_mpdu_ranges;
  1038. u32 attention;
  1039. int fw_desc_len;
  1040. u8 *fw_desc;
  1041. bool channel_set;
  1042. int i, j;
  1043. int ret;
  1044. lockdep_assert_held(&htt->rx_ring.lock);
  1045. fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
  1046. fw_desc = (u8 *)&rx->fw_desc;
  1047. num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
  1048. HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
  1049. mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
  1050. /* Fill this once, while this is per-ppdu */
  1051. if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) {
  1052. memset(rx_status, 0, sizeof(*rx_status));
  1053. rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR +
  1054. rx->ppdu.combined_rssi;
  1055. }
  1056. if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
  1057. /* TSF available only in 32-bit */
  1058. rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
  1059. rx_status->flag |= RX_FLAG_MACTIME_END;
  1060. }
  1061. channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status);
  1062. if (channel_set) {
  1063. ath10k_htt_rx_h_rates(htt->ar, rx_status->band,
  1064. rx->ppdu.info0,
  1065. __le32_to_cpu(rx->ppdu.info1),
  1066. __le32_to_cpu(rx->ppdu.info2),
  1067. rx_status);
  1068. }
  1069. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
  1070. rx, sizeof(*rx) +
  1071. (sizeof(struct htt_rx_indication_mpdu_range) *
  1072. num_mpdu_ranges));
  1073. for (i = 0; i < num_mpdu_ranges; i++) {
  1074. status = mpdu_ranges[i].mpdu_range_status;
  1075. for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
  1076. struct sk_buff *msdu_head, *msdu_tail;
  1077. attention = 0;
  1078. msdu_head = NULL;
  1079. msdu_tail = NULL;
  1080. ret = ath10k_htt_rx_amsdu_pop(htt,
  1081. &fw_desc,
  1082. &fw_desc_len,
  1083. &msdu_head,
  1084. &msdu_tail,
  1085. &attention);
  1086. if (ret < 0) {
  1087. ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n",
  1088. ret);
  1089. ath10k_htt_rx_free_msdu_chain(msdu_head);
  1090. continue;
  1091. }
  1092. rxd = container_of((void *)msdu_head->data,
  1093. struct htt_rx_desc,
  1094. msdu_payload);
  1095. if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head,
  1096. status,
  1097. channel_set,
  1098. attention)) {
  1099. ath10k_htt_rx_free_msdu_chain(msdu_head);
  1100. continue;
  1101. }
  1102. if (ret > 0 &&
  1103. ath10k_unchain_msdu(msdu_head) < 0) {
  1104. ath10k_htt_rx_free_msdu_chain(msdu_head);
  1105. continue;
  1106. }
  1107. if (attention & RX_ATTENTION_FLAGS_FCS_ERR)
  1108. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  1109. else
  1110. rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC;
  1111. if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
  1112. rx_status->flag |= RX_FLAG_MMIC_ERROR;
  1113. else
  1114. rx_status->flag &= ~RX_FLAG_MMIC_ERROR;
  1115. hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
  1116. if (ath10k_htt_rx_hdr_is_amsdu(hdr))
  1117. ath10k_htt_rx_amsdu(htt, rx_status, msdu_head);
  1118. else
  1119. ath10k_htt_rx_msdu(htt, rx_status, msdu_head);
  1120. }
  1121. }
  1122. tasklet_schedule(&htt->rx_replenish_task);
  1123. }
  1124. static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
  1125. struct htt_rx_fragment_indication *frag)
  1126. {
  1127. struct ath10k *ar = htt->ar;
  1128. struct sk_buff *msdu_head, *msdu_tail;
  1129. enum htt_rx_mpdu_encrypt_type enctype;
  1130. struct htt_rx_desc *rxd;
  1131. enum rx_msdu_decap_format fmt;
  1132. struct ieee80211_rx_status *rx_status = &htt->rx_status;
  1133. struct ieee80211_hdr *hdr;
  1134. int ret;
  1135. bool tkip_mic_err;
  1136. bool decrypt_err;
  1137. u8 *fw_desc;
  1138. int fw_desc_len, hdrlen, paramlen;
  1139. int trim;
  1140. u32 attention = 0;
  1141. fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
  1142. fw_desc = (u8 *)frag->fw_msdu_rx_desc;
  1143. msdu_head = NULL;
  1144. msdu_tail = NULL;
  1145. spin_lock_bh(&htt->rx_ring.lock);
  1146. ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
  1147. &msdu_head, &msdu_tail,
  1148. &attention);
  1149. spin_unlock_bh(&htt->rx_ring.lock);
  1150. ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
  1151. if (ret) {
  1152. ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n",
  1153. ret);
  1154. ath10k_htt_rx_free_msdu_chain(msdu_head);
  1155. return;
  1156. }
  1157. /* FIXME: implement signal strength */
  1158. rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
  1159. hdr = (struct ieee80211_hdr *)msdu_head->data;
  1160. rxd = (void *)msdu_head->data - sizeof(*rxd);
  1161. tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
  1162. decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR);
  1163. fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
  1164. RX_MSDU_START_INFO1_DECAP_FORMAT);
  1165. if (fmt != RX_MSDU_DECAP_RAW) {
  1166. ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n");
  1167. dev_kfree_skb_any(msdu_head);
  1168. goto end;
  1169. }
  1170. enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
  1171. RX_MPDU_START_INFO0_ENCRYPT_TYPE);
  1172. ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype, fmt,
  1173. true);
  1174. msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head);
  1175. if (tkip_mic_err)
  1176. ath10k_warn(ar, "tkip mic error\n");
  1177. if (decrypt_err) {
  1178. ath10k_warn(ar, "decryption err in fragmented rx\n");
  1179. dev_kfree_skb_any(msdu_head);
  1180. goto end;
  1181. }
  1182. if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
  1183. hdrlen = ieee80211_hdrlen(hdr->frame_control);
  1184. paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype);
  1185. /* It is more efficient to move the header than the payload */
  1186. memmove((void *)msdu_head->data + paramlen,
  1187. (void *)msdu_head->data,
  1188. hdrlen);
  1189. skb_pull(msdu_head, paramlen);
  1190. hdr = (struct ieee80211_hdr *)msdu_head->data;
  1191. }
  1192. /* remove trailing FCS */
  1193. trim = 4;
  1194. /* remove crypto trailer */
  1195. trim += ath10k_htt_rx_crypto_tail_len(ar, enctype);
  1196. /* last fragment of TKIP frags has MIC */
  1197. if (!ieee80211_has_morefrags(hdr->frame_control) &&
  1198. enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
  1199. trim += 8;
  1200. if (trim > msdu_head->len) {
  1201. ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n");
  1202. dev_kfree_skb_any(msdu_head);
  1203. goto end;
  1204. }
  1205. skb_trim(msdu_head, msdu_head->len - trim);
  1206. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
  1207. msdu_head->data, msdu_head->len);
  1208. ath10k_process_rx(htt->ar, rx_status, msdu_head);
  1209. end:
  1210. if (fw_desc_len > 0) {
  1211. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1212. "expecting more fragmented rx in one indication %d\n",
  1213. fw_desc_len);
  1214. }
  1215. }
  1216. static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
  1217. struct sk_buff *skb)
  1218. {
  1219. struct ath10k_htt *htt = &ar->htt;
  1220. struct htt_resp *resp = (struct htt_resp *)skb->data;
  1221. struct htt_tx_done tx_done = {};
  1222. int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
  1223. __le16 msdu_id;
  1224. int i;
  1225. lockdep_assert_held(&htt->tx_lock);
  1226. switch (status) {
  1227. case HTT_DATA_TX_STATUS_NO_ACK:
  1228. tx_done.no_ack = true;
  1229. break;
  1230. case HTT_DATA_TX_STATUS_OK:
  1231. break;
  1232. case HTT_DATA_TX_STATUS_DISCARD:
  1233. case HTT_DATA_TX_STATUS_POSTPONE:
  1234. case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
  1235. tx_done.discard = true;
  1236. break;
  1237. default:
  1238. ath10k_warn(ar, "unhandled tx completion status %d\n", status);
  1239. tx_done.discard = true;
  1240. break;
  1241. }
  1242. ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
  1243. resp->data_tx_completion.num_msdus);
  1244. for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
  1245. msdu_id = resp->data_tx_completion.msdus[i];
  1246. tx_done.msdu_id = __le16_to_cpu(msdu_id);
  1247. ath10k_txrx_tx_unref(htt, &tx_done);
  1248. }
  1249. }
  1250. static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
  1251. {
  1252. struct htt_rx_addba *ev = &resp->rx_addba;
  1253. struct ath10k_peer *peer;
  1254. struct ath10k_vif *arvif;
  1255. u16 info0, tid, peer_id;
  1256. info0 = __le16_to_cpu(ev->info0);
  1257. tid = MS(info0, HTT_RX_BA_INFO0_TID);
  1258. peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
  1259. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1260. "htt rx addba tid %hu peer_id %hu size %hhu\n",
  1261. tid, peer_id, ev->window_size);
  1262. spin_lock_bh(&ar->data_lock);
  1263. peer = ath10k_peer_find_by_id(ar, peer_id);
  1264. if (!peer) {
  1265. ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
  1266. peer_id);
  1267. spin_unlock_bh(&ar->data_lock);
  1268. return;
  1269. }
  1270. arvif = ath10k_get_arvif(ar, peer->vdev_id);
  1271. if (!arvif) {
  1272. ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
  1273. peer->vdev_id);
  1274. spin_unlock_bh(&ar->data_lock);
  1275. return;
  1276. }
  1277. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1278. "htt rx start rx ba session sta %pM tid %hu size %hhu\n",
  1279. peer->addr, tid, ev->window_size);
  1280. ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid);
  1281. spin_unlock_bh(&ar->data_lock);
  1282. }
  1283. static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
  1284. {
  1285. struct htt_rx_delba *ev = &resp->rx_delba;
  1286. struct ath10k_peer *peer;
  1287. struct ath10k_vif *arvif;
  1288. u16 info0, tid, peer_id;
  1289. info0 = __le16_to_cpu(ev->info0);
  1290. tid = MS(info0, HTT_RX_BA_INFO0_TID);
  1291. peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
  1292. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1293. "htt rx delba tid %hu peer_id %hu\n",
  1294. tid, peer_id);
  1295. spin_lock_bh(&ar->data_lock);
  1296. peer = ath10k_peer_find_by_id(ar, peer_id);
  1297. if (!peer) {
  1298. ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
  1299. peer_id);
  1300. spin_unlock_bh(&ar->data_lock);
  1301. return;
  1302. }
  1303. arvif = ath10k_get_arvif(ar, peer->vdev_id);
  1304. if (!arvif) {
  1305. ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
  1306. peer->vdev_id);
  1307. spin_unlock_bh(&ar->data_lock);
  1308. return;
  1309. }
  1310. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1311. "htt rx stop rx ba session sta %pM tid %hu\n",
  1312. peer->addr, tid);
  1313. ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid);
  1314. spin_unlock_bh(&ar->data_lock);
  1315. }
  1316. void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
  1317. {
  1318. struct ath10k_htt *htt = &ar->htt;
  1319. struct htt_resp *resp = (struct htt_resp *)skb->data;
  1320. /* confirm alignment */
  1321. if (!IS_ALIGNED((unsigned long)skb->data, 4))
  1322. ath10k_warn(ar, "unaligned htt message, expect trouble\n");
  1323. ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
  1324. resp->hdr.msg_type);
  1325. switch (resp->hdr.msg_type) {
  1326. case HTT_T2H_MSG_TYPE_VERSION_CONF: {
  1327. htt->target_version_major = resp->ver_resp.major;
  1328. htt->target_version_minor = resp->ver_resp.minor;
  1329. complete(&htt->target_version_received);
  1330. break;
  1331. }
  1332. case HTT_T2H_MSG_TYPE_RX_IND:
  1333. spin_lock_bh(&htt->rx_ring.lock);
  1334. __skb_queue_tail(&htt->rx_compl_q, skb);
  1335. spin_unlock_bh(&htt->rx_ring.lock);
  1336. tasklet_schedule(&htt->txrx_compl_task);
  1337. return;
  1338. case HTT_T2H_MSG_TYPE_PEER_MAP: {
  1339. struct htt_peer_map_event ev = {
  1340. .vdev_id = resp->peer_map.vdev_id,
  1341. .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
  1342. };
  1343. memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
  1344. ath10k_peer_map_event(htt, &ev);
  1345. break;
  1346. }
  1347. case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
  1348. struct htt_peer_unmap_event ev = {
  1349. .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
  1350. };
  1351. ath10k_peer_unmap_event(htt, &ev);
  1352. break;
  1353. }
  1354. case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
  1355. struct htt_tx_done tx_done = {};
  1356. int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
  1357. tx_done.msdu_id =
  1358. __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
  1359. switch (status) {
  1360. case HTT_MGMT_TX_STATUS_OK:
  1361. break;
  1362. case HTT_MGMT_TX_STATUS_RETRY:
  1363. tx_done.no_ack = true;
  1364. break;
  1365. case HTT_MGMT_TX_STATUS_DROP:
  1366. tx_done.discard = true;
  1367. break;
  1368. }
  1369. spin_lock_bh(&htt->tx_lock);
  1370. ath10k_txrx_tx_unref(htt, &tx_done);
  1371. spin_unlock_bh(&htt->tx_lock);
  1372. break;
  1373. }
  1374. case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
  1375. spin_lock_bh(&htt->tx_lock);
  1376. __skb_queue_tail(&htt->tx_compl_q, skb);
  1377. spin_unlock_bh(&htt->tx_lock);
  1378. tasklet_schedule(&htt->txrx_compl_task);
  1379. return;
  1380. case HTT_T2H_MSG_TYPE_SEC_IND: {
  1381. struct ath10k *ar = htt->ar;
  1382. struct htt_security_indication *ev = &resp->security_indication;
  1383. ath10k_dbg(ar, ATH10K_DBG_HTT,
  1384. "sec ind peer_id %d unicast %d type %d\n",
  1385. __le16_to_cpu(ev->peer_id),
  1386. !!(ev->flags & HTT_SECURITY_IS_UNICAST),
  1387. MS(ev->flags, HTT_SECURITY_TYPE));
  1388. complete(&ar->install_key_done);
  1389. break;
  1390. }
  1391. case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
  1392. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
  1393. skb->data, skb->len);
  1394. ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
  1395. break;
  1396. }
  1397. case HTT_T2H_MSG_TYPE_TEST:
  1398. /* FIX THIS */
  1399. break;
  1400. case HTT_T2H_MSG_TYPE_STATS_CONF:
  1401. trace_ath10k_htt_stats(ar, skb->data, skb->len);
  1402. break;
  1403. case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
  1404. /* Firmware can return tx frames if it's unable to fully
  1405. * process them and suspects host may be able to fix it. ath10k
  1406. * sends all tx frames as already inspected so this shouldn't
  1407. * happen unless fw has a bug.
  1408. */
  1409. ath10k_warn(ar, "received an unexpected htt tx inspect event\n");
  1410. break;
  1411. case HTT_T2H_MSG_TYPE_RX_ADDBA:
  1412. ath10k_htt_rx_addba(ar, resp);
  1413. break;
  1414. case HTT_T2H_MSG_TYPE_RX_DELBA:
  1415. ath10k_htt_rx_delba(ar, resp);
  1416. break;
  1417. case HTT_T2H_MSG_TYPE_RX_FLUSH: {
  1418. /* Ignore this event because mac80211 takes care of Rx
  1419. * aggregation reordering.
  1420. */
  1421. break;
  1422. }
  1423. default:
  1424. ath10k_dbg(ar, ATH10K_DBG_HTT, "htt event (%d) not handled\n",
  1425. resp->hdr.msg_type);
  1426. ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
  1427. skb->data, skb->len);
  1428. break;
  1429. };
  1430. /* Free the indication buffer */
  1431. dev_kfree_skb_any(skb);
  1432. }
  1433. static void ath10k_htt_txrx_compl_task(unsigned long ptr)
  1434. {
  1435. struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
  1436. struct htt_resp *resp;
  1437. struct sk_buff *skb;
  1438. spin_lock_bh(&htt->tx_lock);
  1439. while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
  1440. ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
  1441. dev_kfree_skb_any(skb);
  1442. }
  1443. spin_unlock_bh(&htt->tx_lock);
  1444. spin_lock_bh(&htt->rx_ring.lock);
  1445. while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
  1446. resp = (struct htt_resp *)skb->data;
  1447. ath10k_htt_rx_handler(htt, &resp->rx_ind);
  1448. dev_kfree_skb_any(skb);
  1449. }
  1450. spin_unlock_bh(&htt->rx_ring.lock);
  1451. }