core.h 13 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580
  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef _CORE_H_
  18. #define _CORE_H_
  19. #include <linux/completion.h>
  20. #include <linux/if_ether.h>
  21. #include <linux/types.h>
  22. #include <linux/pci.h>
  23. #include <linux/uuid.h>
  24. #include <linux/time.h>
  25. #include "htt.h"
  26. #include "htc.h"
  27. #include "hw.h"
  28. #include "targaddrs.h"
  29. #include "wmi.h"
  30. #include "../ath.h"
  31. #include "../regd.h"
  32. #include "../dfs_pattern_detector.h"
  33. #include "spectral.h"
  34. #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
  35. #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
  36. #define WO(_f) ((_f##_OFFSET) >> 2)
  37. #define ATH10K_SCAN_ID 0
  38. #define WMI_READY_TIMEOUT (5 * HZ)
  39. #define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
  40. #define ATH10K_NUM_CHANS 38
  41. /* Antenna noise floor */
  42. #define ATH10K_DEFAULT_NOISE_FLOOR -95
  43. #define ATH10K_MAX_NUM_MGMT_PENDING 128
  44. /* number of failed packets */
  45. #define ATH10K_KICKOUT_THRESHOLD 50
  46. /*
  47. * Use insanely high numbers to make sure that the firmware implementation
  48. * won't start, we have the same functionality already in hostapd. Unit
  49. * is seconds.
  50. */
  51. #define ATH10K_KEEPALIVE_MIN_IDLE 3747
  52. #define ATH10K_KEEPALIVE_MAX_IDLE 3895
  53. #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
  54. struct ath10k;
  55. struct ath10k_skb_cb {
  56. dma_addr_t paddr;
  57. u8 vdev_id;
  58. struct {
  59. u8 tid;
  60. bool is_offchan;
  61. struct ath10k_htt_txbuf *txbuf;
  62. u32 txbuf_paddr;
  63. } __packed htt;
  64. struct {
  65. bool dtim_zero;
  66. bool deliver_cab;
  67. } bcn;
  68. } __packed;
  69. static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
  70. {
  71. BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
  72. IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
  73. return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
  74. }
  75. static inline u32 host_interest_item_address(u32 item_offset)
  76. {
  77. return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
  78. }
  79. struct ath10k_bmi {
  80. bool done_sent;
  81. };
  82. #define ATH10K_MAX_MEM_REQS 16
  83. struct ath10k_mem_chunk {
  84. void *vaddr;
  85. dma_addr_t paddr;
  86. u32 len;
  87. u32 req_id;
  88. };
  89. struct ath10k_wmi {
  90. enum ath10k_htc_ep_id eid;
  91. struct completion service_ready;
  92. struct completion unified_ready;
  93. wait_queue_head_t tx_credits_wq;
  94. struct wmi_cmd_map *cmd;
  95. struct wmi_vdev_param_map *vdev_param;
  96. struct wmi_pdev_param_map *pdev_param;
  97. u32 num_mem_chunks;
  98. struct ath10k_mem_chunk mem_chunks[ATH10K_MAX_MEM_REQS];
  99. };
  100. struct ath10k_peer_stat {
  101. u8 peer_macaddr[ETH_ALEN];
  102. u32 peer_rssi;
  103. u32 peer_tx_rate;
  104. u32 peer_rx_rate; /* 10x only */
  105. };
  106. struct ath10k_target_stats {
  107. /* PDEV stats */
  108. s32 ch_noise_floor;
  109. u32 tx_frame_count;
  110. u32 rx_frame_count;
  111. u32 rx_clear_count;
  112. u32 cycle_count;
  113. u32 phy_err_count;
  114. u32 chan_tx_power;
  115. u32 ack_rx_bad;
  116. u32 rts_bad;
  117. u32 rts_good;
  118. u32 fcs_bad;
  119. u32 no_beacons;
  120. u32 mib_int_count;
  121. /* PDEV TX stats */
  122. s32 comp_queued;
  123. s32 comp_delivered;
  124. s32 msdu_enqued;
  125. s32 mpdu_enqued;
  126. s32 wmm_drop;
  127. s32 local_enqued;
  128. s32 local_freed;
  129. s32 hw_queued;
  130. s32 hw_reaped;
  131. s32 underrun;
  132. s32 tx_abort;
  133. s32 mpdus_requed;
  134. u32 tx_ko;
  135. u32 data_rc;
  136. u32 self_triggers;
  137. u32 sw_retry_failure;
  138. u32 illgl_rate_phy_err;
  139. u32 pdev_cont_xretry;
  140. u32 pdev_tx_timeout;
  141. u32 pdev_resets;
  142. u32 phy_underrun;
  143. u32 txop_ovf;
  144. /* PDEV RX stats */
  145. s32 mid_ppdu_route_change;
  146. s32 status_rcvd;
  147. s32 r0_frags;
  148. s32 r1_frags;
  149. s32 r2_frags;
  150. s32 r3_frags;
  151. s32 htt_msdus;
  152. s32 htt_mpdus;
  153. s32 loc_msdus;
  154. s32 loc_mpdus;
  155. s32 oversize_amsdu;
  156. s32 phy_errs;
  157. s32 phy_err_drop;
  158. s32 mpdu_errs;
  159. /* VDEV STATS */
  160. /* PEER STATS */
  161. u8 peers;
  162. struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];
  163. /* TODO: Beacon filter stats */
  164. };
  165. struct ath10k_dfs_stats {
  166. u32 phy_errors;
  167. u32 pulses_total;
  168. u32 pulses_detected;
  169. u32 pulses_discarded;
  170. u32 radar_detected;
  171. };
  172. #define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
  173. struct ath10k_peer {
  174. struct list_head list;
  175. int vdev_id;
  176. u8 addr[ETH_ALEN];
  177. DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
  178. struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
  179. };
  180. struct ath10k_sta {
  181. struct ath10k_vif *arvif;
  182. /* the following are protected by ar->data_lock */
  183. u32 changed; /* IEEE80211_RC_* */
  184. u32 bw;
  185. u32 nss;
  186. u32 smps;
  187. struct work_struct update_wk;
  188. };
  189. #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
  190. struct ath10k_vif {
  191. struct list_head list;
  192. u32 vdev_id;
  193. enum wmi_vdev_type vdev_type;
  194. enum wmi_vdev_subtype vdev_subtype;
  195. u32 beacon_interval;
  196. u32 dtim_period;
  197. struct sk_buff *beacon;
  198. /* protected by data_lock */
  199. bool beacon_sent;
  200. struct ath10k *ar;
  201. struct ieee80211_vif *vif;
  202. bool is_started;
  203. bool is_up;
  204. bool spectral_enabled;
  205. u32 aid;
  206. u8 bssid[ETH_ALEN];
  207. struct work_struct wep_key_work;
  208. struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
  209. u8 def_wep_key_idx;
  210. u8 def_wep_key_newidx;
  211. u16 tx_seq_no;
  212. union {
  213. struct {
  214. u32 uapsd;
  215. } sta;
  216. struct {
  217. /* 127 stations; wmi limit */
  218. u8 tim_bitmap[16];
  219. u8 tim_len;
  220. u32 ssid_len;
  221. u8 ssid[IEEE80211_MAX_SSID_LEN];
  222. bool hidden_ssid;
  223. /* P2P_IE with NoA attribute for P2P_GO case */
  224. u32 noa_len;
  225. u8 *noa_data;
  226. } ap;
  227. } u;
  228. u8 fixed_rate;
  229. u8 fixed_nss;
  230. u8 force_sgi;
  231. bool use_cts_prot;
  232. int num_legacy_stations;
  233. };
  234. struct ath10k_vif_iter {
  235. u32 vdev_id;
  236. struct ath10k_vif *arvif;
  237. };
  238. /* used for crash-dump storage, protected by data-lock */
  239. struct ath10k_fw_crash_data {
  240. bool crashed_since_read;
  241. uuid_le uuid;
  242. struct timespec timestamp;
  243. __le32 registers[REG_DUMP_COUNT_QCA988X];
  244. };
  245. struct ath10k_debug {
  246. struct dentry *debugfs_phy;
  247. struct ath10k_target_stats target_stats;
  248. DECLARE_BITMAP(wmi_service_bitmap, WMI_SERVICE_MAX);
  249. struct completion event_stats_compl;
  250. unsigned long htt_stats_mask;
  251. struct delayed_work htt_stats_dwork;
  252. struct ath10k_dfs_stats dfs_stats;
  253. struct ath_dfs_pool_stats dfs_pool_stats;
  254. u32 fw_dbglog_mask;
  255. u8 htt_max_amsdu;
  256. u8 htt_max_ampdu;
  257. struct ath10k_fw_crash_data *fw_crash_data;
  258. };
  259. enum ath10k_state {
  260. ATH10K_STATE_OFF = 0,
  261. ATH10K_STATE_ON,
  262. /* When doing firmware recovery the device is first powered down.
  263. * mac80211 is supposed to call in to start() hook later on. It is
  264. * however possible that driver unloading and firmware crash overlap.
  265. * mac80211 can wait on conf_mutex in stop() while the device is
  266. * stopped in ath10k_core_restart() work holding conf_mutex. The state
  267. * RESTARTED means that the device is up and mac80211 has started hw
  268. * reconfiguration. Once mac80211 is done with the reconfiguration we
  269. * set the state to STATE_ON in restart_complete(). */
  270. ATH10K_STATE_RESTARTING,
  271. ATH10K_STATE_RESTARTED,
  272. /* The device has crashed while restarting hw. This state is like ON
  273. * but commands are blocked in HTC and -ECOMM response is given. This
  274. * prevents completion timeouts and makes the driver more responsive to
  275. * userspace commands. This is also prevents recursive recovery. */
  276. ATH10K_STATE_WEDGED,
  277. /* factory tests */
  278. ATH10K_STATE_UTF,
  279. };
  280. enum ath10k_firmware_mode {
  281. /* the default mode, standard 802.11 functionality */
  282. ATH10K_FIRMWARE_MODE_NORMAL,
  283. /* factory tests etc */
  284. ATH10K_FIRMWARE_MODE_UTF,
  285. };
  286. enum ath10k_fw_features {
  287. /* wmi_mgmt_rx_hdr contains extra RSSI information */
  288. ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
  289. /* firmware from 10X branch */
  290. ATH10K_FW_FEATURE_WMI_10X = 1,
  291. /* firmware support tx frame management over WMI, otherwise it's HTT */
  292. ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
  293. /* Firmware does not support P2P */
  294. ATH10K_FW_FEATURE_NO_P2P = 3,
  295. /* Firmware 10.2 feature bit. The ATH10K_FW_FEATURE_WMI_10X feature bit
  296. * is required to be set as well.
  297. */
  298. ATH10K_FW_FEATURE_WMI_10_2 = 4,
  299. /* keep last */
  300. ATH10K_FW_FEATURE_COUNT,
  301. };
  302. enum ath10k_dev_flags {
  303. /* Indicates that ath10k device is during CAC phase of DFS */
  304. ATH10K_CAC_RUNNING,
  305. ATH10K_FLAG_CORE_REGISTERED,
  306. };
  307. enum ath10k_scan_state {
  308. ATH10K_SCAN_IDLE,
  309. ATH10K_SCAN_STARTING,
  310. ATH10K_SCAN_RUNNING,
  311. ATH10K_SCAN_ABORTING,
  312. };
  313. static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
  314. {
  315. switch (state) {
  316. case ATH10K_SCAN_IDLE:
  317. return "idle";
  318. case ATH10K_SCAN_STARTING:
  319. return "starting";
  320. case ATH10K_SCAN_RUNNING:
  321. return "running";
  322. case ATH10K_SCAN_ABORTING:
  323. return "aborting";
  324. }
  325. return "unknown";
  326. }
  327. struct ath10k {
  328. struct ath_common ath_common;
  329. struct ieee80211_hw *hw;
  330. struct device *dev;
  331. u8 mac_addr[ETH_ALEN];
  332. u32 chip_id;
  333. u32 target_version;
  334. u8 fw_version_major;
  335. u32 fw_version_minor;
  336. u16 fw_version_release;
  337. u16 fw_version_build;
  338. u32 phy_capability;
  339. u32 hw_min_tx_power;
  340. u32 hw_max_tx_power;
  341. u32 ht_cap_info;
  342. u32 vht_cap_info;
  343. u32 num_rf_chains;
  344. DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
  345. struct targetdef *targetdef;
  346. struct hostdef *hostdef;
  347. bool p2p;
  348. struct {
  349. const struct ath10k_hif_ops *ops;
  350. } hif;
  351. struct completion target_suspend;
  352. struct ath10k_bmi bmi;
  353. struct ath10k_wmi wmi;
  354. struct ath10k_htc htc;
  355. struct ath10k_htt htt;
  356. struct ath10k_hw_params {
  357. u32 id;
  358. const char *name;
  359. u32 patch_load_addr;
  360. struct ath10k_hw_params_fw {
  361. const char *dir;
  362. const char *fw;
  363. const char *otp;
  364. const char *board;
  365. } fw;
  366. } hw_params;
  367. const struct firmware *board;
  368. const void *board_data;
  369. size_t board_len;
  370. const struct firmware *otp;
  371. const void *otp_data;
  372. size_t otp_len;
  373. const struct firmware *firmware;
  374. const void *firmware_data;
  375. size_t firmware_len;
  376. int fw_api;
  377. struct {
  378. struct completion started;
  379. struct completion completed;
  380. struct completion on_channel;
  381. struct delayed_work timeout;
  382. enum ath10k_scan_state state;
  383. bool is_roc;
  384. int vdev_id;
  385. int roc_freq;
  386. } scan;
  387. struct {
  388. struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
  389. } mac;
  390. /* should never be NULL; needed for regular htt rx */
  391. struct ieee80211_channel *rx_channel;
  392. /* valid during scan; needed for mgmt rx during scan */
  393. struct ieee80211_channel *scan_channel;
  394. /* current operating channel definition */
  395. struct cfg80211_chan_def chandef;
  396. int free_vdev_map;
  397. bool monitor;
  398. int monitor_vdev_id;
  399. bool monitor_started;
  400. unsigned int filter_flags;
  401. unsigned long dev_flags;
  402. u32 dfs_block_radar_events;
  403. /* protected by conf_mutex */
  404. bool radar_enabled;
  405. int num_started_vdevs;
  406. /* Protected by conf-mutex */
  407. u8 supp_tx_chainmask;
  408. u8 supp_rx_chainmask;
  409. u8 cfg_tx_chainmask;
  410. u8 cfg_rx_chainmask;
  411. struct wmi_pdev_set_wmm_params_arg wmm_params;
  412. struct completion install_key_done;
  413. struct completion vdev_setup_done;
  414. struct workqueue_struct *workqueue;
  415. /* prevents concurrent FW reconfiguration */
  416. struct mutex conf_mutex;
  417. /* protects shared structure data */
  418. spinlock_t data_lock;
  419. struct list_head arvifs;
  420. struct list_head peers;
  421. wait_queue_head_t peer_mapping_wq;
  422. /* number of created peers; protected by data_lock */
  423. int num_peers;
  424. struct work_struct offchan_tx_work;
  425. struct sk_buff_head offchan_tx_queue;
  426. struct completion offchan_tx_completed;
  427. struct sk_buff *offchan_tx_skb;
  428. struct work_struct wmi_mgmt_tx_work;
  429. struct sk_buff_head wmi_mgmt_tx_queue;
  430. enum ath10k_state state;
  431. struct work_struct register_work;
  432. struct work_struct restart_work;
  433. /* cycle count is reported twice for each visited channel during scan.
  434. * access protected by data_lock */
  435. u32 survey_last_rx_clear_count;
  436. u32 survey_last_cycle_count;
  437. struct survey_info survey[ATH10K_NUM_CHANS];
  438. struct dfs_pattern_detector *dfs_detector;
  439. #ifdef CONFIG_ATH10K_DEBUGFS
  440. struct ath10k_debug debug;
  441. #endif
  442. struct {
  443. /* relay(fs) channel for spectral scan */
  444. struct rchan *rfs_chan_spec_scan;
  445. /* spectral_mode and spec_config are protected by conf_mutex */
  446. enum ath10k_spectral_mode mode;
  447. struct ath10k_spec_scan config;
  448. } spectral;
  449. struct {
  450. /* protected by conf_mutex */
  451. const struct firmware *utf;
  452. DECLARE_BITMAP(orig_fw_features, ATH10K_FW_FEATURE_COUNT);
  453. /* protected by data_lock */
  454. bool utf_monitor;
  455. } testmode;
  456. /* must be last */
  457. u8 drv_priv[0] __aligned(sizeof(void *));
  458. };
  459. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  460. const struct ath10k_hif_ops *hif_ops);
  461. void ath10k_core_destroy(struct ath10k *ar);
  462. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode);
  463. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
  464. void ath10k_core_stop(struct ath10k *ar);
  465. int ath10k_core_register(struct ath10k *ar, u32 chip_id);
  466. void ath10k_core_unregister(struct ath10k *ar);
  467. #endif /* _CORE_H_ */