net_driver.h 54 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2013 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. /* Common definitions for all Efx net driver code */
  11. #ifndef EFX_NET_DRIVER_H
  12. #define EFX_NET_DRIVER_H
  13. #include <linux/netdevice.h>
  14. #include <linux/etherdevice.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/if_vlan.h>
  17. #include <linux/timer.h>
  18. #include <linux/mdio.h>
  19. #include <linux/list.h>
  20. #include <linux/pci.h>
  21. #include <linux/device.h>
  22. #include <linux/highmem.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/mutex.h>
  25. #include <linux/vmalloc.h>
  26. #include <linux/i2c.h>
  27. #include <linux/mtd/mtd.h>
  28. #include <net/busy_poll.h>
  29. #include "enum.h"
  30. #include "bitfield.h"
  31. #include "filter.h"
  32. /**************************************************************************
  33. *
  34. * Build definitions
  35. *
  36. **************************************************************************/
  37. #define EFX_DRIVER_VERSION "4.0"
  38. #ifdef DEBUG
  39. #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  40. #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  41. #else
  42. #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  43. #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  44. #endif
  45. /**************************************************************************
  46. *
  47. * Efx data structures
  48. *
  49. **************************************************************************/
  50. #define EFX_MAX_CHANNELS 32U
  51. #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
  52. #define EFX_EXTRA_CHANNEL_IOV 0
  53. #define EFX_EXTRA_CHANNEL_PTP 1
  54. #define EFX_MAX_EXTRA_CHANNELS 2U
  55. /* Checksum generation is a per-queue option in hardware, so each
  56. * queue visible to the networking core is backed by two hardware TX
  57. * queues. */
  58. #define EFX_MAX_TX_TC 2
  59. #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
  60. #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
  61. #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
  62. #define EFX_TXQ_TYPES 4
  63. #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
  64. /* Maximum possible MTU the driver supports */
  65. #define EFX_MAX_MTU (9 * 1024)
  66. /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
  67. * and should be a multiple of the cache line size.
  68. */
  69. #define EFX_RX_USR_BUF_SIZE (2048 - 256)
  70. /* If possible, we should ensure cache line alignment at start and end
  71. * of every buffer. Otherwise, we just need to ensure 4-byte
  72. * alignment of the network header.
  73. */
  74. #if NET_IP_ALIGN == 0
  75. #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
  76. #else
  77. #define EFX_RX_BUF_ALIGNMENT 4
  78. #endif
  79. /* Forward declare Precision Time Protocol (PTP) support structure. */
  80. struct efx_ptp_data;
  81. struct hwtstamp_config;
  82. struct efx_self_tests;
  83. /**
  84. * struct efx_buffer - A general-purpose DMA buffer
  85. * @addr: host base address of the buffer
  86. * @dma_addr: DMA base address of the buffer
  87. * @len: Buffer length, in bytes
  88. *
  89. * The NIC uses these buffers for its interrupt status registers and
  90. * MAC stats dumps.
  91. */
  92. struct efx_buffer {
  93. void *addr;
  94. dma_addr_t dma_addr;
  95. unsigned int len;
  96. };
  97. /**
  98. * struct efx_special_buffer - DMA buffer entered into buffer table
  99. * @buf: Standard &struct efx_buffer
  100. * @index: Buffer index within controller;s buffer table
  101. * @entries: Number of buffer table entries
  102. *
  103. * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
  104. * Event and descriptor rings are addressed via one or more buffer
  105. * table entries (and so can be physically non-contiguous, although we
  106. * currently do not take advantage of that). On Falcon and Siena we
  107. * have to take care of allocating and initialising the entries
  108. * ourselves. On later hardware this is managed by the firmware and
  109. * @index and @entries are left as 0.
  110. */
  111. struct efx_special_buffer {
  112. struct efx_buffer buf;
  113. unsigned int index;
  114. unsigned int entries;
  115. };
  116. /**
  117. * struct efx_tx_buffer - buffer state for a TX descriptor
  118. * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
  119. * freed when descriptor completes
  120. * @heap_buf: When @flags & %EFX_TX_BUF_HEAP, the associated heap buffer to be
  121. * freed when descriptor completes.
  122. * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
  123. * @dma_addr: DMA address of the fragment.
  124. * @flags: Flags for allocation and DMA mapping type
  125. * @len: Length of this fragment.
  126. * This field is zero when the queue slot is empty.
  127. * @unmap_len: Length of this fragment to unmap
  128. * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
  129. * Only valid if @unmap_len != 0.
  130. */
  131. struct efx_tx_buffer {
  132. union {
  133. const struct sk_buff *skb;
  134. void *heap_buf;
  135. };
  136. union {
  137. efx_qword_t option;
  138. dma_addr_t dma_addr;
  139. };
  140. unsigned short flags;
  141. unsigned short len;
  142. unsigned short unmap_len;
  143. unsigned short dma_offset;
  144. };
  145. #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
  146. #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
  147. #define EFX_TX_BUF_HEAP 4 /* buffer was allocated with kmalloc() */
  148. #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
  149. #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
  150. /**
  151. * struct efx_tx_queue - An Efx TX queue
  152. *
  153. * This is a ring buffer of TX fragments.
  154. * Since the TX completion path always executes on the same
  155. * CPU and the xmit path can operate on different CPUs,
  156. * performance is increased by ensuring that the completion
  157. * path and the xmit path operate on different cache lines.
  158. * This is particularly important if the xmit path is always
  159. * executing on one CPU which is different from the completion
  160. * path. There is also a cache line for members which are
  161. * read but not written on the fast path.
  162. *
  163. * @efx: The associated Efx NIC
  164. * @queue: DMA queue number
  165. * @channel: The associated channel
  166. * @core_txq: The networking core TX queue structure
  167. * @buffer: The software buffer ring
  168. * @tsoh_page: Array of pages of TSO header buffers
  169. * @txd: The hardware descriptor ring
  170. * @ptr_mask: The size of the ring minus 1.
  171. * @piobuf: PIO buffer region for this TX queue (shared with its partner).
  172. * Size of the region is efx_piobuf_size.
  173. * @piobuf_offset: Buffer offset to be specified in PIO descriptors
  174. * @initialised: Has hardware queue been initialised?
  175. * @read_count: Current read pointer.
  176. * This is the number of buffers that have been removed from both rings.
  177. * @old_write_count: The value of @write_count when last checked.
  178. * This is here for performance reasons. The xmit path will
  179. * only get the up-to-date value of @write_count if this
  180. * variable indicates that the queue is empty. This is to
  181. * avoid cache-line ping-pong between the xmit path and the
  182. * completion path.
  183. * @merge_events: Number of TX merged completion events
  184. * @insert_count: Current insert pointer
  185. * This is the number of buffers that have been added to the
  186. * software ring.
  187. * @write_count: Current write pointer
  188. * This is the number of buffers that have been added to the
  189. * hardware ring.
  190. * @old_read_count: The value of read_count when last checked.
  191. * This is here for performance reasons. The xmit path will
  192. * only get the up-to-date value of read_count if this
  193. * variable indicates that the queue is full. This is to
  194. * avoid cache-line ping-pong between the xmit path and the
  195. * completion path.
  196. * @tso_bursts: Number of times TSO xmit invoked by kernel
  197. * @tso_long_headers: Number of packets with headers too long for standard
  198. * blocks
  199. * @tso_packets: Number of packets via the TSO xmit path
  200. * @pushes: Number of times the TX push feature has been used
  201. * @pio_packets: Number of times the TX PIO feature has been used
  202. * @empty_read_count: If the completion path has seen the queue as empty
  203. * and the transmission path has not yet checked this, the value of
  204. * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
  205. */
  206. struct efx_tx_queue {
  207. /* Members which don't change on the fast path */
  208. struct efx_nic *efx ____cacheline_aligned_in_smp;
  209. unsigned queue;
  210. struct efx_channel *channel;
  211. struct netdev_queue *core_txq;
  212. struct efx_tx_buffer *buffer;
  213. struct efx_buffer *tsoh_page;
  214. struct efx_special_buffer txd;
  215. unsigned int ptr_mask;
  216. void __iomem *piobuf;
  217. unsigned int piobuf_offset;
  218. bool initialised;
  219. /* Members used mainly on the completion path */
  220. unsigned int read_count ____cacheline_aligned_in_smp;
  221. unsigned int old_write_count;
  222. unsigned int merge_events;
  223. /* Members used only on the xmit path */
  224. unsigned int insert_count ____cacheline_aligned_in_smp;
  225. unsigned int write_count;
  226. unsigned int old_read_count;
  227. unsigned int tso_bursts;
  228. unsigned int tso_long_headers;
  229. unsigned int tso_packets;
  230. unsigned int pushes;
  231. unsigned int pio_packets;
  232. /* Statistics to supplement MAC stats */
  233. unsigned long tx_packets;
  234. /* Members shared between paths and sometimes updated */
  235. unsigned int empty_read_count ____cacheline_aligned_in_smp;
  236. #define EFX_EMPTY_COUNT_VALID 0x80000000
  237. atomic_t flush_outstanding;
  238. };
  239. /**
  240. * struct efx_rx_buffer - An Efx RX data buffer
  241. * @dma_addr: DMA base address of the buffer
  242. * @page: The associated page buffer.
  243. * Will be %NULL if the buffer slot is currently free.
  244. * @page_offset: If pending: offset in @page of DMA base address.
  245. * If completed: offset in @page of Ethernet header.
  246. * @len: If pending: length for DMA descriptor.
  247. * If completed: received length, excluding hash prefix.
  248. * @flags: Flags for buffer and packet state. These are only set on the
  249. * first buffer of a scattered packet.
  250. */
  251. struct efx_rx_buffer {
  252. dma_addr_t dma_addr;
  253. struct page *page;
  254. u16 page_offset;
  255. u16 len;
  256. u16 flags;
  257. };
  258. #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
  259. #define EFX_RX_PKT_CSUMMED 0x0002
  260. #define EFX_RX_PKT_DISCARD 0x0004
  261. #define EFX_RX_PKT_TCP 0x0040
  262. #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
  263. /**
  264. * struct efx_rx_page_state - Page-based rx buffer state
  265. *
  266. * Inserted at the start of every page allocated for receive buffers.
  267. * Used to facilitate sharing dma mappings between recycled rx buffers
  268. * and those passed up to the kernel.
  269. *
  270. * @dma_addr: The dma address of this page.
  271. */
  272. struct efx_rx_page_state {
  273. dma_addr_t dma_addr;
  274. unsigned int __pad[0] ____cacheline_aligned;
  275. };
  276. /**
  277. * struct efx_rx_queue - An Efx RX queue
  278. * @efx: The associated Efx NIC
  279. * @core_index: Index of network core RX queue. Will be >= 0 iff this
  280. * is associated with a real RX queue.
  281. * @buffer: The software buffer ring
  282. * @rxd: The hardware descriptor ring
  283. * @ptr_mask: The size of the ring minus 1.
  284. * @refill_enabled: Enable refill whenever fill level is low
  285. * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
  286. * @rxq_flush_pending.
  287. * @added_count: Number of buffers added to the receive queue.
  288. * @notified_count: Number of buffers given to NIC (<= @added_count).
  289. * @removed_count: Number of buffers removed from the receive queue.
  290. * @scatter_n: Used by NIC specific receive code.
  291. * @scatter_len: Used by NIC specific receive code.
  292. * @page_ring: The ring to store DMA mapped pages for reuse.
  293. * @page_add: Counter to calculate the write pointer for the recycle ring.
  294. * @page_remove: Counter to calculate the read pointer for the recycle ring.
  295. * @page_recycle_count: The number of pages that have been recycled.
  296. * @page_recycle_failed: The number of pages that couldn't be recycled because
  297. * the kernel still held a reference to them.
  298. * @page_recycle_full: The number of pages that were released because the
  299. * recycle ring was full.
  300. * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
  301. * @max_fill: RX descriptor maximum fill level (<= ring size)
  302. * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
  303. * (<= @max_fill)
  304. * @min_fill: RX descriptor minimum non-zero fill level.
  305. * This records the minimum fill level observed when a ring
  306. * refill was triggered.
  307. * @recycle_count: RX buffer recycle counter.
  308. * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
  309. */
  310. struct efx_rx_queue {
  311. struct efx_nic *efx;
  312. int core_index;
  313. struct efx_rx_buffer *buffer;
  314. struct efx_special_buffer rxd;
  315. unsigned int ptr_mask;
  316. bool refill_enabled;
  317. bool flush_pending;
  318. unsigned int added_count;
  319. unsigned int notified_count;
  320. unsigned int removed_count;
  321. unsigned int scatter_n;
  322. unsigned int scatter_len;
  323. struct page **page_ring;
  324. unsigned int page_add;
  325. unsigned int page_remove;
  326. unsigned int page_recycle_count;
  327. unsigned int page_recycle_failed;
  328. unsigned int page_recycle_full;
  329. unsigned int page_ptr_mask;
  330. unsigned int max_fill;
  331. unsigned int fast_fill_trigger;
  332. unsigned int min_fill;
  333. unsigned int min_overfill;
  334. unsigned int recycle_count;
  335. struct timer_list slow_fill;
  336. unsigned int slow_fill_count;
  337. /* Statistics to supplement MAC stats */
  338. unsigned long rx_packets;
  339. };
  340. enum efx_sync_events_state {
  341. SYNC_EVENTS_DISABLED = 0,
  342. SYNC_EVENTS_QUIESCENT,
  343. SYNC_EVENTS_REQUESTED,
  344. SYNC_EVENTS_VALID,
  345. };
  346. /**
  347. * struct efx_channel - An Efx channel
  348. *
  349. * A channel comprises an event queue, at least one TX queue, at least
  350. * one RX queue, and an associated tasklet for processing the event
  351. * queue.
  352. *
  353. * @efx: Associated Efx NIC
  354. * @channel: Channel instance number
  355. * @type: Channel type definition
  356. * @eventq_init: Event queue initialised flag
  357. * @enabled: Channel enabled indicator
  358. * @irq: IRQ number (MSI and MSI-X only)
  359. * @irq_moderation: IRQ moderation value (in hardware ticks)
  360. * @napi_dev: Net device used with NAPI
  361. * @napi_str: NAPI control structure
  362. * @state: state for NAPI vs busy polling
  363. * @state_lock: lock protecting @state
  364. * @eventq: Event queue buffer
  365. * @eventq_mask: Event queue pointer mask
  366. * @eventq_read_ptr: Event queue read pointer
  367. * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
  368. * @irq_count: Number of IRQs since last adaptive moderation decision
  369. * @irq_mod_score: IRQ moderation score
  370. * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
  371. * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
  372. * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
  373. * @n_rx_mcast_mismatch: Count of unmatched multicast frames
  374. * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
  375. * @n_rx_overlength: Count of RX_OVERLENGTH errors
  376. * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
  377. * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
  378. * lack of descriptors
  379. * @n_rx_merge_events: Number of RX merged completion events
  380. * @n_rx_merge_packets: Number of RX packets completed by merged events
  381. * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
  382. * __efx_rx_packet(), or zero if there is none
  383. * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
  384. * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
  385. * @rx_queue: RX queue for this channel
  386. * @tx_queue: TX queues for this channel
  387. * @sync_events_state: Current state of sync events on this channel
  388. * @sync_timestamp_major: Major part of the last ptp sync event
  389. * @sync_timestamp_minor: Minor part of the last ptp sync event
  390. */
  391. struct efx_channel {
  392. struct efx_nic *efx;
  393. int channel;
  394. const struct efx_channel_type *type;
  395. bool eventq_init;
  396. bool enabled;
  397. int irq;
  398. unsigned int irq_moderation;
  399. struct net_device *napi_dev;
  400. struct napi_struct napi_str;
  401. #ifdef CONFIG_NET_RX_BUSY_POLL
  402. unsigned int state;
  403. spinlock_t state_lock;
  404. #define EFX_CHANNEL_STATE_IDLE 0
  405. #define EFX_CHANNEL_STATE_NAPI (1 << 0) /* NAPI owns this channel */
  406. #define EFX_CHANNEL_STATE_POLL (1 << 1) /* poll owns this channel */
  407. #define EFX_CHANNEL_STATE_DISABLED (1 << 2) /* channel is disabled */
  408. #define EFX_CHANNEL_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this channel */
  409. #define EFX_CHANNEL_STATE_POLL_YIELD (1 << 4) /* poll yielded this channel */
  410. #define EFX_CHANNEL_OWNED \
  411. (EFX_CHANNEL_STATE_NAPI | EFX_CHANNEL_STATE_POLL)
  412. #define EFX_CHANNEL_LOCKED \
  413. (EFX_CHANNEL_OWNED | EFX_CHANNEL_STATE_DISABLED)
  414. #define EFX_CHANNEL_USER_PEND \
  415. (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_POLL_YIELD)
  416. #endif /* CONFIG_NET_RX_BUSY_POLL */
  417. struct efx_special_buffer eventq;
  418. unsigned int eventq_mask;
  419. unsigned int eventq_read_ptr;
  420. int event_test_cpu;
  421. unsigned int irq_count;
  422. unsigned int irq_mod_score;
  423. #ifdef CONFIG_RFS_ACCEL
  424. unsigned int rfs_filters_added;
  425. #endif
  426. unsigned n_rx_tobe_disc;
  427. unsigned n_rx_ip_hdr_chksum_err;
  428. unsigned n_rx_tcp_udp_chksum_err;
  429. unsigned n_rx_mcast_mismatch;
  430. unsigned n_rx_frm_trunc;
  431. unsigned n_rx_overlength;
  432. unsigned n_skbuff_leaks;
  433. unsigned int n_rx_nodesc_trunc;
  434. unsigned int n_rx_merge_events;
  435. unsigned int n_rx_merge_packets;
  436. unsigned int rx_pkt_n_frags;
  437. unsigned int rx_pkt_index;
  438. struct efx_rx_queue rx_queue;
  439. struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
  440. enum efx_sync_events_state sync_events_state;
  441. u32 sync_timestamp_major;
  442. u32 sync_timestamp_minor;
  443. };
  444. #ifdef CONFIG_NET_RX_BUSY_POLL
  445. static inline void efx_channel_init_lock(struct efx_channel *channel)
  446. {
  447. spin_lock_init(&channel->state_lock);
  448. }
  449. /* Called from the device poll routine to get ownership of a channel. */
  450. static inline bool efx_channel_lock_napi(struct efx_channel *channel)
  451. {
  452. bool rc = true;
  453. spin_lock_bh(&channel->state_lock);
  454. if (channel->state & EFX_CHANNEL_LOCKED) {
  455. WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI);
  456. channel->state |= EFX_CHANNEL_STATE_NAPI_YIELD;
  457. rc = false;
  458. } else {
  459. /* we don't care if someone yielded */
  460. channel->state = EFX_CHANNEL_STATE_NAPI;
  461. }
  462. spin_unlock_bh(&channel->state_lock);
  463. return rc;
  464. }
  465. static inline void efx_channel_unlock_napi(struct efx_channel *channel)
  466. {
  467. spin_lock_bh(&channel->state_lock);
  468. WARN_ON(channel->state &
  469. (EFX_CHANNEL_STATE_POLL | EFX_CHANNEL_STATE_NAPI_YIELD));
  470. channel->state &= EFX_CHANNEL_STATE_DISABLED;
  471. spin_unlock_bh(&channel->state_lock);
  472. }
  473. /* Called from efx_busy_poll(). */
  474. static inline bool efx_channel_lock_poll(struct efx_channel *channel)
  475. {
  476. bool rc = true;
  477. spin_lock_bh(&channel->state_lock);
  478. if ((channel->state & EFX_CHANNEL_LOCKED)) {
  479. channel->state |= EFX_CHANNEL_STATE_POLL_YIELD;
  480. rc = false;
  481. } else {
  482. /* preserve yield marks */
  483. channel->state |= EFX_CHANNEL_STATE_POLL;
  484. }
  485. spin_unlock_bh(&channel->state_lock);
  486. return rc;
  487. }
  488. /* Returns true if NAPI tried to get the channel while it was locked. */
  489. static inline void efx_channel_unlock_poll(struct efx_channel *channel)
  490. {
  491. spin_lock_bh(&channel->state_lock);
  492. WARN_ON(channel->state & EFX_CHANNEL_STATE_NAPI);
  493. /* will reset state to idle, unless channel is disabled */
  494. channel->state &= EFX_CHANNEL_STATE_DISABLED;
  495. spin_unlock_bh(&channel->state_lock);
  496. }
  497. /* True if a socket is polling, even if it did not get the lock. */
  498. static inline bool efx_channel_busy_polling(struct efx_channel *channel)
  499. {
  500. WARN_ON(!(channel->state & EFX_CHANNEL_OWNED));
  501. return channel->state & EFX_CHANNEL_USER_PEND;
  502. }
  503. static inline void efx_channel_enable(struct efx_channel *channel)
  504. {
  505. spin_lock_bh(&channel->state_lock);
  506. channel->state = EFX_CHANNEL_STATE_IDLE;
  507. spin_unlock_bh(&channel->state_lock);
  508. }
  509. /* False if the channel is currently owned. */
  510. static inline bool efx_channel_disable(struct efx_channel *channel)
  511. {
  512. bool rc = true;
  513. spin_lock_bh(&channel->state_lock);
  514. if (channel->state & EFX_CHANNEL_OWNED)
  515. rc = false;
  516. channel->state |= EFX_CHANNEL_STATE_DISABLED;
  517. spin_unlock_bh(&channel->state_lock);
  518. return rc;
  519. }
  520. #else /* CONFIG_NET_RX_BUSY_POLL */
  521. static inline void efx_channel_init_lock(struct efx_channel *channel)
  522. {
  523. }
  524. static inline bool efx_channel_lock_napi(struct efx_channel *channel)
  525. {
  526. return true;
  527. }
  528. static inline void efx_channel_unlock_napi(struct efx_channel *channel)
  529. {
  530. }
  531. static inline bool efx_channel_lock_poll(struct efx_channel *channel)
  532. {
  533. return false;
  534. }
  535. static inline void efx_channel_unlock_poll(struct efx_channel *channel)
  536. {
  537. }
  538. static inline bool efx_channel_busy_polling(struct efx_channel *channel)
  539. {
  540. return false;
  541. }
  542. static inline void efx_channel_enable(struct efx_channel *channel)
  543. {
  544. }
  545. static inline bool efx_channel_disable(struct efx_channel *channel)
  546. {
  547. return true;
  548. }
  549. #endif /* CONFIG_NET_RX_BUSY_POLL */
  550. /**
  551. * struct efx_msi_context - Context for each MSI
  552. * @efx: The associated NIC
  553. * @index: Index of the channel/IRQ
  554. * @name: Name of the channel/IRQ
  555. *
  556. * Unlike &struct efx_channel, this is never reallocated and is always
  557. * safe for the IRQ handler to access.
  558. */
  559. struct efx_msi_context {
  560. struct efx_nic *efx;
  561. unsigned int index;
  562. char name[IFNAMSIZ + 6];
  563. };
  564. /**
  565. * struct efx_channel_type - distinguishes traffic and extra channels
  566. * @handle_no_channel: Handle failure to allocate an extra channel
  567. * @pre_probe: Set up extra state prior to initialisation
  568. * @post_remove: Tear down extra state after finalisation, if allocated.
  569. * May be called on channels that have not been probed.
  570. * @get_name: Generate the channel's name (used for its IRQ handler)
  571. * @copy: Copy the channel state prior to reallocation. May be %NULL if
  572. * reallocation is not supported.
  573. * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
  574. * @keep_eventq: Flag for whether event queue should be kept initialised
  575. * while the device is stopped
  576. */
  577. struct efx_channel_type {
  578. void (*handle_no_channel)(struct efx_nic *);
  579. int (*pre_probe)(struct efx_channel *);
  580. void (*post_remove)(struct efx_channel *);
  581. void (*get_name)(struct efx_channel *, char *buf, size_t len);
  582. struct efx_channel *(*copy)(const struct efx_channel *);
  583. bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
  584. bool keep_eventq;
  585. };
  586. enum efx_led_mode {
  587. EFX_LED_OFF = 0,
  588. EFX_LED_ON = 1,
  589. EFX_LED_DEFAULT = 2
  590. };
  591. #define STRING_TABLE_LOOKUP(val, member) \
  592. ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
  593. extern const char *const efx_loopback_mode_names[];
  594. extern const unsigned int efx_loopback_mode_max;
  595. #define LOOPBACK_MODE(efx) \
  596. STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
  597. extern const char *const efx_reset_type_names[];
  598. extern const unsigned int efx_reset_type_max;
  599. #define RESET_TYPE(type) \
  600. STRING_TABLE_LOOKUP(type, efx_reset_type)
  601. enum efx_int_mode {
  602. /* Be careful if altering to correct macro below */
  603. EFX_INT_MODE_MSIX = 0,
  604. EFX_INT_MODE_MSI = 1,
  605. EFX_INT_MODE_LEGACY = 2,
  606. EFX_INT_MODE_MAX /* Insert any new items before this */
  607. };
  608. #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
  609. enum nic_state {
  610. STATE_UNINIT = 0, /* device being probed/removed or is frozen */
  611. STATE_READY = 1, /* hardware ready and netdev registered */
  612. STATE_DISABLED = 2, /* device disabled due to hardware errors */
  613. STATE_RECOVERY = 3, /* device recovering from PCI error */
  614. };
  615. /* Forward declaration */
  616. struct efx_nic;
  617. /* Pseudo bit-mask flow control field */
  618. #define EFX_FC_RX FLOW_CTRL_RX
  619. #define EFX_FC_TX FLOW_CTRL_TX
  620. #define EFX_FC_AUTO 4
  621. /**
  622. * struct efx_link_state - Current state of the link
  623. * @up: Link is up
  624. * @fd: Link is full-duplex
  625. * @fc: Actual flow control flags
  626. * @speed: Link speed (Mbps)
  627. */
  628. struct efx_link_state {
  629. bool up;
  630. bool fd;
  631. u8 fc;
  632. unsigned int speed;
  633. };
  634. static inline bool efx_link_state_equal(const struct efx_link_state *left,
  635. const struct efx_link_state *right)
  636. {
  637. return left->up == right->up && left->fd == right->fd &&
  638. left->fc == right->fc && left->speed == right->speed;
  639. }
  640. /**
  641. * struct efx_phy_operations - Efx PHY operations table
  642. * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
  643. * efx->loopback_modes.
  644. * @init: Initialise PHY
  645. * @fini: Shut down PHY
  646. * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
  647. * @poll: Update @link_state and report whether it changed.
  648. * Serialised by the mac_lock.
  649. * @get_settings: Get ethtool settings. Serialised by the mac_lock.
  650. * @set_settings: Set ethtool settings. Serialised by the mac_lock.
  651. * @set_npage_adv: Set abilities advertised in (Extended) Next Page
  652. * (only needed where AN bit is set in mmds)
  653. * @test_alive: Test that PHY is 'alive' (online)
  654. * @test_name: Get the name of a PHY-specific test/result
  655. * @run_tests: Run tests and record results as appropriate (offline).
  656. * Flags are the ethtool tests flags.
  657. */
  658. struct efx_phy_operations {
  659. int (*probe) (struct efx_nic *efx);
  660. int (*init) (struct efx_nic *efx);
  661. void (*fini) (struct efx_nic *efx);
  662. void (*remove) (struct efx_nic *efx);
  663. int (*reconfigure) (struct efx_nic *efx);
  664. bool (*poll) (struct efx_nic *efx);
  665. void (*get_settings) (struct efx_nic *efx,
  666. struct ethtool_cmd *ecmd);
  667. int (*set_settings) (struct efx_nic *efx,
  668. struct ethtool_cmd *ecmd);
  669. void (*set_npage_adv) (struct efx_nic *efx, u32);
  670. int (*test_alive) (struct efx_nic *efx);
  671. const char *(*test_name) (struct efx_nic *efx, unsigned int index);
  672. int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
  673. int (*get_module_eeprom) (struct efx_nic *efx,
  674. struct ethtool_eeprom *ee,
  675. u8 *data);
  676. int (*get_module_info) (struct efx_nic *efx,
  677. struct ethtool_modinfo *modinfo);
  678. };
  679. /**
  680. * enum efx_phy_mode - PHY operating mode flags
  681. * @PHY_MODE_NORMAL: on and should pass traffic
  682. * @PHY_MODE_TX_DISABLED: on with TX disabled
  683. * @PHY_MODE_LOW_POWER: set to low power through MDIO
  684. * @PHY_MODE_OFF: switched off through external control
  685. * @PHY_MODE_SPECIAL: on but will not pass traffic
  686. */
  687. enum efx_phy_mode {
  688. PHY_MODE_NORMAL = 0,
  689. PHY_MODE_TX_DISABLED = 1,
  690. PHY_MODE_LOW_POWER = 2,
  691. PHY_MODE_OFF = 4,
  692. PHY_MODE_SPECIAL = 8,
  693. };
  694. static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
  695. {
  696. return !!(mode & ~PHY_MODE_TX_DISABLED);
  697. }
  698. /**
  699. * struct efx_hw_stat_desc - Description of a hardware statistic
  700. * @name: Name of the statistic as visible through ethtool, or %NULL if
  701. * it should not be exposed
  702. * @dma_width: Width in bits (0 for non-DMA statistics)
  703. * @offset: Offset within stats (ignored for non-DMA statistics)
  704. */
  705. struct efx_hw_stat_desc {
  706. const char *name;
  707. u16 dma_width;
  708. u16 offset;
  709. };
  710. /* Number of bits used in a multicast filter hash address */
  711. #define EFX_MCAST_HASH_BITS 8
  712. /* Number of (single-bit) entries in a multicast filter hash */
  713. #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
  714. /* An Efx multicast filter hash */
  715. union efx_multicast_hash {
  716. u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
  717. efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
  718. };
  719. struct efx_vf;
  720. struct vfdi_status;
  721. /**
  722. * struct efx_nic - an Efx NIC
  723. * @name: Device name (net device name or bus id before net device registered)
  724. * @pci_dev: The PCI device
  725. * @node: List node for maintaning primary/secondary function lists
  726. * @primary: &struct efx_nic instance for the primary function of this
  727. * controller. May be the same structure, and may be %NULL if no
  728. * primary function is bound. Serialised by rtnl_lock.
  729. * @secondary_list: List of &struct efx_nic instances for the secondary PCI
  730. * functions of the controller, if this is for the primary function.
  731. * Serialised by rtnl_lock.
  732. * @type: Controller type attributes
  733. * @legacy_irq: IRQ number
  734. * @workqueue: Workqueue for port reconfigures and the HW monitor.
  735. * Work items do not hold and must not acquire RTNL.
  736. * @workqueue_name: Name of workqueue
  737. * @reset_work: Scheduled reset workitem
  738. * @membase_phys: Memory BAR value as physical address
  739. * @membase: Memory BAR value
  740. * @interrupt_mode: Interrupt mode
  741. * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
  742. * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
  743. * @irq_rx_moderation: IRQ moderation time for RX event queues
  744. * @msg_enable: Log message enable flags
  745. * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
  746. * @reset_pending: Bitmask for pending resets
  747. * @tx_queue: TX DMA queues
  748. * @rx_queue: RX DMA queues
  749. * @channel: Channels
  750. * @msi_context: Context for each MSI
  751. * @extra_channel_types: Types of extra (non-traffic) channels that
  752. * should be allocated for this NIC
  753. * @rxq_entries: Size of receive queues requested by user.
  754. * @txq_entries: Size of transmit queues requested by user.
  755. * @txq_stop_thresh: TX queue fill level at or above which we stop it.
  756. * @txq_wake_thresh: TX queue fill level at or below which we wake it.
  757. * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
  758. * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
  759. * @sram_lim_qw: Qword address limit of SRAM
  760. * @next_buffer_table: First available buffer table id
  761. * @n_channels: Number of channels in use
  762. * @n_rx_channels: Number of channels used for RX (= number of RX queues)
  763. * @n_tx_channels: Number of channels used for TX
  764. * @rx_ip_align: RX DMA address offset to have IP header aligned in
  765. * in accordance with NET_IP_ALIGN
  766. * @rx_dma_len: Current maximum RX DMA length
  767. * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
  768. * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
  769. * for use in sk_buff::truesize
  770. * @rx_prefix_size: Size of RX prefix before packet data
  771. * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
  772. * (valid only if @rx_prefix_size != 0; always negative)
  773. * @rx_packet_len_offset: Offset of RX packet length from start of packet data
  774. * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
  775. * @rx_packet_ts_offset: Offset of timestamp from start of packet data
  776. * (valid only if channel->sync_timestamps_enabled; always negative)
  777. * @rx_hash_key: Toeplitz hash key for RSS
  778. * @rx_indir_table: Indirection table for RSS
  779. * @rx_scatter: Scatter mode enabled for receives
  780. * @int_error_count: Number of internal errors seen recently
  781. * @int_error_expire: Time at which error count will be expired
  782. * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
  783. * acknowledge but do nothing else.
  784. * @irq_status: Interrupt status buffer
  785. * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
  786. * @irq_level: IRQ level/index for IRQs not triggered by an event queue
  787. * @selftest_work: Work item for asynchronous self-test
  788. * @mtd_list: List of MTDs attached to the NIC
  789. * @nic_data: Hardware dependent state
  790. * @mcdi: Management-Controller-to-Driver Interface state
  791. * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
  792. * efx_monitor() and efx_reconfigure_port()
  793. * @port_enabled: Port enabled indicator.
  794. * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
  795. * efx_mac_work() with kernel interfaces. Safe to read under any
  796. * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
  797. * be held to modify it.
  798. * @port_initialized: Port initialized?
  799. * @net_dev: Operating system network device. Consider holding the rtnl lock
  800. * @stats_buffer: DMA buffer for statistics
  801. * @phy_type: PHY type
  802. * @phy_op: PHY interface
  803. * @phy_data: PHY private data (including PHY-specific stats)
  804. * @mdio: PHY MDIO interface
  805. * @mdio_bus: PHY MDIO bus ID (only used by Siena)
  806. * @phy_mode: PHY operating mode. Serialised by @mac_lock.
  807. * @link_advertising: Autonegotiation advertising flags
  808. * @link_state: Current state of the link
  809. * @n_link_state_changes: Number of times the link has changed state
  810. * @unicast_filter: Flag for Falcon-arch simple unicast filter.
  811. * Protected by @mac_lock.
  812. * @multicast_hash: Multicast hash table for Falcon-arch.
  813. * Protected by @mac_lock.
  814. * @wanted_fc: Wanted flow control flags
  815. * @fc_disable: When non-zero flow control is disabled. Typically used to
  816. * ensure that network back pressure doesn't delay dma queue flushes.
  817. * Serialised by the rtnl lock.
  818. * @mac_work: Work item for changing MAC promiscuity and multicast hash
  819. * @loopback_mode: Loopback status
  820. * @loopback_modes: Supported loopback mode bitmask
  821. * @loopback_selftest: Offline self-test private state
  822. * @filter_lock: Filter table lock
  823. * @filter_state: Architecture-dependent filter table state
  824. * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
  825. * indexed by filter ID
  826. * @rps_expire_index: Next index to check for expiry in @rps_flow_id
  827. * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
  828. * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
  829. * Decremented when the efx_flush_rx_queue() is called.
  830. * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
  831. * completed (either success or failure). Not used when MCDI is used to
  832. * flush receive queues.
  833. * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
  834. * @vf: Array of &struct efx_vf objects.
  835. * @vf_count: Number of VFs intended to be enabled.
  836. * @vf_init_count: Number of VFs that have been fully initialised.
  837. * @vi_scale: log2 number of vnics per VF.
  838. * @vf_buftbl_base: The zeroth buffer table index used to back VF queues.
  839. * @vfdi_status: Common VFDI status page to be dmad to VF address space.
  840. * @local_addr_list: List of local addresses. Protected by %local_lock.
  841. * @local_page_list: List of DMA addressable pages used to broadcast
  842. * %local_addr_list. Protected by %local_lock.
  843. * @local_lock: Mutex protecting %local_addr_list and %local_page_list.
  844. * @peer_work: Work item to broadcast peer addresses to VMs.
  845. * @ptp_data: PTP state data
  846. * @vpd_sn: Serial number read from VPD
  847. * @monitor_work: Hardware monitor workitem
  848. * @biu_lock: BIU (bus interface unit) lock
  849. * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
  850. * field is used by efx_test_interrupts() to verify that an
  851. * interrupt has occurred.
  852. * @stats_lock: Statistics update lock. Must be held when calling
  853. * efx_nic_type::{update,start,stop}_stats.
  854. * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
  855. *
  856. * This is stored in the private area of the &struct net_device.
  857. */
  858. struct efx_nic {
  859. /* The following fields should be written very rarely */
  860. char name[IFNAMSIZ];
  861. struct list_head node;
  862. struct efx_nic *primary;
  863. struct list_head secondary_list;
  864. struct pci_dev *pci_dev;
  865. unsigned int port_num;
  866. const struct efx_nic_type *type;
  867. int legacy_irq;
  868. bool eeh_disabled_legacy_irq;
  869. struct workqueue_struct *workqueue;
  870. char workqueue_name[16];
  871. struct work_struct reset_work;
  872. resource_size_t membase_phys;
  873. void __iomem *membase;
  874. enum efx_int_mode interrupt_mode;
  875. unsigned int timer_quantum_ns;
  876. bool irq_rx_adaptive;
  877. unsigned int irq_rx_moderation;
  878. u32 msg_enable;
  879. enum nic_state state;
  880. unsigned long reset_pending;
  881. struct efx_channel *channel[EFX_MAX_CHANNELS];
  882. struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
  883. const struct efx_channel_type *
  884. extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
  885. unsigned rxq_entries;
  886. unsigned txq_entries;
  887. unsigned int txq_stop_thresh;
  888. unsigned int txq_wake_thresh;
  889. unsigned tx_dc_base;
  890. unsigned rx_dc_base;
  891. unsigned sram_lim_qw;
  892. unsigned next_buffer_table;
  893. unsigned int max_channels;
  894. unsigned n_channels;
  895. unsigned n_rx_channels;
  896. unsigned rss_spread;
  897. unsigned tx_channel_offset;
  898. unsigned n_tx_channels;
  899. unsigned int rx_ip_align;
  900. unsigned int rx_dma_len;
  901. unsigned int rx_buffer_order;
  902. unsigned int rx_buffer_truesize;
  903. unsigned int rx_page_buf_step;
  904. unsigned int rx_bufs_per_page;
  905. unsigned int rx_pages_per_batch;
  906. unsigned int rx_prefix_size;
  907. int rx_packet_hash_offset;
  908. int rx_packet_len_offset;
  909. int rx_packet_ts_offset;
  910. u8 rx_hash_key[40];
  911. u32 rx_indir_table[128];
  912. bool rx_scatter;
  913. unsigned int_error_count;
  914. unsigned long int_error_expire;
  915. bool irq_soft_enabled;
  916. struct efx_buffer irq_status;
  917. unsigned irq_zero_count;
  918. unsigned irq_level;
  919. struct delayed_work selftest_work;
  920. #ifdef CONFIG_SFC_MTD
  921. struct list_head mtd_list;
  922. #endif
  923. void *nic_data;
  924. struct efx_mcdi_data *mcdi;
  925. struct mutex mac_lock;
  926. struct work_struct mac_work;
  927. bool port_enabled;
  928. bool mc_bist_for_other_fn;
  929. bool port_initialized;
  930. struct net_device *net_dev;
  931. struct efx_buffer stats_buffer;
  932. u64 rx_nodesc_drops_total;
  933. u64 rx_nodesc_drops_while_down;
  934. bool rx_nodesc_drops_prev_state;
  935. unsigned int phy_type;
  936. const struct efx_phy_operations *phy_op;
  937. void *phy_data;
  938. struct mdio_if_info mdio;
  939. unsigned int mdio_bus;
  940. enum efx_phy_mode phy_mode;
  941. u32 link_advertising;
  942. struct efx_link_state link_state;
  943. unsigned int n_link_state_changes;
  944. bool unicast_filter;
  945. union efx_multicast_hash multicast_hash;
  946. u8 wanted_fc;
  947. unsigned fc_disable;
  948. atomic_t rx_reset;
  949. enum efx_loopback_mode loopback_mode;
  950. u64 loopback_modes;
  951. void *loopback_selftest;
  952. spinlock_t filter_lock;
  953. void *filter_state;
  954. #ifdef CONFIG_RFS_ACCEL
  955. u32 *rps_flow_id;
  956. unsigned int rps_expire_index;
  957. #endif
  958. atomic_t active_queues;
  959. atomic_t rxq_flush_pending;
  960. atomic_t rxq_flush_outstanding;
  961. wait_queue_head_t flush_wq;
  962. #ifdef CONFIG_SFC_SRIOV
  963. struct efx_channel *vfdi_channel;
  964. struct efx_vf *vf;
  965. unsigned vf_count;
  966. unsigned vf_init_count;
  967. unsigned vi_scale;
  968. unsigned vf_buftbl_base;
  969. struct efx_buffer vfdi_status;
  970. struct list_head local_addr_list;
  971. struct list_head local_page_list;
  972. struct mutex local_lock;
  973. struct work_struct peer_work;
  974. #endif
  975. struct efx_ptp_data *ptp_data;
  976. char *vpd_sn;
  977. /* The following fields may be written more often */
  978. struct delayed_work monitor_work ____cacheline_aligned_in_smp;
  979. spinlock_t biu_lock;
  980. int last_irq_cpu;
  981. spinlock_t stats_lock;
  982. atomic_t n_rx_noskb_drops;
  983. };
  984. static inline int efx_dev_registered(struct efx_nic *efx)
  985. {
  986. return efx->net_dev->reg_state == NETREG_REGISTERED;
  987. }
  988. static inline unsigned int efx_port_num(struct efx_nic *efx)
  989. {
  990. return efx->port_num;
  991. }
  992. struct efx_mtd_partition {
  993. struct list_head node;
  994. struct mtd_info mtd;
  995. const char *dev_type_name;
  996. const char *type_name;
  997. char name[IFNAMSIZ + 20];
  998. };
  999. /**
  1000. * struct efx_nic_type - Efx device type definition
  1001. * @mem_map_size: Get memory BAR mapped size
  1002. * @probe: Probe the controller
  1003. * @remove: Free resources allocated by probe()
  1004. * @init: Initialise the controller
  1005. * @dimension_resources: Dimension controller resources (buffer table,
  1006. * and VIs once the available interrupt resources are clear)
  1007. * @fini: Shut down the controller
  1008. * @monitor: Periodic function for polling link state and hardware monitor
  1009. * @map_reset_reason: Map ethtool reset reason to a reset method
  1010. * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
  1011. * @reset: Reset the controller hardware and possibly the PHY. This will
  1012. * be called while the controller is uninitialised.
  1013. * @probe_port: Probe the MAC and PHY
  1014. * @remove_port: Free resources allocated by probe_port()
  1015. * @handle_global_event: Handle a "global" event (may be %NULL)
  1016. * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
  1017. * @prepare_flush: Prepare the hardware for flushing the DMA queues
  1018. * (for Falcon architecture)
  1019. * @finish_flush: Clean up after flushing the DMA queues (for Falcon
  1020. * architecture)
  1021. * @prepare_flr: Prepare for an FLR
  1022. * @finish_flr: Clean up after an FLR
  1023. * @describe_stats: Describe statistics for ethtool
  1024. * @update_stats: Update statistics not provided by event handling.
  1025. * Either argument may be %NULL.
  1026. * @start_stats: Start the regular fetching of statistics
  1027. * @pull_stats: Pull stats from the NIC and wait until they arrive.
  1028. * @stop_stats: Stop the regular fetching of statistics
  1029. * @set_id_led: Set state of identifying LED or revert to automatic function
  1030. * @push_irq_moderation: Apply interrupt moderation value
  1031. * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
  1032. * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
  1033. * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
  1034. * to the hardware. Serialised by the mac_lock.
  1035. * @check_mac_fault: Check MAC fault state. True if fault present.
  1036. * @get_wol: Get WoL configuration from driver state
  1037. * @set_wol: Push WoL configuration to the NIC
  1038. * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
  1039. * @test_chip: Test registers. May use efx_farch_test_registers(), and is
  1040. * expected to reset the NIC.
  1041. * @test_nvram: Test validity of NVRAM contents
  1042. * @mcdi_request: Send an MCDI request with the given header and SDU.
  1043. * The SDU length may be any value from 0 up to the protocol-
  1044. * defined maximum, but its buffer will be padded to a multiple
  1045. * of 4 bytes.
  1046. * @mcdi_poll_response: Test whether an MCDI response is available.
  1047. * @mcdi_read_response: Read the MCDI response PDU. The offset will
  1048. * be a multiple of 4. The length may not be, but the buffer
  1049. * will be padded so it is safe to round up.
  1050. * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
  1051. * return an appropriate error code for aborting any current
  1052. * request; otherwise return 0.
  1053. * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
  1054. * be separately enabled after this.
  1055. * @irq_test_generate: Generate a test IRQ
  1056. * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
  1057. * queue must be separately disabled before this.
  1058. * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
  1059. * a pointer to the &struct efx_msi_context for the channel.
  1060. * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
  1061. * is a pointer to the &struct efx_nic.
  1062. * @tx_probe: Allocate resources for TX queue
  1063. * @tx_init: Initialise TX queue on the NIC
  1064. * @tx_remove: Free resources for TX queue
  1065. * @tx_write: Write TX descriptors and doorbell
  1066. * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
  1067. * @rx_probe: Allocate resources for RX queue
  1068. * @rx_init: Initialise RX queue on the NIC
  1069. * @rx_remove: Free resources for RX queue
  1070. * @rx_write: Write RX descriptors and doorbell
  1071. * @rx_defer_refill: Generate a refill reminder event
  1072. * @ev_probe: Allocate resources for event queue
  1073. * @ev_init: Initialise event queue on the NIC
  1074. * @ev_fini: Deinitialise event queue on the NIC
  1075. * @ev_remove: Free resources for event queue
  1076. * @ev_process: Process events for a queue, up to the given NAPI quota
  1077. * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
  1078. * @ev_test_generate: Generate a test event
  1079. * @filter_table_probe: Probe filter capabilities and set up filter software state
  1080. * @filter_table_restore: Restore filters removed from hardware
  1081. * @filter_table_remove: Remove filters from hardware and tear down software state
  1082. * @filter_update_rx_scatter: Update filters after change to rx scatter setting
  1083. * @filter_insert: add or replace a filter
  1084. * @filter_remove_safe: remove a filter by ID, carefully
  1085. * @filter_get_safe: retrieve a filter by ID, carefully
  1086. * @filter_clear_rx: Remove all RX filters whose priority is less than or
  1087. * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
  1088. * @filter_count_rx_used: Get the number of filters in use at a given priority
  1089. * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
  1090. * @filter_get_rx_ids: Get list of RX filters at a given priority
  1091. * @filter_rfs_insert: Add or replace a filter for RFS. This must be
  1092. * atomic. The hardware change may be asynchronous but should
  1093. * not be delayed for long. It may fail if this can't be done
  1094. * atomically.
  1095. * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
  1096. * This must check whether the specified table entry is used by RFS
  1097. * and that rps_may_expire_flow() returns true for it.
  1098. * @mtd_probe: Probe and add MTD partitions associated with this net device,
  1099. * using efx_mtd_add()
  1100. * @mtd_rename: Set an MTD partition name using the net device name
  1101. * @mtd_read: Read from an MTD partition
  1102. * @mtd_erase: Erase part of an MTD partition
  1103. * @mtd_write: Write to an MTD partition
  1104. * @mtd_sync: Wait for write-back to complete on MTD partition. This
  1105. * also notifies the driver that a writer has finished using this
  1106. * partition.
  1107. * @ptp_write_host_time: Send host time to MC as part of sync protocol
  1108. * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
  1109. * timestamping, possibly only temporarily for the purposes of a reset.
  1110. * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
  1111. * and tx_type will already have been validated but this operation
  1112. * must validate and update rx_filter.
  1113. * @revision: Hardware architecture revision
  1114. * @txd_ptr_tbl_base: TX descriptor ring base address
  1115. * @rxd_ptr_tbl_base: RX descriptor ring base address
  1116. * @buf_tbl_base: Buffer table base address
  1117. * @evq_ptr_tbl_base: Event queue pointer table base address
  1118. * @evq_rptr_tbl_base: Event queue read-pointer table base address
  1119. * @max_dma_mask: Maximum possible DMA mask
  1120. * @rx_prefix_size: Size of RX prefix before packet data
  1121. * @rx_hash_offset: Offset of RX flow hash within prefix
  1122. * @rx_ts_offset: Offset of timestamp within prefix
  1123. * @rx_buffer_padding: Size of padding at end of RX packet
  1124. * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
  1125. * @always_rx_scatter: NIC will always scatter packets to multiple buffers
  1126. * @max_interrupt_mode: Highest capability interrupt mode supported
  1127. * from &enum efx_init_mode.
  1128. * @timer_period_max: Maximum period of interrupt timer (in ticks)
  1129. * @offload_features: net_device feature flags for protocol offload
  1130. * features implemented in hardware
  1131. * @mcdi_max_ver: Maximum MCDI version supported
  1132. * @hwtstamp_filters: Mask of hardware timestamp filter types supported
  1133. */
  1134. struct efx_nic_type {
  1135. unsigned int (*mem_map_size)(struct efx_nic *efx);
  1136. int (*probe)(struct efx_nic *efx);
  1137. void (*remove)(struct efx_nic *efx);
  1138. int (*init)(struct efx_nic *efx);
  1139. int (*dimension_resources)(struct efx_nic *efx);
  1140. void (*fini)(struct efx_nic *efx);
  1141. void (*monitor)(struct efx_nic *efx);
  1142. enum reset_type (*map_reset_reason)(enum reset_type reason);
  1143. int (*map_reset_flags)(u32 *flags);
  1144. int (*reset)(struct efx_nic *efx, enum reset_type method);
  1145. int (*probe_port)(struct efx_nic *efx);
  1146. void (*remove_port)(struct efx_nic *efx);
  1147. bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
  1148. int (*fini_dmaq)(struct efx_nic *efx);
  1149. void (*prepare_flush)(struct efx_nic *efx);
  1150. void (*finish_flush)(struct efx_nic *efx);
  1151. void (*prepare_flr)(struct efx_nic *efx);
  1152. void (*finish_flr)(struct efx_nic *efx);
  1153. size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
  1154. size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
  1155. struct rtnl_link_stats64 *core_stats);
  1156. void (*start_stats)(struct efx_nic *efx);
  1157. void (*pull_stats)(struct efx_nic *efx);
  1158. void (*stop_stats)(struct efx_nic *efx);
  1159. void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
  1160. void (*push_irq_moderation)(struct efx_channel *channel);
  1161. int (*reconfigure_port)(struct efx_nic *efx);
  1162. void (*prepare_enable_fc_tx)(struct efx_nic *efx);
  1163. int (*reconfigure_mac)(struct efx_nic *efx);
  1164. bool (*check_mac_fault)(struct efx_nic *efx);
  1165. void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
  1166. int (*set_wol)(struct efx_nic *efx, u32 type);
  1167. void (*resume_wol)(struct efx_nic *efx);
  1168. int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
  1169. int (*test_nvram)(struct efx_nic *efx);
  1170. void (*mcdi_request)(struct efx_nic *efx,
  1171. const efx_dword_t *hdr, size_t hdr_len,
  1172. const efx_dword_t *sdu, size_t sdu_len);
  1173. bool (*mcdi_poll_response)(struct efx_nic *efx);
  1174. void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
  1175. size_t pdu_offset, size_t pdu_len);
  1176. int (*mcdi_poll_reboot)(struct efx_nic *efx);
  1177. void (*irq_enable_master)(struct efx_nic *efx);
  1178. void (*irq_test_generate)(struct efx_nic *efx);
  1179. void (*irq_disable_non_ev)(struct efx_nic *efx);
  1180. irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
  1181. irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
  1182. int (*tx_probe)(struct efx_tx_queue *tx_queue);
  1183. void (*tx_init)(struct efx_tx_queue *tx_queue);
  1184. void (*tx_remove)(struct efx_tx_queue *tx_queue);
  1185. void (*tx_write)(struct efx_tx_queue *tx_queue);
  1186. void (*rx_push_rss_config)(struct efx_nic *efx);
  1187. int (*rx_probe)(struct efx_rx_queue *rx_queue);
  1188. void (*rx_init)(struct efx_rx_queue *rx_queue);
  1189. void (*rx_remove)(struct efx_rx_queue *rx_queue);
  1190. void (*rx_write)(struct efx_rx_queue *rx_queue);
  1191. void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
  1192. int (*ev_probe)(struct efx_channel *channel);
  1193. int (*ev_init)(struct efx_channel *channel);
  1194. void (*ev_fini)(struct efx_channel *channel);
  1195. void (*ev_remove)(struct efx_channel *channel);
  1196. int (*ev_process)(struct efx_channel *channel, int quota);
  1197. void (*ev_read_ack)(struct efx_channel *channel);
  1198. void (*ev_test_generate)(struct efx_channel *channel);
  1199. int (*filter_table_probe)(struct efx_nic *efx);
  1200. void (*filter_table_restore)(struct efx_nic *efx);
  1201. void (*filter_table_remove)(struct efx_nic *efx);
  1202. void (*filter_update_rx_scatter)(struct efx_nic *efx);
  1203. s32 (*filter_insert)(struct efx_nic *efx,
  1204. struct efx_filter_spec *spec, bool replace);
  1205. int (*filter_remove_safe)(struct efx_nic *efx,
  1206. enum efx_filter_priority priority,
  1207. u32 filter_id);
  1208. int (*filter_get_safe)(struct efx_nic *efx,
  1209. enum efx_filter_priority priority,
  1210. u32 filter_id, struct efx_filter_spec *);
  1211. int (*filter_clear_rx)(struct efx_nic *efx,
  1212. enum efx_filter_priority priority);
  1213. u32 (*filter_count_rx_used)(struct efx_nic *efx,
  1214. enum efx_filter_priority priority);
  1215. u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
  1216. s32 (*filter_get_rx_ids)(struct efx_nic *efx,
  1217. enum efx_filter_priority priority,
  1218. u32 *buf, u32 size);
  1219. #ifdef CONFIG_RFS_ACCEL
  1220. s32 (*filter_rfs_insert)(struct efx_nic *efx,
  1221. struct efx_filter_spec *spec);
  1222. bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
  1223. unsigned int index);
  1224. #endif
  1225. #ifdef CONFIG_SFC_MTD
  1226. int (*mtd_probe)(struct efx_nic *efx);
  1227. void (*mtd_rename)(struct efx_mtd_partition *part);
  1228. int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
  1229. size_t *retlen, u8 *buffer);
  1230. int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
  1231. int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
  1232. size_t *retlen, const u8 *buffer);
  1233. int (*mtd_sync)(struct mtd_info *mtd);
  1234. #endif
  1235. void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
  1236. int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
  1237. int (*ptp_set_ts_config)(struct efx_nic *efx,
  1238. struct hwtstamp_config *init);
  1239. int revision;
  1240. unsigned int txd_ptr_tbl_base;
  1241. unsigned int rxd_ptr_tbl_base;
  1242. unsigned int buf_tbl_base;
  1243. unsigned int evq_ptr_tbl_base;
  1244. unsigned int evq_rptr_tbl_base;
  1245. u64 max_dma_mask;
  1246. unsigned int rx_prefix_size;
  1247. unsigned int rx_hash_offset;
  1248. unsigned int rx_ts_offset;
  1249. unsigned int rx_buffer_padding;
  1250. bool can_rx_scatter;
  1251. bool always_rx_scatter;
  1252. unsigned int max_interrupt_mode;
  1253. unsigned int timer_period_max;
  1254. netdev_features_t offload_features;
  1255. int mcdi_max_ver;
  1256. unsigned int max_rx_ip_filters;
  1257. u32 hwtstamp_filters;
  1258. };
  1259. /**************************************************************************
  1260. *
  1261. * Prototypes and inline functions
  1262. *
  1263. *************************************************************************/
  1264. static inline struct efx_channel *
  1265. efx_get_channel(struct efx_nic *efx, unsigned index)
  1266. {
  1267. EFX_BUG_ON_PARANOID(index >= efx->n_channels);
  1268. return efx->channel[index];
  1269. }
  1270. /* Iterate over all used channels */
  1271. #define efx_for_each_channel(_channel, _efx) \
  1272. for (_channel = (_efx)->channel[0]; \
  1273. _channel; \
  1274. _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
  1275. (_efx)->channel[_channel->channel + 1] : NULL)
  1276. /* Iterate over all used channels in reverse */
  1277. #define efx_for_each_channel_rev(_channel, _efx) \
  1278. for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
  1279. _channel; \
  1280. _channel = _channel->channel ? \
  1281. (_efx)->channel[_channel->channel - 1] : NULL)
  1282. static inline struct efx_tx_queue *
  1283. efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
  1284. {
  1285. EFX_BUG_ON_PARANOID(index >= efx->n_tx_channels ||
  1286. type >= EFX_TXQ_TYPES);
  1287. return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
  1288. }
  1289. static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
  1290. {
  1291. return channel->channel - channel->efx->tx_channel_offset <
  1292. channel->efx->n_tx_channels;
  1293. }
  1294. static inline struct efx_tx_queue *
  1295. efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
  1296. {
  1297. EFX_BUG_ON_PARANOID(!efx_channel_has_tx_queues(channel) ||
  1298. type >= EFX_TXQ_TYPES);
  1299. return &channel->tx_queue[type];
  1300. }
  1301. static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
  1302. {
  1303. return !(tx_queue->efx->net_dev->num_tc < 2 &&
  1304. tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
  1305. }
  1306. /* Iterate over all TX queues belonging to a channel */
  1307. #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
  1308. if (!efx_channel_has_tx_queues(_channel)) \
  1309. ; \
  1310. else \
  1311. for (_tx_queue = (_channel)->tx_queue; \
  1312. _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
  1313. efx_tx_queue_used(_tx_queue); \
  1314. _tx_queue++)
  1315. /* Iterate over all possible TX queues belonging to a channel */
  1316. #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
  1317. if (!efx_channel_has_tx_queues(_channel)) \
  1318. ; \
  1319. else \
  1320. for (_tx_queue = (_channel)->tx_queue; \
  1321. _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
  1322. _tx_queue++)
  1323. static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
  1324. {
  1325. return channel->rx_queue.core_index >= 0;
  1326. }
  1327. static inline struct efx_rx_queue *
  1328. efx_channel_get_rx_queue(struct efx_channel *channel)
  1329. {
  1330. EFX_BUG_ON_PARANOID(!efx_channel_has_rx_queue(channel));
  1331. return &channel->rx_queue;
  1332. }
  1333. /* Iterate over all RX queues belonging to a channel */
  1334. #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
  1335. if (!efx_channel_has_rx_queue(_channel)) \
  1336. ; \
  1337. else \
  1338. for (_rx_queue = &(_channel)->rx_queue; \
  1339. _rx_queue; \
  1340. _rx_queue = NULL)
  1341. static inline struct efx_channel *
  1342. efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
  1343. {
  1344. return container_of(rx_queue, struct efx_channel, rx_queue);
  1345. }
  1346. static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
  1347. {
  1348. return efx_rx_queue_channel(rx_queue)->channel;
  1349. }
  1350. /* Returns a pointer to the specified receive buffer in the RX
  1351. * descriptor queue.
  1352. */
  1353. static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
  1354. unsigned int index)
  1355. {
  1356. return &rx_queue->buffer[index];
  1357. }
  1358. /**
  1359. * EFX_MAX_FRAME_LEN - calculate maximum frame length
  1360. *
  1361. * This calculates the maximum frame length that will be used for a
  1362. * given MTU. The frame length will be equal to the MTU plus a
  1363. * constant amount of header space and padding. This is the quantity
  1364. * that the net driver will program into the MAC as the maximum frame
  1365. * length.
  1366. *
  1367. * The 10G MAC requires 8-byte alignment on the frame
  1368. * length, so we round up to the nearest 8.
  1369. *
  1370. * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
  1371. * XGMII cycle). If the frame length reaches the maximum value in the
  1372. * same cycle, the XMAC can miss the IPG altogether. We work around
  1373. * this by adding a further 16 bytes.
  1374. */
  1375. #define EFX_MAX_FRAME_LEN(mtu) \
  1376. ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
  1377. static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
  1378. {
  1379. return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
  1380. }
  1381. static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
  1382. {
  1383. skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
  1384. }
  1385. #endif /* EFX_NET_DRIVER_H */