mipi.c 6.8 KB

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  1. /*
  2. * Copyright (C) 2013 NVIDIA Corporation
  3. *
  4. * Permission to use, copy, modify, distribute, and sell this software and its
  5. * documentation for any purpose is hereby granted without fee, provided that
  6. * the above copyright notice appear in all copies and that both that copyright
  7. * notice and this permission notice appear in supporting documentation, and
  8. * that the name of the copyright holders not be used in advertising or
  9. * publicity pertaining to distribution of the software without specific,
  10. * written prior permission. The copyright holders make no representations
  11. * about the suitability of this software for any purpose. It is provided "as
  12. * is" without express or implied warranty.
  13. *
  14. * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15. * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16. * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17. * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18. * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20. * OF THIS SOFTWARE.
  21. */
  22. #include <linux/clk.h>
  23. #include <linux/delay.h>
  24. #include <linux/host1x.h>
  25. #include <linux/io.h>
  26. #include <linux/of_platform.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/slab.h>
  29. #include "dev.h"
  30. #define MIPI_CAL_CTRL 0x00
  31. #define MIPI_CAL_CTRL_START (1 << 0)
  32. #define MIPI_CAL_AUTOCAL_CTRL 0x01
  33. #define MIPI_CAL_STATUS 0x02
  34. #define MIPI_CAL_STATUS_DONE (1 << 16)
  35. #define MIPI_CAL_STATUS_ACTIVE (1 << 0)
  36. #define MIPI_CAL_CONFIG_CSIA 0x05
  37. #define MIPI_CAL_CONFIG_CSIB 0x06
  38. #define MIPI_CAL_CONFIG_CSIC 0x07
  39. #define MIPI_CAL_CONFIG_CSID 0x08
  40. #define MIPI_CAL_CONFIG_CSIE 0x09
  41. #define MIPI_CAL_CONFIG_DSIA 0x0e
  42. #define MIPI_CAL_CONFIG_DSIB 0x0f
  43. #define MIPI_CAL_CONFIG_DSIC 0x10
  44. #define MIPI_CAL_CONFIG_DSID 0x11
  45. #define MIPI_CAL_CONFIG_SELECT (1 << 21)
  46. #define MIPI_CAL_CONFIG_HSPDOS(x) (((x) & 0x1f) << 16)
  47. #define MIPI_CAL_CONFIG_HSPUOS(x) (((x) & 0x1f) << 8)
  48. #define MIPI_CAL_CONFIG_TERMOS(x) (((x) & 0x1f) << 0)
  49. #define MIPI_CAL_BIAS_PAD_CFG0 0x16
  50. #define MIPI_CAL_BIAS_PAD_PDVCLAMP (1 << 1)
  51. #define MIPI_CAL_BIAS_PAD_E_VCLAMP_REF (1 << 0)
  52. #define MIPI_CAL_BIAS_PAD_CFG1 0x17
  53. #define MIPI_CAL_BIAS_PAD_CFG2 0x18
  54. #define MIPI_CAL_BIAS_PAD_PDVREG (1 << 1)
  55. static const struct module {
  56. unsigned long reg;
  57. } modules[] = {
  58. { .reg = MIPI_CAL_CONFIG_CSIA },
  59. { .reg = MIPI_CAL_CONFIG_CSIB },
  60. { .reg = MIPI_CAL_CONFIG_CSIC },
  61. { .reg = MIPI_CAL_CONFIG_CSID },
  62. { .reg = MIPI_CAL_CONFIG_CSIE },
  63. { .reg = MIPI_CAL_CONFIG_DSIA },
  64. { .reg = MIPI_CAL_CONFIG_DSIB },
  65. { .reg = MIPI_CAL_CONFIG_DSIC },
  66. { .reg = MIPI_CAL_CONFIG_DSID },
  67. };
  68. struct tegra_mipi {
  69. void __iomem *regs;
  70. struct mutex lock;
  71. struct clk *clk;
  72. };
  73. struct tegra_mipi_device {
  74. struct platform_device *pdev;
  75. struct tegra_mipi *mipi;
  76. struct device *device;
  77. unsigned long pads;
  78. };
  79. static inline unsigned long tegra_mipi_readl(struct tegra_mipi *mipi,
  80. unsigned long reg)
  81. {
  82. return readl(mipi->regs + (reg << 2));
  83. }
  84. static inline void tegra_mipi_writel(struct tegra_mipi *mipi,
  85. unsigned long value, unsigned long reg)
  86. {
  87. writel(value, mipi->regs + (reg << 2));
  88. }
  89. struct tegra_mipi_device *tegra_mipi_request(struct device *device)
  90. {
  91. struct device_node *np = device->of_node;
  92. struct tegra_mipi_device *dev;
  93. struct of_phandle_args args;
  94. int err;
  95. err = of_parse_phandle_with_args(np, "nvidia,mipi-calibrate",
  96. "#nvidia,mipi-calibrate-cells", 0,
  97. &args);
  98. if (err < 0)
  99. return ERR_PTR(err);
  100. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  101. if (!dev) {
  102. of_node_put(args.np);
  103. err = -ENOMEM;
  104. goto out;
  105. }
  106. dev->pdev = of_find_device_by_node(args.np);
  107. if (!dev->pdev) {
  108. of_node_put(args.np);
  109. err = -ENODEV;
  110. goto free;
  111. }
  112. of_node_put(args.np);
  113. dev->mipi = platform_get_drvdata(dev->pdev);
  114. if (!dev->mipi) {
  115. err = -EPROBE_DEFER;
  116. goto pdev_put;
  117. }
  118. dev->pads = args.args[0];
  119. dev->device = device;
  120. return dev;
  121. pdev_put:
  122. platform_device_put(dev->pdev);
  123. free:
  124. kfree(dev);
  125. out:
  126. return ERR_PTR(err);
  127. }
  128. EXPORT_SYMBOL(tegra_mipi_request);
  129. void tegra_mipi_free(struct tegra_mipi_device *device)
  130. {
  131. platform_device_put(device->pdev);
  132. kfree(device);
  133. }
  134. EXPORT_SYMBOL(tegra_mipi_free);
  135. static int tegra_mipi_wait(struct tegra_mipi *mipi)
  136. {
  137. unsigned long timeout = jiffies + msecs_to_jiffies(250);
  138. unsigned long value;
  139. while (time_before(jiffies, timeout)) {
  140. value = tegra_mipi_readl(mipi, MIPI_CAL_STATUS);
  141. if ((value & MIPI_CAL_STATUS_ACTIVE) == 0 &&
  142. (value & MIPI_CAL_STATUS_DONE) != 0)
  143. return 0;
  144. usleep_range(10, 50);
  145. }
  146. return -ETIMEDOUT;
  147. }
  148. int tegra_mipi_calibrate(struct tegra_mipi_device *device)
  149. {
  150. unsigned long value;
  151. unsigned int i;
  152. int err;
  153. err = clk_enable(device->mipi->clk);
  154. if (err < 0)
  155. return err;
  156. mutex_lock(&device->mipi->lock);
  157. value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG0);
  158. value &= ~MIPI_CAL_BIAS_PAD_PDVCLAMP;
  159. value |= MIPI_CAL_BIAS_PAD_E_VCLAMP_REF;
  160. tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG0);
  161. value = tegra_mipi_readl(device->mipi, MIPI_CAL_BIAS_PAD_CFG2);
  162. value &= ~MIPI_CAL_BIAS_PAD_PDVREG;
  163. tegra_mipi_writel(device->mipi, value, MIPI_CAL_BIAS_PAD_CFG2);
  164. for (i = 0; i < ARRAY_SIZE(modules); i++) {
  165. if (device->pads & BIT(i))
  166. value = MIPI_CAL_CONFIG_SELECT |
  167. MIPI_CAL_CONFIG_HSPDOS(0) |
  168. MIPI_CAL_CONFIG_HSPUOS(4) |
  169. MIPI_CAL_CONFIG_TERMOS(5);
  170. else
  171. value = 0;
  172. tegra_mipi_writel(device->mipi, value, modules[i].reg);
  173. }
  174. tegra_mipi_writel(device->mipi, MIPI_CAL_CTRL_START, MIPI_CAL_CTRL);
  175. err = tegra_mipi_wait(device->mipi);
  176. mutex_unlock(&device->mipi->lock);
  177. clk_disable(device->mipi->clk);
  178. return err;
  179. }
  180. EXPORT_SYMBOL(tegra_mipi_calibrate);
  181. static int tegra_mipi_probe(struct platform_device *pdev)
  182. {
  183. struct tegra_mipi *mipi;
  184. struct resource *res;
  185. int err;
  186. mipi = devm_kzalloc(&pdev->dev, sizeof(*mipi), GFP_KERNEL);
  187. if (!mipi)
  188. return -ENOMEM;
  189. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  190. mipi->regs = devm_ioremap_resource(&pdev->dev, res);
  191. if (IS_ERR(mipi->regs))
  192. return PTR_ERR(mipi->regs);
  193. mutex_init(&mipi->lock);
  194. mipi->clk = devm_clk_get(&pdev->dev, NULL);
  195. if (IS_ERR(mipi->clk)) {
  196. dev_err(&pdev->dev, "failed to get clock\n");
  197. return PTR_ERR(mipi->clk);
  198. }
  199. err = clk_prepare(mipi->clk);
  200. if (err < 0)
  201. return err;
  202. platform_set_drvdata(pdev, mipi);
  203. return 0;
  204. }
  205. static int tegra_mipi_remove(struct platform_device *pdev)
  206. {
  207. struct tegra_mipi *mipi = platform_get_drvdata(pdev);
  208. clk_unprepare(mipi->clk);
  209. return 0;
  210. }
  211. static struct of_device_id tegra_mipi_of_match[] = {
  212. { .compatible = "nvidia,tegra114-mipi", },
  213. { },
  214. };
  215. struct platform_driver tegra_mipi_driver = {
  216. .driver = {
  217. .name = "tegra-mipi",
  218. .of_match_table = tegra_mipi_of_match,
  219. },
  220. .probe = tegra_mipi_probe,
  221. .remove = tegra_mipi_remove,
  222. };