sti_hdmi.c 21 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2014
  3. * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
  4. * License terms: GNU General Public License (GPL), version 2
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/component.h>
  8. #include <linux/hdmi.h>
  9. #include <linux/module.h>
  10. #include <linux/of_gpio.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reset.h>
  13. #include <drm/drmP.h>
  14. #include <drm/drm_crtc_helper.h>
  15. #include <drm/drm_edid.h>
  16. #include "sti_hdmi.h"
  17. #include "sti_hdmi_tx3g4c28phy.h"
  18. #include "sti_hdmi_tx3g0c55phy.h"
  19. #include "sti_vtg.h"
  20. #define HDMI_CFG 0x0000
  21. #define HDMI_INT_EN 0x0004
  22. #define HDMI_INT_STA 0x0008
  23. #define HDMI_INT_CLR 0x000C
  24. #define HDMI_STA 0x0010
  25. #define HDMI_ACTIVE_VID_XMIN 0x0100
  26. #define HDMI_ACTIVE_VID_XMAX 0x0104
  27. #define HDMI_ACTIVE_VID_YMIN 0x0108
  28. #define HDMI_ACTIVE_VID_YMAX 0x010C
  29. #define HDMI_DFLT_CHL0_DAT 0x0110
  30. #define HDMI_DFLT_CHL1_DAT 0x0114
  31. #define HDMI_DFLT_CHL2_DAT 0x0118
  32. #define HDMI_SW_DI_1_HEAD_WORD 0x0210
  33. #define HDMI_SW_DI_1_PKT_WORD0 0x0214
  34. #define HDMI_SW_DI_1_PKT_WORD1 0x0218
  35. #define HDMI_SW_DI_1_PKT_WORD2 0x021C
  36. #define HDMI_SW_DI_1_PKT_WORD3 0x0220
  37. #define HDMI_SW_DI_1_PKT_WORD4 0x0224
  38. #define HDMI_SW_DI_1_PKT_WORD5 0x0228
  39. #define HDMI_SW_DI_1_PKT_WORD6 0x022C
  40. #define HDMI_SW_DI_CFG 0x0230
  41. #define HDMI_IFRAME_SLOT_AVI 1
  42. #define XCAT(prefix, x, suffix) prefix ## x ## suffix
  43. #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  44. #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  45. #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  46. #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  47. #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  48. #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  49. #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  50. #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  51. #define HDMI_IFRAME_DISABLED 0x0
  52. #define HDMI_IFRAME_SINGLE_SHOT 0x1
  53. #define HDMI_IFRAME_FIELD 0x2
  54. #define HDMI_IFRAME_FRAME 0x3
  55. #define HDMI_IFRAME_MASK 0x3
  56. #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
  57. #define HDMI_CFG_DEVICE_EN BIT(0)
  58. #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
  59. #define HDMI_CFG_HDCP_EN BIT(2)
  60. #define HDMI_CFG_ESS_NOT_OESS BIT(3)
  61. #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
  62. #define HDMI_CFG_SINK_TERM_DET_EN BIT(5)
  63. #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
  64. #define HDMI_CFG_422_EN BIT(8)
  65. #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
  66. #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
  67. #define HDMI_CFG_SW_RST_EN BIT(31)
  68. #define HDMI_INT_GLOBAL BIT(0)
  69. #define HDMI_INT_SW_RST BIT(1)
  70. #define HDMI_INT_PIX_CAP BIT(3)
  71. #define HDMI_INT_HOT_PLUG BIT(4)
  72. #define HDMI_INT_DLL_LCK BIT(5)
  73. #define HDMI_INT_NEW_FRAME BIT(6)
  74. #define HDMI_INT_GENCTRL_PKT BIT(7)
  75. #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
  76. #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
  77. | HDMI_INT_DLL_LCK \
  78. | HDMI_INT_HOT_PLUG \
  79. | HDMI_INT_GLOBAL)
  80. #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
  81. | HDMI_INT_GENCTRL_PKT \
  82. | HDMI_INT_NEW_FRAME \
  83. | HDMI_INT_DLL_LCK \
  84. | HDMI_INT_HOT_PLUG \
  85. | HDMI_INT_PIX_CAP \
  86. | HDMI_INT_SW_RST \
  87. | HDMI_INT_GLOBAL)
  88. #define HDMI_STA_SW_RST BIT(1)
  89. struct sti_hdmi_connector {
  90. struct drm_connector drm_connector;
  91. struct drm_encoder *encoder;
  92. struct sti_hdmi *hdmi;
  93. };
  94. #define to_sti_hdmi_connector(x) \
  95. container_of(x, struct sti_hdmi_connector, drm_connector)
  96. u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
  97. {
  98. return readl(hdmi->regs + offset);
  99. }
  100. void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
  101. {
  102. writel(val, hdmi->regs + offset);
  103. }
  104. /**
  105. * HDMI interrupt handler threaded
  106. *
  107. * @irq: irq number
  108. * @arg: connector structure
  109. */
  110. static irqreturn_t hdmi_irq_thread(int irq, void *arg)
  111. {
  112. struct sti_hdmi *hdmi = arg;
  113. /* Hot plug/unplug IRQ */
  114. if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
  115. /* read gpio to get the status */
  116. hdmi->hpd = gpio_get_value(hdmi->hpd_gpio);
  117. if (hdmi->drm_dev)
  118. drm_helper_hpd_irq_event(hdmi->drm_dev);
  119. }
  120. /* Sw reset and PLL lock are exclusive so we can use the same
  121. * event to signal them
  122. */
  123. if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
  124. hdmi->event_received = true;
  125. wake_up_interruptible(&hdmi->wait_event);
  126. }
  127. return IRQ_HANDLED;
  128. }
  129. /**
  130. * HDMI interrupt handler
  131. *
  132. * @irq: irq number
  133. * @arg: connector structure
  134. */
  135. static irqreturn_t hdmi_irq(int irq, void *arg)
  136. {
  137. struct sti_hdmi *hdmi = arg;
  138. /* read interrupt status */
  139. hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
  140. /* clear interrupt status */
  141. hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
  142. /* force sync bus write */
  143. hdmi_read(hdmi, HDMI_INT_STA);
  144. return IRQ_WAKE_THREAD;
  145. }
  146. /**
  147. * Set hdmi active area depending on the drm display mode selected
  148. *
  149. * @hdmi: pointer on the hdmi internal structure
  150. */
  151. static void hdmi_active_area(struct sti_hdmi *hdmi)
  152. {
  153. u32 xmin, xmax;
  154. u32 ymin, ymax;
  155. xmin = sti_vtg_get_pixel_number(hdmi->mode, 0);
  156. xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay - 1);
  157. ymin = sti_vtg_get_line_number(hdmi->mode, 0);
  158. ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
  159. hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
  160. hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
  161. hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
  162. hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
  163. }
  164. /**
  165. * Overall hdmi configuration
  166. *
  167. * @hdmi: pointer on the hdmi internal structure
  168. */
  169. static void hdmi_config(struct sti_hdmi *hdmi)
  170. {
  171. u32 conf;
  172. DRM_DEBUG_DRIVER("\n");
  173. /* Clear overrun and underrun fifo */
  174. conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
  175. /* Enable HDMI mode not DVI */
  176. conf |= HDMI_CFG_HDMI_NOT_DVI | HDMI_CFG_ESS_NOT_OESS;
  177. /* Enable sink term detection */
  178. conf |= HDMI_CFG_SINK_TERM_DET_EN;
  179. /* Set Hsync polarity */
  180. if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
  181. DRM_DEBUG_DRIVER("H Sync Negative\n");
  182. conf |= HDMI_CFG_H_SYNC_POL_NEG;
  183. }
  184. /* Set Vsync polarity */
  185. if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
  186. DRM_DEBUG_DRIVER("V Sync Negative\n");
  187. conf |= HDMI_CFG_V_SYNC_POL_NEG;
  188. }
  189. /* Enable HDMI */
  190. conf |= HDMI_CFG_DEVICE_EN;
  191. hdmi_write(hdmi, conf, HDMI_CFG);
  192. }
  193. /**
  194. * Prepare and configure the AVI infoframe
  195. *
  196. * AVI infoframe are transmitted at least once per two video field and
  197. * contains information about HDMI transmission mode such as color space,
  198. * colorimetry, ...
  199. *
  200. * @hdmi: pointer on the hdmi internal structure
  201. *
  202. * Return negative value if error occurs
  203. */
  204. static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
  205. {
  206. struct drm_display_mode *mode = &hdmi->mode;
  207. struct hdmi_avi_infoframe infoframe;
  208. u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  209. u8 *frame = buffer + HDMI_INFOFRAME_HEADER_SIZE;
  210. u32 val;
  211. int ret;
  212. DRM_DEBUG_DRIVER("\n");
  213. ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode);
  214. if (ret < 0) {
  215. DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
  216. return ret;
  217. }
  218. /* fixed infoframe configuration not linked to the mode */
  219. infoframe.colorspace = HDMI_COLORSPACE_RGB;
  220. infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  221. infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
  222. ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
  223. if (ret < 0) {
  224. DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
  225. return ret;
  226. }
  227. /* Disable transmission slot for AVI infoframe */
  228. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  229. val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, HDMI_IFRAME_SLOT_AVI);
  230. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  231. /* Infoframe header */
  232. val = buffer[0x0];
  233. val |= buffer[0x1] << 8;
  234. val |= buffer[0x2] << 16;
  235. hdmi_write(hdmi, val, HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI));
  236. /* Infoframe packet bytes */
  237. val = frame[0x0];
  238. val |= frame[0x1] << 8;
  239. val |= frame[0x2] << 16;
  240. val |= frame[0x3] << 24;
  241. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI));
  242. val = frame[0x4];
  243. val |= frame[0x5] << 8;
  244. val |= frame[0x6] << 16;
  245. val |= frame[0x7] << 24;
  246. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD1(HDMI_IFRAME_SLOT_AVI));
  247. val = frame[0x8];
  248. val |= frame[0x9] << 8;
  249. val |= frame[0xA] << 16;
  250. val |= frame[0xB] << 24;
  251. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD2(HDMI_IFRAME_SLOT_AVI));
  252. val = frame[0xC];
  253. hdmi_write(hdmi, val, HDMI_SW_DI_N_PKT_WORD3(HDMI_IFRAME_SLOT_AVI));
  254. /* Enable transmission slot for AVI infoframe
  255. * According to the hdmi specification, AVI infoframe should be
  256. * transmitted at least once per two video fields
  257. */
  258. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  259. val |= HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_FIELD, HDMI_IFRAME_SLOT_AVI);
  260. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  261. return 0;
  262. }
  263. /**
  264. * Software reset of the hdmi subsystem
  265. *
  266. * @hdmi: pointer on the hdmi internal structure
  267. *
  268. */
  269. #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
  270. static void hdmi_swreset(struct sti_hdmi *hdmi)
  271. {
  272. u32 val;
  273. DRM_DEBUG_DRIVER("\n");
  274. /* Enable hdmi_audio clock only during hdmi reset */
  275. if (clk_prepare_enable(hdmi->clk_audio))
  276. DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
  277. /* Sw reset */
  278. hdmi->event_received = false;
  279. val = hdmi_read(hdmi, HDMI_CFG);
  280. val |= HDMI_CFG_SW_RST_EN;
  281. hdmi_write(hdmi, val, HDMI_CFG);
  282. /* Wait reset completed */
  283. wait_event_interruptible_timeout(hdmi->wait_event,
  284. hdmi->event_received == true,
  285. msecs_to_jiffies
  286. (HDMI_TIMEOUT_SWRESET));
  287. /*
  288. * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
  289. * set to '1' and clk_audio is running.
  290. */
  291. if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
  292. DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
  293. val = hdmi_read(hdmi, HDMI_CFG);
  294. val &= ~HDMI_CFG_SW_RST_EN;
  295. hdmi_write(hdmi, val, HDMI_CFG);
  296. /* Disable hdmi_audio clock. Not used anymore for drm purpose */
  297. clk_disable_unprepare(hdmi->clk_audio);
  298. }
  299. static void sti_hdmi_disable(struct drm_bridge *bridge)
  300. {
  301. struct sti_hdmi *hdmi = bridge->driver_private;
  302. u32 val = hdmi_read(hdmi, HDMI_CFG);
  303. if (!hdmi->enabled)
  304. return;
  305. DRM_DEBUG_DRIVER("\n");
  306. /* Disable HDMI */
  307. val &= ~HDMI_CFG_DEVICE_EN;
  308. hdmi_write(hdmi, val, HDMI_CFG);
  309. hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
  310. /* Stop the phy */
  311. hdmi->phy_ops->stop(hdmi);
  312. /* Set the default channel data to be a dark red */
  313. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
  314. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
  315. hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
  316. /* Disable/unprepare hdmi clock */
  317. clk_disable_unprepare(hdmi->clk_phy);
  318. clk_disable_unprepare(hdmi->clk_tmds);
  319. clk_disable_unprepare(hdmi->clk_pix);
  320. hdmi->enabled = false;
  321. }
  322. static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
  323. {
  324. struct sti_hdmi *hdmi = bridge->driver_private;
  325. DRM_DEBUG_DRIVER("\n");
  326. if (hdmi->enabled)
  327. return;
  328. /* Prepare/enable clocks */
  329. if (clk_prepare_enable(hdmi->clk_pix))
  330. DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
  331. if (clk_prepare_enable(hdmi->clk_tmds))
  332. DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
  333. if (clk_prepare_enable(hdmi->clk_phy))
  334. DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
  335. hdmi->enabled = true;
  336. /* Program hdmi serializer and start phy */
  337. if (!hdmi->phy_ops->start(hdmi)) {
  338. DRM_ERROR("Unable to start hdmi phy\n");
  339. return;
  340. }
  341. /* Program hdmi active area */
  342. hdmi_active_area(hdmi);
  343. /* Enable working interrupts */
  344. hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
  345. /* Program hdmi config */
  346. hdmi_config(hdmi);
  347. /* Program AVI infoframe */
  348. if (hdmi_avi_infoframe_config(hdmi))
  349. DRM_ERROR("Unable to configure AVI infoframe\n");
  350. /* Sw reset */
  351. hdmi_swreset(hdmi);
  352. }
  353. static void sti_hdmi_set_mode(struct drm_bridge *bridge,
  354. struct drm_display_mode *mode,
  355. struct drm_display_mode *adjusted_mode)
  356. {
  357. struct sti_hdmi *hdmi = bridge->driver_private;
  358. int ret;
  359. DRM_DEBUG_DRIVER("\n");
  360. /* Copy the drm display mode in the connector local structure */
  361. memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
  362. /* Update clock framerate according to the selected mode */
  363. ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
  364. if (ret < 0) {
  365. DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
  366. mode->clock * 1000);
  367. return;
  368. }
  369. ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
  370. if (ret < 0) {
  371. DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
  372. mode->clock * 1000);
  373. return;
  374. }
  375. }
  376. static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
  377. {
  378. /* do nothing */
  379. }
  380. static void sti_hdmi_brigde_destroy(struct drm_bridge *bridge)
  381. {
  382. drm_bridge_cleanup(bridge);
  383. kfree(bridge);
  384. }
  385. static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
  386. .pre_enable = sti_hdmi_pre_enable,
  387. .enable = sti_hdmi_bridge_nope,
  388. .disable = sti_hdmi_disable,
  389. .post_disable = sti_hdmi_bridge_nope,
  390. .mode_set = sti_hdmi_set_mode,
  391. .destroy = sti_hdmi_brigde_destroy,
  392. };
  393. static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
  394. {
  395. struct i2c_adapter *i2c_adap;
  396. struct edid *edid;
  397. int count;
  398. DRM_DEBUG_DRIVER("\n");
  399. i2c_adap = i2c_get_adapter(1);
  400. if (!i2c_adap)
  401. goto fail;
  402. edid = drm_get_edid(connector, i2c_adap);
  403. if (!edid)
  404. goto fail;
  405. count = drm_add_edid_modes(connector, edid);
  406. drm_mode_connector_update_edid_property(connector, edid);
  407. kfree(edid);
  408. return count;
  409. fail:
  410. DRM_ERROR("Can not read HDMI EDID\n");
  411. return 0;
  412. }
  413. #define CLK_TOLERANCE_HZ 50
  414. static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
  415. struct drm_display_mode *mode)
  416. {
  417. int target = mode->clock * 1000;
  418. int target_min = target - CLK_TOLERANCE_HZ;
  419. int target_max = target + CLK_TOLERANCE_HZ;
  420. int result;
  421. struct sti_hdmi_connector *hdmi_connector
  422. = to_sti_hdmi_connector(connector);
  423. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  424. result = clk_round_rate(hdmi->clk_pix, target);
  425. DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
  426. target, result);
  427. if ((result < target_min) || (result > target_max)) {
  428. DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
  429. return MODE_BAD;
  430. }
  431. return MODE_OK;
  432. }
  433. struct drm_encoder *sti_hdmi_best_encoder(struct drm_connector *connector)
  434. {
  435. struct sti_hdmi_connector *hdmi_connector
  436. = to_sti_hdmi_connector(connector);
  437. /* Best encoder is the one associated during connector creation */
  438. return hdmi_connector->encoder;
  439. }
  440. static struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
  441. .get_modes = sti_hdmi_connector_get_modes,
  442. .mode_valid = sti_hdmi_connector_mode_valid,
  443. .best_encoder = sti_hdmi_best_encoder,
  444. };
  445. /* get detection status of display device */
  446. static enum drm_connector_status
  447. sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
  448. {
  449. struct sti_hdmi_connector *hdmi_connector
  450. = to_sti_hdmi_connector(connector);
  451. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  452. DRM_DEBUG_DRIVER("\n");
  453. if (hdmi->hpd) {
  454. DRM_DEBUG_DRIVER("hdmi cable connected\n");
  455. return connector_status_connected;
  456. }
  457. DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
  458. return connector_status_disconnected;
  459. }
  460. static void sti_hdmi_connector_destroy(struct drm_connector *connector)
  461. {
  462. struct sti_hdmi_connector *hdmi_connector
  463. = to_sti_hdmi_connector(connector);
  464. drm_connector_unregister(connector);
  465. drm_connector_cleanup(connector);
  466. kfree(hdmi_connector);
  467. }
  468. static struct drm_connector_funcs sti_hdmi_connector_funcs = {
  469. .dpms = drm_helper_connector_dpms,
  470. .fill_modes = drm_helper_probe_single_connector_modes,
  471. .detect = sti_hdmi_connector_detect,
  472. .destroy = sti_hdmi_connector_destroy,
  473. };
  474. static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
  475. {
  476. struct drm_encoder *encoder;
  477. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  478. if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
  479. return encoder;
  480. }
  481. return NULL;
  482. }
  483. static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
  484. {
  485. struct sti_hdmi *hdmi = dev_get_drvdata(dev);
  486. struct drm_device *drm_dev = data;
  487. struct drm_encoder *encoder;
  488. struct sti_hdmi_connector *connector;
  489. struct drm_connector *drm_connector;
  490. struct drm_bridge *bridge;
  491. struct i2c_adapter *i2c_adap;
  492. int err;
  493. i2c_adap = i2c_get_adapter(1);
  494. if (!i2c_adap)
  495. return -EPROBE_DEFER;
  496. /* Set the drm device handle */
  497. hdmi->drm_dev = drm_dev;
  498. encoder = sti_hdmi_find_encoder(drm_dev);
  499. if (!encoder)
  500. return -ENOMEM;
  501. connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
  502. if (!connector)
  503. return -ENOMEM;
  504. connector->hdmi = hdmi;
  505. bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
  506. if (!bridge)
  507. return -ENOMEM;
  508. bridge->driver_private = hdmi;
  509. drm_bridge_init(drm_dev, bridge, &sti_hdmi_bridge_funcs);
  510. encoder->bridge = bridge;
  511. connector->encoder = encoder;
  512. drm_connector = (struct drm_connector *)connector;
  513. drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
  514. drm_connector_init(drm_dev, drm_connector,
  515. &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
  516. drm_connector_helper_add(drm_connector,
  517. &sti_hdmi_connector_helper_funcs);
  518. err = drm_connector_register(drm_connector);
  519. if (err)
  520. goto err_connector;
  521. err = drm_mode_connector_attach_encoder(drm_connector, encoder);
  522. if (err) {
  523. DRM_ERROR("Failed to attach a connector to a encoder\n");
  524. goto err_sysfs;
  525. }
  526. /* Enable default interrupts */
  527. hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
  528. return 0;
  529. err_sysfs:
  530. drm_connector_unregister(drm_connector);
  531. err_connector:
  532. drm_bridge_cleanup(bridge);
  533. drm_connector_cleanup(drm_connector);
  534. return -EINVAL;
  535. }
  536. static void sti_hdmi_unbind(struct device *dev,
  537. struct device *master, void *data)
  538. {
  539. /* do nothing */
  540. }
  541. static const struct component_ops sti_hdmi_ops = {
  542. .bind = sti_hdmi_bind,
  543. .unbind = sti_hdmi_unbind,
  544. };
  545. static const struct of_device_id hdmi_of_match[] = {
  546. {
  547. .compatible = "st,stih416-hdmi",
  548. .data = &tx3g0c55phy_ops,
  549. }, {
  550. .compatible = "st,stih407-hdmi",
  551. .data = &tx3g4c28phy_ops,
  552. }, {
  553. /* end node */
  554. }
  555. };
  556. MODULE_DEVICE_TABLE(of, hdmi_of_match);
  557. static int sti_hdmi_probe(struct platform_device *pdev)
  558. {
  559. struct device *dev = &pdev->dev;
  560. struct sti_hdmi *hdmi;
  561. struct device_node *np = dev->of_node;
  562. struct resource *res;
  563. int ret;
  564. DRM_INFO("%s\n", __func__);
  565. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  566. if (!hdmi)
  567. return -ENOMEM;
  568. hdmi->dev = pdev->dev;
  569. /* Get resources */
  570. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
  571. if (!res) {
  572. DRM_ERROR("Invalid hdmi resource\n");
  573. return -ENOMEM;
  574. }
  575. hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
  576. if (!hdmi->regs)
  577. return -ENOMEM;
  578. if (of_device_is_compatible(np, "st,stih416-hdmi")) {
  579. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  580. "syscfg");
  581. if (!res) {
  582. DRM_ERROR("Invalid syscfg resource\n");
  583. return -ENOMEM;
  584. }
  585. hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
  586. resource_size(res));
  587. if (!hdmi->syscfg)
  588. return -ENOMEM;
  589. }
  590. hdmi->phy_ops = (struct hdmi_phy_ops *)
  591. of_match_node(hdmi_of_match, np)->data;
  592. /* Get clock resources */
  593. hdmi->clk_pix = devm_clk_get(dev, "pix");
  594. if (IS_ERR(hdmi->clk_pix)) {
  595. DRM_ERROR("Cannot get hdmi_pix clock\n");
  596. return PTR_ERR(hdmi->clk_pix);
  597. }
  598. hdmi->clk_tmds = devm_clk_get(dev, "tmds");
  599. if (IS_ERR(hdmi->clk_tmds)) {
  600. DRM_ERROR("Cannot get hdmi_tmds clock\n");
  601. return PTR_ERR(hdmi->clk_tmds);
  602. }
  603. hdmi->clk_phy = devm_clk_get(dev, "phy");
  604. if (IS_ERR(hdmi->clk_phy)) {
  605. DRM_ERROR("Cannot get hdmi_phy clock\n");
  606. return PTR_ERR(hdmi->clk_phy);
  607. }
  608. hdmi->clk_audio = devm_clk_get(dev, "audio");
  609. if (IS_ERR(hdmi->clk_audio)) {
  610. DRM_ERROR("Cannot get hdmi_audio clock\n");
  611. return PTR_ERR(hdmi->clk_audio);
  612. }
  613. hdmi->hpd_gpio = of_get_named_gpio(np, "hdmi,hpd-gpio", 0);
  614. if (hdmi->hpd_gpio < 0) {
  615. DRM_ERROR("Failed to get hdmi hpd-gpio\n");
  616. return -EIO;
  617. }
  618. hdmi->hpd = gpio_get_value(hdmi->hpd_gpio);
  619. init_waitqueue_head(&hdmi->wait_event);
  620. hdmi->irq = platform_get_irq_byname(pdev, "irq");
  621. ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
  622. hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
  623. if (ret) {
  624. DRM_ERROR("Failed to register HDMI interrupt\n");
  625. return ret;
  626. }
  627. hdmi->reset = devm_reset_control_get(dev, "hdmi");
  628. /* Take hdmi out of reset */
  629. if (!IS_ERR(hdmi->reset))
  630. reset_control_deassert(hdmi->reset);
  631. platform_set_drvdata(pdev, hdmi);
  632. return component_add(&pdev->dev, &sti_hdmi_ops);
  633. }
  634. static int sti_hdmi_remove(struct platform_device *pdev)
  635. {
  636. component_del(&pdev->dev, &sti_hdmi_ops);
  637. return 0;
  638. }
  639. struct platform_driver sti_hdmi_driver = {
  640. .driver = {
  641. .name = "sti-hdmi",
  642. .owner = THIS_MODULE,
  643. .of_match_table = hdmi_of_match,
  644. },
  645. .probe = sti_hdmi_probe,
  646. .remove = sti_hdmi_remove,
  647. };
  648. module_platform_driver(sti_hdmi_driver);
  649. MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
  650. MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
  651. MODULE_LICENSE("GPL");