clk-divider.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465
  1. /*
  2. * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  3. * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
  4. * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Adjustable divider clock implementation
  11. */
  12. #include <linux/clk-provider.h>
  13. #include <linux/module.h>
  14. #include <linux/slab.h>
  15. #include <linux/io.h>
  16. #include <linux/err.h>
  17. #include <linux/string.h>
  18. #include <linux/log2.h>
  19. /*
  20. * DOC: basic adjustable divider clock that cannot gate
  21. *
  22. * Traits of this clock:
  23. * prepare - clk_prepare only ensures that parents are prepared
  24. * enable - clk_enable only ensures that parents are enabled
  25. * rate - rate is adjustable. clk->rate = DIV_ROUND_UP(parent->rate / divisor)
  26. * parent - fixed parent. No clk_set_parent support
  27. */
  28. #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
  29. #define div_mask(d) ((1 << ((d)->width)) - 1)
  30. static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
  31. {
  32. unsigned int maxdiv = 0;
  33. const struct clk_div_table *clkt;
  34. for (clkt = table; clkt->div; clkt++)
  35. if (clkt->div > maxdiv)
  36. maxdiv = clkt->div;
  37. return maxdiv;
  38. }
  39. static unsigned int _get_table_mindiv(const struct clk_div_table *table)
  40. {
  41. unsigned int mindiv = UINT_MAX;
  42. const struct clk_div_table *clkt;
  43. for (clkt = table; clkt->div; clkt++)
  44. if (clkt->div < mindiv)
  45. mindiv = clkt->div;
  46. return mindiv;
  47. }
  48. static unsigned int _get_maxdiv(struct clk_divider *divider)
  49. {
  50. if (divider->flags & CLK_DIVIDER_ONE_BASED)
  51. return div_mask(divider);
  52. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  53. return 1 << div_mask(divider);
  54. if (divider->table)
  55. return _get_table_maxdiv(divider->table);
  56. return div_mask(divider) + 1;
  57. }
  58. static unsigned int _get_table_div(const struct clk_div_table *table,
  59. unsigned int val)
  60. {
  61. const struct clk_div_table *clkt;
  62. for (clkt = table; clkt->div; clkt++)
  63. if (clkt->val == val)
  64. return clkt->div;
  65. return 0;
  66. }
  67. static unsigned int _get_div(struct clk_divider *divider, unsigned int val)
  68. {
  69. if (divider->flags & CLK_DIVIDER_ONE_BASED)
  70. return val;
  71. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  72. return 1 << val;
  73. if (divider->table)
  74. return _get_table_div(divider->table, val);
  75. return val + 1;
  76. }
  77. static unsigned int _get_table_val(const struct clk_div_table *table,
  78. unsigned int div)
  79. {
  80. const struct clk_div_table *clkt;
  81. for (clkt = table; clkt->div; clkt++)
  82. if (clkt->div == div)
  83. return clkt->val;
  84. return 0;
  85. }
  86. static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
  87. {
  88. if (divider->flags & CLK_DIVIDER_ONE_BASED)
  89. return div;
  90. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  91. return __ffs(div);
  92. if (divider->table)
  93. return _get_table_val(divider->table, div);
  94. return div - 1;
  95. }
  96. static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
  97. unsigned long parent_rate)
  98. {
  99. struct clk_divider *divider = to_clk_divider(hw);
  100. unsigned int div, val;
  101. val = clk_readl(divider->reg) >> divider->shift;
  102. val &= div_mask(divider);
  103. div = _get_div(divider, val);
  104. if (!div) {
  105. WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
  106. "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
  107. __clk_get_name(hw->clk));
  108. return parent_rate;
  109. }
  110. return DIV_ROUND_UP(parent_rate, div);
  111. }
  112. /*
  113. * The reverse of DIV_ROUND_UP: The maximum number which
  114. * divided by m is r
  115. */
  116. #define MULT_ROUND_UP(r, m) ((r) * (m) + (m) - 1)
  117. static bool _is_valid_table_div(const struct clk_div_table *table,
  118. unsigned int div)
  119. {
  120. const struct clk_div_table *clkt;
  121. for (clkt = table; clkt->div; clkt++)
  122. if (clkt->div == div)
  123. return true;
  124. return false;
  125. }
  126. static bool _is_valid_div(struct clk_divider *divider, unsigned int div)
  127. {
  128. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  129. return is_power_of_2(div);
  130. if (divider->table)
  131. return _is_valid_table_div(divider->table, div);
  132. return true;
  133. }
  134. static int _round_up_table(const struct clk_div_table *table, int div)
  135. {
  136. const struct clk_div_table *clkt;
  137. int up = INT_MAX;
  138. for (clkt = table; clkt->div; clkt++) {
  139. if (clkt->div == div)
  140. return clkt->div;
  141. else if (clkt->div < div)
  142. continue;
  143. if ((clkt->div - div) < (up - div))
  144. up = clkt->div;
  145. }
  146. return up;
  147. }
  148. static int _round_down_table(const struct clk_div_table *table, int div)
  149. {
  150. const struct clk_div_table *clkt;
  151. int down = _get_table_mindiv(table);
  152. for (clkt = table; clkt->div; clkt++) {
  153. if (clkt->div == div)
  154. return clkt->div;
  155. else if (clkt->div > div)
  156. continue;
  157. if ((div - clkt->div) < (div - down))
  158. down = clkt->div;
  159. }
  160. return down;
  161. }
  162. static int _div_round_up(struct clk_divider *divider,
  163. unsigned long parent_rate, unsigned long rate)
  164. {
  165. int div = DIV_ROUND_UP(parent_rate, rate);
  166. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  167. div = __roundup_pow_of_two(div);
  168. if (divider->table)
  169. div = _round_up_table(divider->table, div);
  170. return div;
  171. }
  172. static int _div_round_closest(struct clk_divider *divider,
  173. unsigned long parent_rate, unsigned long rate)
  174. {
  175. int up, down, div;
  176. up = down = div = DIV_ROUND_CLOSEST(parent_rate, rate);
  177. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) {
  178. up = __roundup_pow_of_two(div);
  179. down = __rounddown_pow_of_two(div);
  180. } else if (divider->table) {
  181. up = _round_up_table(divider->table, div);
  182. down = _round_down_table(divider->table, div);
  183. }
  184. return (up - div) <= (div - down) ? up : down;
  185. }
  186. static int _div_round(struct clk_divider *divider, unsigned long parent_rate,
  187. unsigned long rate)
  188. {
  189. if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
  190. return _div_round_closest(divider, parent_rate, rate);
  191. return _div_round_up(divider, parent_rate, rate);
  192. }
  193. static bool _is_best_div(struct clk_divider *divider,
  194. unsigned long rate, unsigned long now, unsigned long best)
  195. {
  196. if (divider->flags & CLK_DIVIDER_ROUND_CLOSEST)
  197. return abs(rate - now) < abs(rate - best);
  198. return now <= rate && now > best;
  199. }
  200. static int _next_div(struct clk_divider *divider, int div)
  201. {
  202. div++;
  203. if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
  204. return __roundup_pow_of_two(div);
  205. if (divider->table)
  206. return _round_up_table(divider->table, div);
  207. return div;
  208. }
  209. static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
  210. unsigned long *best_parent_rate)
  211. {
  212. struct clk_divider *divider = to_clk_divider(hw);
  213. int i, bestdiv = 0;
  214. unsigned long parent_rate, best = 0, now, maxdiv;
  215. unsigned long parent_rate_saved = *best_parent_rate;
  216. if (!rate)
  217. rate = 1;
  218. maxdiv = _get_maxdiv(divider);
  219. if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
  220. parent_rate = *best_parent_rate;
  221. bestdiv = _div_round(divider, parent_rate, rate);
  222. bestdiv = bestdiv == 0 ? 1 : bestdiv;
  223. bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
  224. return bestdiv;
  225. }
  226. /*
  227. * The maximum divider we can use without overflowing
  228. * unsigned long in rate * i below
  229. */
  230. maxdiv = min(ULONG_MAX / rate, maxdiv);
  231. for (i = 1; i <= maxdiv; i = _next_div(divider, i)) {
  232. if (!_is_valid_div(divider, i))
  233. continue;
  234. if (rate * i == parent_rate_saved) {
  235. /*
  236. * It's the most ideal case if the requested rate can be
  237. * divided from parent clock without needing to change
  238. * parent rate, so return the divider immediately.
  239. */
  240. *best_parent_rate = parent_rate_saved;
  241. return i;
  242. }
  243. parent_rate = __clk_round_rate(__clk_get_parent(hw->clk),
  244. MULT_ROUND_UP(rate, i));
  245. now = DIV_ROUND_UP(parent_rate, i);
  246. if (_is_best_div(divider, rate, now, best)) {
  247. bestdiv = i;
  248. best = now;
  249. *best_parent_rate = parent_rate;
  250. }
  251. }
  252. if (!bestdiv) {
  253. bestdiv = _get_maxdiv(divider);
  254. *best_parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), 1);
  255. }
  256. return bestdiv;
  257. }
  258. static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
  259. unsigned long *prate)
  260. {
  261. int div;
  262. div = clk_divider_bestdiv(hw, rate, prate);
  263. return DIV_ROUND_UP(*prate, div);
  264. }
  265. static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
  266. unsigned long parent_rate)
  267. {
  268. struct clk_divider *divider = to_clk_divider(hw);
  269. unsigned int div, value;
  270. unsigned long flags = 0;
  271. u32 val;
  272. div = DIV_ROUND_UP(parent_rate, rate);
  273. if (!_is_valid_div(divider, div))
  274. return -EINVAL;
  275. value = _get_val(divider, div);
  276. if (value > div_mask(divider))
  277. value = div_mask(divider);
  278. if (divider->lock)
  279. spin_lock_irqsave(divider->lock, flags);
  280. if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
  281. val = div_mask(divider) << (divider->shift + 16);
  282. } else {
  283. val = clk_readl(divider->reg);
  284. val &= ~(div_mask(divider) << divider->shift);
  285. }
  286. val |= value << divider->shift;
  287. clk_writel(val, divider->reg);
  288. if (divider->lock)
  289. spin_unlock_irqrestore(divider->lock, flags);
  290. return 0;
  291. }
  292. const struct clk_ops clk_divider_ops = {
  293. .recalc_rate = clk_divider_recalc_rate,
  294. .round_rate = clk_divider_round_rate,
  295. .set_rate = clk_divider_set_rate,
  296. };
  297. EXPORT_SYMBOL_GPL(clk_divider_ops);
  298. const struct clk_ops clk_divider_ro_ops = {
  299. .recalc_rate = clk_divider_recalc_rate,
  300. };
  301. EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
  302. static struct clk *_register_divider(struct device *dev, const char *name,
  303. const char *parent_name, unsigned long flags,
  304. void __iomem *reg, u8 shift, u8 width,
  305. u8 clk_divider_flags, const struct clk_div_table *table,
  306. spinlock_t *lock)
  307. {
  308. struct clk_divider *div;
  309. struct clk *clk;
  310. struct clk_init_data init;
  311. if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
  312. if (width + shift > 16) {
  313. pr_warn("divider value exceeds LOWORD field\n");
  314. return ERR_PTR(-EINVAL);
  315. }
  316. }
  317. /* allocate the divider */
  318. div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
  319. if (!div) {
  320. pr_err("%s: could not allocate divider clk\n", __func__);
  321. return ERR_PTR(-ENOMEM);
  322. }
  323. init.name = name;
  324. if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
  325. init.ops = &clk_divider_ro_ops;
  326. else
  327. init.ops = &clk_divider_ops;
  328. init.flags = flags | CLK_IS_BASIC;
  329. init.parent_names = (parent_name ? &parent_name: NULL);
  330. init.num_parents = (parent_name ? 1 : 0);
  331. /* struct clk_divider assignments */
  332. div->reg = reg;
  333. div->shift = shift;
  334. div->width = width;
  335. div->flags = clk_divider_flags;
  336. div->lock = lock;
  337. div->hw.init = &init;
  338. div->table = table;
  339. /* register the clock */
  340. clk = clk_register(dev, &div->hw);
  341. if (IS_ERR(clk))
  342. kfree(div);
  343. return clk;
  344. }
  345. /**
  346. * clk_register_divider - register a divider clock with the clock framework
  347. * @dev: device registering this clock
  348. * @name: name of this clock
  349. * @parent_name: name of clock's parent
  350. * @flags: framework-specific flags
  351. * @reg: register address to adjust divider
  352. * @shift: number of bits to shift the bitfield
  353. * @width: width of the bitfield
  354. * @clk_divider_flags: divider-specific flags for this clock
  355. * @lock: shared register lock for this clock
  356. */
  357. struct clk *clk_register_divider(struct device *dev, const char *name,
  358. const char *parent_name, unsigned long flags,
  359. void __iomem *reg, u8 shift, u8 width,
  360. u8 clk_divider_flags, spinlock_t *lock)
  361. {
  362. return _register_divider(dev, name, parent_name, flags, reg, shift,
  363. width, clk_divider_flags, NULL, lock);
  364. }
  365. EXPORT_SYMBOL_GPL(clk_register_divider);
  366. /**
  367. * clk_register_divider_table - register a table based divider clock with
  368. * the clock framework
  369. * @dev: device registering this clock
  370. * @name: name of this clock
  371. * @parent_name: name of clock's parent
  372. * @flags: framework-specific flags
  373. * @reg: register address to adjust divider
  374. * @shift: number of bits to shift the bitfield
  375. * @width: width of the bitfield
  376. * @clk_divider_flags: divider-specific flags for this clock
  377. * @table: array of divider/value pairs ending with a div set to 0
  378. * @lock: shared register lock for this clock
  379. */
  380. struct clk *clk_register_divider_table(struct device *dev, const char *name,
  381. const char *parent_name, unsigned long flags,
  382. void __iomem *reg, u8 shift, u8 width,
  383. u8 clk_divider_flags, const struct clk_div_table *table,
  384. spinlock_t *lock)
  385. {
  386. return _register_divider(dev, name, parent_name, flags, reg, shift,
  387. width, clk_divider_flags, table, lock);
  388. }
  389. EXPORT_SYMBOL_GPL(clk_register_divider_table);