i40e_txrx.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*******************************************************************************
  3. *
  4. * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
  5. * Copyright(c) 2013 - 2016 Intel Corporation.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along
  17. * with this program. If not, see <http://www.gnu.org/licenses/>.
  18. *
  19. * The full GNU General Public License is included in this distribution in
  20. * the file called "COPYING".
  21. *
  22. * Contact Information:
  23. * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25. *
  26. ******************************************************************************/
  27. #ifndef _I40E_TXRX_H_
  28. #define _I40E_TXRX_H_
  29. /* Interrupt Throttling and Rate Limiting Goodies */
  30. #define I40E_DEFAULT_IRQ_WORK 256
  31. /* The datasheet for the X710 and XL710 indicate that the maximum value for
  32. * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec
  33. * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing
  34. * the register value which is divided by 2 lets use the actual values and
  35. * avoid an excessive amount of translation.
  36. */
  37. #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
  38. #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */
  39. #define I40E_MIN_ITR 2 /* reg uses 2 usec resolution */
  40. #define I40E_ITR_100K 10 /* all values below must be even */
  41. #define I40E_ITR_50K 20
  42. #define I40E_ITR_20K 50
  43. #define I40E_ITR_18K 60
  44. #define I40E_ITR_8K 122
  45. #define I40E_MAX_ITR 8160 /* maximum value as per datasheet */
  46. #define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC)
  47. #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK)
  48. #define ITR_IS_DYNAMIC(setting) (!!((setting) & I40E_ITR_DYNAMIC))
  49. #define I40E_ITR_RX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC)
  50. #define I40E_ITR_TX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC)
  51. /* 0x40 is the enable bit for interrupt rate limiting, and must be set if
  52. * the value of the rate limit is non-zero
  53. */
  54. #define INTRL_ENA BIT(6)
  55. #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */
  56. #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2)
  57. #define INTRL_USEC_TO_REG(set) ((set) ? ((set) >> 2) | INTRL_ENA : 0)
  58. #define I40E_INTRL_8K 125 /* 8000 ints/sec */
  59. #define I40E_INTRL_62K 16 /* 62500 ints/sec */
  60. #define I40E_INTRL_83K 12 /* 83333 ints/sec */
  61. #define I40E_QUEUE_END_OF_LIST 0x7FF
  62. /* this enum matches hardware bits and is meant to be used by DYN_CTLN
  63. * registers and QINT registers or more generally anywhere in the manual
  64. * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
  65. * register but instead is a special value meaning "don't update" ITR0/1/2.
  66. */
  67. enum i40e_dyn_idx_t {
  68. I40E_IDX_ITR0 = 0,
  69. I40E_IDX_ITR1 = 1,
  70. I40E_IDX_ITR2 = 2,
  71. I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
  72. };
  73. /* these are indexes into ITRN registers */
  74. #define I40E_RX_ITR I40E_IDX_ITR0
  75. #define I40E_TX_ITR I40E_IDX_ITR1
  76. #define I40E_PE_ITR I40E_IDX_ITR2
  77. /* Supported RSS offloads */
  78. #define I40E_DEFAULT_RSS_HENA ( \
  79. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
  80. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
  81. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
  82. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
  83. BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
  84. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
  85. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
  86. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
  87. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
  88. BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
  89. BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
  90. #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \
  91. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
  92. BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
  93. BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
  94. BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
  95. BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
  96. BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP))
  97. /* Supported Rx Buffer Sizes (a multiple of 128) */
  98. #define I40E_RXBUFFER_256 256
  99. #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */
  100. #define I40E_RXBUFFER_2048 2048
  101. #define I40E_RXBUFFER_3072 3072 /* Used for large frames w/ padding */
  102. #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */
  103. /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we
  104. * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
  105. * this adds up to 512 bytes of extra data meaning the smallest allocation
  106. * we could have is 1K.
  107. * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab)
  108. * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab)
  109. */
  110. #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256
  111. #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
  112. #define i40e_rx_desc i40e_32byte_rx_desc
  113. #define I40E_RX_DMA_ATTR \
  114. (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
  115. /* Attempt to maximize the headroom available for incoming frames. We
  116. * use a 2K buffer for receives and need 1536/1534 to store the data for
  117. * the frame. This leaves us with 512 bytes of room. From that we need
  118. * to deduct the space needed for the shared info and the padding needed
  119. * to IP align the frame.
  120. *
  121. * Note: For cache line sizes 256 or larger this value is going to end
  122. * up negative. In these cases we should fall back to the legacy
  123. * receive path.
  124. */
  125. #if (PAGE_SIZE < 8192)
  126. #define I40E_2K_TOO_SMALL_WITH_PADDING \
  127. ((NET_SKB_PAD + I40E_RXBUFFER_1536) > SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048))
  128. static inline int i40e_compute_pad(int rx_buf_len)
  129. {
  130. int page_size, pad_size;
  131. page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
  132. pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
  133. return pad_size;
  134. }
  135. static inline int i40e_skb_pad(void)
  136. {
  137. int rx_buf_len;
  138. /* If a 2K buffer cannot handle a standard Ethernet frame then
  139. * optimize padding for a 3K buffer instead of a 1.5K buffer.
  140. *
  141. * For a 3K buffer we need to add enough padding to allow for
  142. * tailroom due to NET_IP_ALIGN possibly shifting us out of
  143. * cache-line alignment.
  144. */
  145. if (I40E_2K_TOO_SMALL_WITH_PADDING)
  146. rx_buf_len = I40E_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
  147. else
  148. rx_buf_len = I40E_RXBUFFER_1536;
  149. /* if needed make room for NET_IP_ALIGN */
  150. rx_buf_len -= NET_IP_ALIGN;
  151. return i40e_compute_pad(rx_buf_len);
  152. }
  153. #define I40E_SKB_PAD i40e_skb_pad()
  154. #else
  155. #define I40E_2K_TOO_SMALL_WITH_PADDING false
  156. #define I40E_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
  157. #endif
  158. /**
  159. * i40e_test_staterr - tests bits in Rx descriptor status and error fields
  160. * @rx_desc: pointer to receive descriptor (in le64 format)
  161. * @stat_err_bits: value to mask
  162. *
  163. * This function does some fast chicanery in order to return the
  164. * value of the mask which is really only used for boolean tests.
  165. * The status_error_len doesn't need to be shifted because it begins
  166. * at offset zero.
  167. */
  168. static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc,
  169. const u64 stat_err_bits)
  170. {
  171. return !!(rx_desc->wb.qword1.status_error_len &
  172. cpu_to_le64(stat_err_bits));
  173. }
  174. /* How many Rx Buffers do we bundle into one write to the hardware ? */
  175. #define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */
  176. #define I40E_RX_INCREMENT(r, i) \
  177. do { \
  178. (i)++; \
  179. if ((i) == (r)->count) \
  180. i = 0; \
  181. r->next_to_clean = i; \
  182. } while (0)
  183. #define I40E_RX_NEXT_DESC(r, i, n) \
  184. do { \
  185. (i)++; \
  186. if ((i) == (r)->count) \
  187. i = 0; \
  188. (n) = I40E_RX_DESC((r), (i)); \
  189. } while (0)
  190. #define I40E_RX_NEXT_DESC_PREFETCH(r, i, n) \
  191. do { \
  192. I40E_RX_NEXT_DESC((r), (i), (n)); \
  193. prefetch((n)); \
  194. } while (0)
  195. #define I40E_MAX_BUFFER_TXD 8
  196. #define I40E_MIN_TX_LEN 17
  197. /* The size limit for a transmit buffer in a descriptor is (16K - 1).
  198. * In order to align with the read requests we will align the value to
  199. * the nearest 4K which represents our maximum read request size.
  200. */
  201. #define I40E_MAX_READ_REQ_SIZE 4096
  202. #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1)
  203. #define I40E_MAX_DATA_PER_TXD_ALIGNED \
  204. (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1))
  205. /**
  206. * i40e_txd_use_count - estimate the number of descriptors needed for Tx
  207. * @size: transmit request size in bytes
  208. *
  209. * Due to hardware alignment restrictions (4K alignment), we need to
  210. * assume that we can have no more than 12K of data per descriptor, even
  211. * though each descriptor can take up to 16K - 1 bytes of aligned memory.
  212. * Thus, we need to divide by 12K. But division is slow! Instead,
  213. * we decompose the operation into shifts and one relatively cheap
  214. * multiply operation.
  215. *
  216. * To divide by 12K, we first divide by 4K, then divide by 3:
  217. * To divide by 4K, shift right by 12 bits
  218. * To divide by 3, multiply by 85, then divide by 256
  219. * (Divide by 256 is done by shifting right by 8 bits)
  220. * Finally, we add one to round up. Because 256 isn't an exact multiple of
  221. * 3, we'll underestimate near each multiple of 12K. This is actually more
  222. * accurate as we have 4K - 1 of wiggle room that we can fit into the last
  223. * segment. For our purposes this is accurate out to 1M which is orders of
  224. * magnitude greater than our largest possible GSO size.
  225. *
  226. * This would then be implemented as:
  227. * return (((size >> 12) * 85) >> 8) + 1;
  228. *
  229. * Since multiplication and division are commutative, we can reorder
  230. * operations into:
  231. * return ((size * 85) >> 20) + 1;
  232. */
  233. static inline unsigned int i40e_txd_use_count(unsigned int size)
  234. {
  235. return ((size * 85) >> 20) + 1;
  236. }
  237. /* Tx Descriptors needed, worst case */
  238. #define DESC_NEEDED (MAX_SKB_FRAGS + 6)
  239. #define I40E_MIN_DESC_PENDING 4
  240. #define I40E_TX_FLAGS_HW_VLAN BIT(1)
  241. #define I40E_TX_FLAGS_SW_VLAN BIT(2)
  242. #define I40E_TX_FLAGS_TSO BIT(3)
  243. #define I40E_TX_FLAGS_IPV4 BIT(4)
  244. #define I40E_TX_FLAGS_IPV6 BIT(5)
  245. #define I40E_TX_FLAGS_FCCRC BIT(6)
  246. #define I40E_TX_FLAGS_FSO BIT(7)
  247. #define I40E_TX_FLAGS_FD_SB BIT(9)
  248. #define I40E_TX_FLAGS_VXLAN_TUNNEL BIT(10)
  249. #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000
  250. #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000
  251. #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29
  252. #define I40E_TX_FLAGS_VLAN_SHIFT 16
  253. struct i40e_tx_buffer {
  254. struct i40e_tx_desc *next_to_watch;
  255. union {
  256. struct sk_buff *skb;
  257. void *raw_buf;
  258. };
  259. unsigned int bytecount;
  260. unsigned short gso_segs;
  261. DEFINE_DMA_UNMAP_ADDR(dma);
  262. DEFINE_DMA_UNMAP_LEN(len);
  263. u32 tx_flags;
  264. };
  265. struct i40e_rx_buffer {
  266. dma_addr_t dma;
  267. struct page *page;
  268. #if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
  269. __u32 page_offset;
  270. #else
  271. __u16 page_offset;
  272. #endif
  273. __u16 pagecnt_bias;
  274. };
  275. struct i40e_queue_stats {
  276. u64 packets;
  277. u64 bytes;
  278. };
  279. struct i40e_tx_queue_stats {
  280. u64 restart_queue;
  281. u64 tx_busy;
  282. u64 tx_done_old;
  283. u64 tx_linearize;
  284. u64 tx_force_wb;
  285. int prev_pkt_ctr;
  286. u64 tx_lost_interrupt;
  287. };
  288. struct i40e_rx_queue_stats {
  289. u64 non_eop_descs;
  290. u64 alloc_page_failed;
  291. u64 alloc_buff_failed;
  292. u64 page_reuse_count;
  293. u64 realloc_count;
  294. };
  295. enum i40e_ring_state_t {
  296. __I40E_TX_FDIR_INIT_DONE,
  297. __I40E_TX_XPS_INIT_DONE,
  298. __I40E_RING_STATE_NBITS /* must be last */
  299. };
  300. /* some useful defines for virtchannel interface, which
  301. * is the only remaining user of header split
  302. */
  303. #define I40E_RX_DTYPE_NO_SPLIT 0
  304. #define I40E_RX_DTYPE_HEADER_SPLIT 1
  305. #define I40E_RX_DTYPE_SPLIT_ALWAYS 2
  306. #define I40E_RX_SPLIT_L2 0x1
  307. #define I40E_RX_SPLIT_IP 0x2
  308. #define I40E_RX_SPLIT_TCP_UDP 0x4
  309. #define I40E_RX_SPLIT_SCTP 0x8
  310. /* struct that defines a descriptor ring, associated with a VSI */
  311. struct i40e_ring {
  312. struct i40e_ring *next; /* pointer to next ring in q_vector */
  313. void *desc; /* Descriptor ring memory */
  314. struct device *dev; /* Used for DMA mapping */
  315. struct net_device *netdev; /* netdev ring maps to */
  316. union {
  317. struct i40e_tx_buffer *tx_bi;
  318. struct i40e_rx_buffer *rx_bi;
  319. };
  320. DECLARE_BITMAP(state, __I40E_RING_STATE_NBITS);
  321. u16 queue_index; /* Queue number of ring */
  322. u8 dcb_tc; /* Traffic class of ring */
  323. u8 __iomem *tail;
  324. /* high bit set means dynamic, use accessors routines to read/write.
  325. * hardware only supports 2us resolution for the ITR registers.
  326. * these values always store the USER setting, and must be converted
  327. * before programming to a register.
  328. */
  329. u16 itr_setting;
  330. u16 count; /* Number of descriptors */
  331. u16 reg_idx; /* HW register index of the ring */
  332. u16 rx_buf_len;
  333. /* used in interrupt processing */
  334. u16 next_to_use;
  335. u16 next_to_clean;
  336. u8 atr_sample_rate;
  337. u8 atr_count;
  338. bool ring_active; /* is ring online or not */
  339. bool arm_wb; /* do something to arm write back */
  340. u8 packet_stride;
  341. u16 flags;
  342. #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0)
  343. #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1)
  344. /* stats structs */
  345. struct i40e_queue_stats stats;
  346. struct u64_stats_sync syncp;
  347. union {
  348. struct i40e_tx_queue_stats tx_stats;
  349. struct i40e_rx_queue_stats rx_stats;
  350. };
  351. unsigned int size; /* length of descriptor ring in bytes */
  352. dma_addr_t dma; /* physical address of ring */
  353. struct i40e_vsi *vsi; /* Backreference to associated VSI */
  354. struct i40e_q_vector *q_vector; /* Backreference to associated vector */
  355. struct rcu_head rcu; /* to avoid race on free */
  356. u16 next_to_alloc;
  357. struct sk_buff *skb; /* When i40evf_clean_rx_ring_irq() must
  358. * return before it sees the EOP for
  359. * the current packet, we save that skb
  360. * here and resume receiving this
  361. * packet the next time
  362. * i40evf_clean_rx_ring_irq() is called
  363. * for this ring.
  364. */
  365. } ____cacheline_internodealigned_in_smp;
  366. static inline bool ring_uses_build_skb(struct i40e_ring *ring)
  367. {
  368. return !!(ring->flags & I40E_RXR_FLAGS_BUILD_SKB_ENABLED);
  369. }
  370. static inline void set_ring_build_skb_enabled(struct i40e_ring *ring)
  371. {
  372. ring->flags |= I40E_RXR_FLAGS_BUILD_SKB_ENABLED;
  373. }
  374. static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring)
  375. {
  376. ring->flags &= ~I40E_RXR_FLAGS_BUILD_SKB_ENABLED;
  377. }
  378. #define I40E_ITR_ADAPTIVE_MIN_INC 0x0002
  379. #define I40E_ITR_ADAPTIVE_MIN_USECS 0x0002
  380. #define I40E_ITR_ADAPTIVE_MAX_USECS 0x007e
  381. #define I40E_ITR_ADAPTIVE_LATENCY 0x8000
  382. #define I40E_ITR_ADAPTIVE_BULK 0x0000
  383. #define ITR_IS_BULK(x) (!((x) & I40E_ITR_ADAPTIVE_LATENCY))
  384. struct i40e_ring_container {
  385. struct i40e_ring *ring; /* pointer to linked list of ring(s) */
  386. unsigned long next_update; /* jiffies value of next update */
  387. unsigned int total_bytes; /* total bytes processed this int */
  388. unsigned int total_packets; /* total packets processed this int */
  389. u16 count;
  390. u16 target_itr; /* target ITR setting for ring(s) */
  391. u16 current_itr; /* current ITR setting for ring(s) */
  392. };
  393. /* iterator for handling rings in ring container */
  394. #define i40e_for_each_ring(pos, head) \
  395. for (pos = (head).ring; pos != NULL; pos = pos->next)
  396. static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring)
  397. {
  398. #if (PAGE_SIZE < 8192)
  399. if (ring->rx_buf_len > (PAGE_SIZE / 2))
  400. return 1;
  401. #endif
  402. return 0;
  403. }
  404. #define i40e_rx_pg_size(_ring) (PAGE_SIZE << i40e_rx_pg_order(_ring))
  405. bool i40evf_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count);
  406. netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
  407. void i40evf_clean_tx_ring(struct i40e_ring *tx_ring);
  408. void i40evf_clean_rx_ring(struct i40e_ring *rx_ring);
  409. int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring);
  410. int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring);
  411. void i40evf_free_tx_resources(struct i40e_ring *tx_ring);
  412. void i40evf_free_rx_resources(struct i40e_ring *rx_ring);
  413. int i40evf_napi_poll(struct napi_struct *napi, int budget);
  414. void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector);
  415. u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw);
  416. void i40evf_detect_recover_hung(struct i40e_vsi *vsi);
  417. int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size);
  418. bool __i40evf_chk_linearize(struct sk_buff *skb);
  419. /**
  420. * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed
  421. * @skb: send buffer
  422. * @tx_ring: ring to send buffer on
  423. *
  424. * Returns number of data descriptors needed for this skb. Returns 0 to indicate
  425. * there is not enough descriptors available in this ring since we need at least
  426. * one descriptor.
  427. **/
  428. static inline int i40e_xmit_descriptor_count(struct sk_buff *skb)
  429. {
  430. const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
  431. unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
  432. int count = 0, size = skb_headlen(skb);
  433. for (;;) {
  434. count += i40e_txd_use_count(size);
  435. if (!nr_frags--)
  436. break;
  437. size = skb_frag_size(frag++);
  438. }
  439. return count;
  440. }
  441. /**
  442. * i40e_maybe_stop_tx - 1st level check for Tx stop conditions
  443. * @tx_ring: the ring to be checked
  444. * @size: the size buffer we want to assure is available
  445. *
  446. * Returns 0 if stop is not needed
  447. **/
  448. static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
  449. {
  450. if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
  451. return 0;
  452. return __i40evf_maybe_stop_tx(tx_ring, size);
  453. }
  454. /**
  455. * i40e_chk_linearize - Check if there are more than 8 fragments per packet
  456. * @skb: send buffer
  457. * @count: number of buffers used
  458. *
  459. * Note: Our HW can't scatter-gather more than 8 fragments to build
  460. * a packet on the wire and so we need to figure out the cases where we
  461. * need to linearize the skb.
  462. **/
  463. static inline bool i40e_chk_linearize(struct sk_buff *skb, int count)
  464. {
  465. /* Both TSO and single send will work if count is less than 8 */
  466. if (likely(count < I40E_MAX_BUFFER_TXD))
  467. return false;
  468. if (skb_is_gso(skb))
  469. return __i40evf_chk_linearize(skb);
  470. /* we can support up to 8 data buffers for a single send */
  471. return count != I40E_MAX_BUFFER_TXD;
  472. }
  473. /**
  474. * @ring: Tx ring to find the netdev equivalent of
  475. **/
  476. static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring)
  477. {
  478. return netdev_get_tx_queue(ring->netdev, ring->queue_index);
  479. }
  480. #endif /* _I40E_TXRX_H_ */