rtc-rs5c348.c 6.2 KB

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  1. /*
  2. * A SPI driver for the Ricoh RS5C348 RTC
  3. *
  4. * Copyright (C) 2006 Atsushi Nemoto <anemo@mba.ocn.ne.jp>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * The board specific init code should provide characteristics of this
  11. * device:
  12. * Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS
  13. */
  14. #include <linux/bcd.h>
  15. #include <linux/delay.h>
  16. #include <linux/device.h>
  17. #include <linux/errno.h>
  18. #include <linux/init.h>
  19. #include <linux/kernel.h>
  20. #include <linux/string.h>
  21. #include <linux/slab.h>
  22. #include <linux/rtc.h>
  23. #include <linux/workqueue.h>
  24. #include <linux/spi/spi.h>
  25. #include <linux/module.h>
  26. #define RS5C348_REG_SECS 0
  27. #define RS5C348_REG_MINS 1
  28. #define RS5C348_REG_HOURS 2
  29. #define RS5C348_REG_WDAY 3
  30. #define RS5C348_REG_DAY 4
  31. #define RS5C348_REG_MONTH 5
  32. #define RS5C348_REG_YEAR 6
  33. #define RS5C348_REG_CTL1 14
  34. #define RS5C348_REG_CTL2 15
  35. #define RS5C348_SECS_MASK 0x7f
  36. #define RS5C348_MINS_MASK 0x7f
  37. #define RS5C348_HOURS_MASK 0x3f
  38. #define RS5C348_WDAY_MASK 0x03
  39. #define RS5C348_DAY_MASK 0x3f
  40. #define RS5C348_MONTH_MASK 0x1f
  41. #define RS5C348_BIT_PM 0x20 /* REG_HOURS */
  42. #define RS5C348_BIT_Y2K 0x80 /* REG_MONTH */
  43. #define RS5C348_BIT_24H 0x20 /* REG_CTL1 */
  44. #define RS5C348_BIT_XSTP 0x10 /* REG_CTL2 */
  45. #define RS5C348_BIT_VDET 0x40 /* REG_CTL2 */
  46. #define RS5C348_CMD_W(addr) (((addr) << 4) | 0x08) /* single write */
  47. #define RS5C348_CMD_R(addr) (((addr) << 4) | 0x0c) /* single read */
  48. #define RS5C348_CMD_MW(addr) (((addr) << 4) | 0x00) /* burst write */
  49. #define RS5C348_CMD_MR(addr) (((addr) << 4) | 0x04) /* burst read */
  50. struct rs5c348_plat_data {
  51. struct rtc_device *rtc;
  52. int rtc_24h;
  53. };
  54. static int
  55. rs5c348_rtc_set_time(struct device *dev, struct rtc_time *tm)
  56. {
  57. struct spi_device *spi = to_spi_device(dev);
  58. struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
  59. u8 txbuf[5+7], *txp;
  60. int ret;
  61. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
  62. if (ret < 0)
  63. return ret;
  64. if (ret & RS5C348_BIT_XSTP) {
  65. txbuf[0] = RS5C348_CMD_W(RS5C348_REG_CTL2);
  66. txbuf[1] = 0;
  67. ret = spi_write_then_read(spi, txbuf, 2, NULL, 0);
  68. if (ret < 0)
  69. return ret;
  70. }
  71. /* Transfer 5 bytes before writing SEC. This gives 31us for carry. */
  72. txp = txbuf;
  73. txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  74. txbuf[1] = 0; /* dummy */
  75. txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  76. txbuf[3] = 0; /* dummy */
  77. txbuf[4] = RS5C348_CMD_MW(RS5C348_REG_SECS); /* cmd, sec, ... */
  78. txp = &txbuf[5];
  79. txp[RS5C348_REG_SECS] = bin2bcd(tm->tm_sec);
  80. txp[RS5C348_REG_MINS] = bin2bcd(tm->tm_min);
  81. if (pdata->rtc_24h) {
  82. txp[RS5C348_REG_HOURS] = bin2bcd(tm->tm_hour);
  83. } else {
  84. /* hour 0 is AM12, noon is PM12 */
  85. txp[RS5C348_REG_HOURS] = bin2bcd((tm->tm_hour + 11) % 12 + 1) |
  86. (tm->tm_hour >= 12 ? RS5C348_BIT_PM : 0);
  87. }
  88. txp[RS5C348_REG_WDAY] = bin2bcd(tm->tm_wday);
  89. txp[RS5C348_REG_DAY] = bin2bcd(tm->tm_mday);
  90. txp[RS5C348_REG_MONTH] = bin2bcd(tm->tm_mon + 1) |
  91. (tm->tm_year >= 100 ? RS5C348_BIT_Y2K : 0);
  92. txp[RS5C348_REG_YEAR] = bin2bcd(tm->tm_year % 100);
  93. /* write in one transfer to avoid data inconsistency */
  94. ret = spi_write_then_read(spi, txbuf, sizeof(txbuf), NULL, 0);
  95. udelay(62); /* Tcsr 62us */
  96. return ret;
  97. }
  98. static int
  99. rs5c348_rtc_read_time(struct device *dev, struct rtc_time *tm)
  100. {
  101. struct spi_device *spi = to_spi_device(dev);
  102. struct rs5c348_plat_data *pdata = dev_get_platdata(&spi->dev);
  103. u8 txbuf[5], rxbuf[7];
  104. int ret;
  105. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL2));
  106. if (ret < 0)
  107. return ret;
  108. if (ret & RS5C348_BIT_VDET)
  109. dev_warn(&spi->dev, "voltage-low detected.\n");
  110. if (ret & RS5C348_BIT_XSTP) {
  111. dev_warn(&spi->dev, "oscillator-stop detected.\n");
  112. return -EINVAL;
  113. }
  114. /* Transfer 5 byte befores reading SEC. This gives 31us for carry. */
  115. txbuf[0] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  116. txbuf[1] = 0; /* dummy */
  117. txbuf[2] = RS5C348_CMD_R(RS5C348_REG_CTL2); /* cmd, ctl2 */
  118. txbuf[3] = 0; /* dummy */
  119. txbuf[4] = RS5C348_CMD_MR(RS5C348_REG_SECS); /* cmd, sec, ... */
  120. /* read in one transfer to avoid data inconsistency */
  121. ret = spi_write_then_read(spi, txbuf, sizeof(txbuf),
  122. rxbuf, sizeof(rxbuf));
  123. udelay(62); /* Tcsr 62us */
  124. if (ret < 0)
  125. return ret;
  126. tm->tm_sec = bcd2bin(rxbuf[RS5C348_REG_SECS] & RS5C348_SECS_MASK);
  127. tm->tm_min = bcd2bin(rxbuf[RS5C348_REG_MINS] & RS5C348_MINS_MASK);
  128. tm->tm_hour = bcd2bin(rxbuf[RS5C348_REG_HOURS] & RS5C348_HOURS_MASK);
  129. if (!pdata->rtc_24h) {
  130. if (rxbuf[RS5C348_REG_HOURS] & RS5C348_BIT_PM) {
  131. tm->tm_hour -= 20;
  132. tm->tm_hour %= 12;
  133. tm->tm_hour += 12;
  134. } else
  135. tm->tm_hour %= 12;
  136. }
  137. tm->tm_wday = bcd2bin(rxbuf[RS5C348_REG_WDAY] & RS5C348_WDAY_MASK);
  138. tm->tm_mday = bcd2bin(rxbuf[RS5C348_REG_DAY] & RS5C348_DAY_MASK);
  139. tm->tm_mon =
  140. bcd2bin(rxbuf[RS5C348_REG_MONTH] & RS5C348_MONTH_MASK) - 1;
  141. /* year is 1900 + tm->tm_year */
  142. tm->tm_year = bcd2bin(rxbuf[RS5C348_REG_YEAR]) +
  143. ((rxbuf[RS5C348_REG_MONTH] & RS5C348_BIT_Y2K) ? 100 : 0);
  144. return 0;
  145. }
  146. static const struct rtc_class_ops rs5c348_rtc_ops = {
  147. .read_time = rs5c348_rtc_read_time,
  148. .set_time = rs5c348_rtc_set_time,
  149. };
  150. static int rs5c348_probe(struct spi_device *spi)
  151. {
  152. int ret;
  153. struct rtc_device *rtc;
  154. struct rs5c348_plat_data *pdata;
  155. pdata = devm_kzalloc(&spi->dev, sizeof(struct rs5c348_plat_data),
  156. GFP_KERNEL);
  157. if (!pdata)
  158. return -ENOMEM;
  159. spi->dev.platform_data = pdata;
  160. /* Check D7 of SECOND register */
  161. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_SECS));
  162. if (ret < 0 || (ret & 0x80)) {
  163. dev_err(&spi->dev, "not found.\n");
  164. return ret;
  165. }
  166. dev_info(&spi->dev, "spiclk %u KHz.\n",
  167. (spi->max_speed_hz + 500) / 1000);
  168. ret = spi_w8r8(spi, RS5C348_CMD_R(RS5C348_REG_CTL1));
  169. if (ret < 0)
  170. return ret;
  171. if (ret & RS5C348_BIT_24H)
  172. pdata->rtc_24h = 1;
  173. rtc = devm_rtc_allocate_device(&spi->dev);
  174. if (IS_ERR(rtc))
  175. return PTR_ERR(rtc);
  176. pdata->rtc = rtc;
  177. rtc->ops = &rs5c348_rtc_ops;
  178. return rtc_register_device(rtc);
  179. }
  180. static struct spi_driver rs5c348_driver = {
  181. .driver = {
  182. .name = "rtc-rs5c348",
  183. },
  184. .probe = rs5c348_probe,
  185. };
  186. module_spi_driver(rs5c348_driver);
  187. MODULE_AUTHOR("Atsushi Nemoto <anemo@mba.ocn.ne.jp>");
  188. MODULE_DESCRIPTION("Ricoh RS5C348 RTC driver");
  189. MODULE_LICENSE("GPL");
  190. MODULE_ALIAS("spi:rtc-rs5c348");