dce_virtual.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803
  1. /*
  2. * Copyright 2014 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <drm/drmP.h>
  24. #include "amdgpu.h"
  25. #include "amdgpu_pm.h"
  26. #include "amdgpu_i2c.h"
  27. #include "atom.h"
  28. #include "amdgpu_pll.h"
  29. #include "amdgpu_connectors.h"
  30. #ifdef CONFIG_DRM_AMDGPU_SI
  31. #include "dce_v6_0.h"
  32. #endif
  33. #ifdef CONFIG_DRM_AMDGPU_CIK
  34. #include "dce_v8_0.h"
  35. #endif
  36. #include "dce_v10_0.h"
  37. #include "dce_v11_0.h"
  38. #include "dce_virtual.h"
  39. #define DCE_VIRTUAL_VBLANK_PERIOD 16666666
  40. static void dce_virtual_set_display_funcs(struct amdgpu_device *adev);
  41. static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
  42. static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  43. int index);
  44. /**
  45. * dce_virtual_vblank_wait - vblank wait asic callback.
  46. *
  47. * @adev: amdgpu_device pointer
  48. * @crtc: crtc to wait for vblank on
  49. *
  50. * Wait for vblank on the requested crtc (evergreen+).
  51. */
  52. static void dce_virtual_vblank_wait(struct amdgpu_device *adev, int crtc)
  53. {
  54. return;
  55. }
  56. static u32 dce_virtual_vblank_get_counter(struct amdgpu_device *adev, int crtc)
  57. {
  58. return 0;
  59. }
  60. static void dce_virtual_page_flip(struct amdgpu_device *adev,
  61. int crtc_id, u64 crtc_base, bool async)
  62. {
  63. return;
  64. }
  65. static int dce_virtual_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
  66. u32 *vbl, u32 *position)
  67. {
  68. *vbl = 0;
  69. *position = 0;
  70. return -EINVAL;
  71. }
  72. static bool dce_virtual_hpd_sense(struct amdgpu_device *adev,
  73. enum amdgpu_hpd_id hpd)
  74. {
  75. return true;
  76. }
  77. static void dce_virtual_hpd_set_polarity(struct amdgpu_device *adev,
  78. enum amdgpu_hpd_id hpd)
  79. {
  80. return;
  81. }
  82. static u32 dce_virtual_hpd_get_gpio_reg(struct amdgpu_device *adev)
  83. {
  84. return 0;
  85. }
  86. /**
  87. * dce_virtual_bandwidth_update - program display watermarks
  88. *
  89. * @adev: amdgpu_device pointer
  90. *
  91. * Calculate and program the display watermarks and line
  92. * buffer allocation (CIK).
  93. */
  94. static void dce_virtual_bandwidth_update(struct amdgpu_device *adev)
  95. {
  96. return;
  97. }
  98. static int dce_virtual_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
  99. u16 *green, u16 *blue, uint32_t size,
  100. struct drm_modeset_acquire_ctx *ctx)
  101. {
  102. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  103. int i;
  104. /* userspace palettes are always correct as is */
  105. for (i = 0; i < size; i++) {
  106. amdgpu_crtc->lut_r[i] = red[i] >> 6;
  107. amdgpu_crtc->lut_g[i] = green[i] >> 6;
  108. amdgpu_crtc->lut_b[i] = blue[i] >> 6;
  109. }
  110. return 0;
  111. }
  112. static void dce_virtual_crtc_destroy(struct drm_crtc *crtc)
  113. {
  114. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  115. drm_crtc_cleanup(crtc);
  116. kfree(amdgpu_crtc);
  117. }
  118. static const struct drm_crtc_funcs dce_virtual_crtc_funcs = {
  119. .cursor_set2 = NULL,
  120. .cursor_move = NULL,
  121. .gamma_set = dce_virtual_crtc_gamma_set,
  122. .set_config = amdgpu_crtc_set_config,
  123. .destroy = dce_virtual_crtc_destroy,
  124. .page_flip_target = amdgpu_crtc_page_flip_target,
  125. };
  126. static void dce_virtual_crtc_dpms(struct drm_crtc *crtc, int mode)
  127. {
  128. struct drm_device *dev = crtc->dev;
  129. struct amdgpu_device *adev = dev->dev_private;
  130. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  131. unsigned type;
  132. if (amdgpu_sriov_vf(adev))
  133. return;
  134. switch (mode) {
  135. case DRM_MODE_DPMS_ON:
  136. amdgpu_crtc->enabled = true;
  137. /* Make sure VBLANK interrupts are still enabled */
  138. type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
  139. amdgpu_irq_update(adev, &adev->crtc_irq, type);
  140. drm_crtc_vblank_on(crtc);
  141. break;
  142. case DRM_MODE_DPMS_STANDBY:
  143. case DRM_MODE_DPMS_SUSPEND:
  144. case DRM_MODE_DPMS_OFF:
  145. drm_crtc_vblank_off(crtc);
  146. amdgpu_crtc->enabled = false;
  147. break;
  148. }
  149. }
  150. static void dce_virtual_crtc_prepare(struct drm_crtc *crtc)
  151. {
  152. dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  153. }
  154. static void dce_virtual_crtc_commit(struct drm_crtc *crtc)
  155. {
  156. dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
  157. }
  158. static void dce_virtual_crtc_disable(struct drm_crtc *crtc)
  159. {
  160. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  161. dce_virtual_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
  162. if (crtc->primary->fb) {
  163. int r;
  164. struct amdgpu_framebuffer *amdgpu_fb;
  165. struct amdgpu_bo *abo;
  166. amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
  167. abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
  168. r = amdgpu_bo_reserve(abo, true);
  169. if (unlikely(r))
  170. DRM_ERROR("failed to reserve abo before unpin\n");
  171. else {
  172. amdgpu_bo_unpin(abo);
  173. amdgpu_bo_unreserve(abo);
  174. }
  175. }
  176. amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  177. amdgpu_crtc->encoder = NULL;
  178. amdgpu_crtc->connector = NULL;
  179. }
  180. static int dce_virtual_crtc_mode_set(struct drm_crtc *crtc,
  181. struct drm_display_mode *mode,
  182. struct drm_display_mode *adjusted_mode,
  183. int x, int y, struct drm_framebuffer *old_fb)
  184. {
  185. struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
  186. /* update the hw version fpr dpm */
  187. amdgpu_crtc->hw_mode = *adjusted_mode;
  188. return 0;
  189. }
  190. static bool dce_virtual_crtc_mode_fixup(struct drm_crtc *crtc,
  191. const struct drm_display_mode *mode,
  192. struct drm_display_mode *adjusted_mode)
  193. {
  194. return true;
  195. }
  196. static int dce_virtual_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  197. struct drm_framebuffer *old_fb)
  198. {
  199. return 0;
  200. }
  201. static void dce_virtual_crtc_load_lut(struct drm_crtc *crtc)
  202. {
  203. return;
  204. }
  205. static int dce_virtual_crtc_set_base_atomic(struct drm_crtc *crtc,
  206. struct drm_framebuffer *fb,
  207. int x, int y, enum mode_set_atomic state)
  208. {
  209. return 0;
  210. }
  211. static const struct drm_crtc_helper_funcs dce_virtual_crtc_helper_funcs = {
  212. .dpms = dce_virtual_crtc_dpms,
  213. .mode_fixup = dce_virtual_crtc_mode_fixup,
  214. .mode_set = dce_virtual_crtc_mode_set,
  215. .mode_set_base = dce_virtual_crtc_set_base,
  216. .mode_set_base_atomic = dce_virtual_crtc_set_base_atomic,
  217. .prepare = dce_virtual_crtc_prepare,
  218. .commit = dce_virtual_crtc_commit,
  219. .load_lut = dce_virtual_crtc_load_lut,
  220. .disable = dce_virtual_crtc_disable,
  221. };
  222. static int dce_virtual_crtc_init(struct amdgpu_device *adev, int index)
  223. {
  224. struct amdgpu_crtc *amdgpu_crtc;
  225. int i;
  226. amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
  227. (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
  228. if (amdgpu_crtc == NULL)
  229. return -ENOMEM;
  230. drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_virtual_crtc_funcs);
  231. drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
  232. amdgpu_crtc->crtc_id = index;
  233. adev->mode_info.crtcs[index] = amdgpu_crtc;
  234. for (i = 0; i < 256; i++) {
  235. amdgpu_crtc->lut_r[i] = i << 2;
  236. amdgpu_crtc->lut_g[i] = i << 2;
  237. amdgpu_crtc->lut_b[i] = i << 2;
  238. }
  239. amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
  240. amdgpu_crtc->encoder = NULL;
  241. amdgpu_crtc->connector = NULL;
  242. amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
  243. drm_crtc_helper_add(&amdgpu_crtc->base, &dce_virtual_crtc_helper_funcs);
  244. return 0;
  245. }
  246. static int dce_virtual_early_init(void *handle)
  247. {
  248. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  249. dce_virtual_set_display_funcs(adev);
  250. dce_virtual_set_irq_funcs(adev);
  251. adev->mode_info.num_hpd = 1;
  252. adev->mode_info.num_dig = 1;
  253. return 0;
  254. }
  255. static struct drm_encoder *
  256. dce_virtual_encoder(struct drm_connector *connector)
  257. {
  258. int enc_id = connector->encoder_ids[0];
  259. struct drm_encoder *encoder;
  260. int i;
  261. for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
  262. if (connector->encoder_ids[i] == 0)
  263. break;
  264. encoder = drm_encoder_find(connector->dev, connector->encoder_ids[i]);
  265. if (!encoder)
  266. continue;
  267. if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
  268. return encoder;
  269. }
  270. /* pick the first one */
  271. if (enc_id)
  272. return drm_encoder_find(connector->dev, enc_id);
  273. return NULL;
  274. }
  275. static int dce_virtual_get_modes(struct drm_connector *connector)
  276. {
  277. struct drm_device *dev = connector->dev;
  278. struct drm_display_mode *mode = NULL;
  279. unsigned i;
  280. static const struct mode_size {
  281. int w;
  282. int h;
  283. } common_modes[17] = {
  284. { 640, 480},
  285. { 720, 480},
  286. { 800, 600},
  287. { 848, 480},
  288. {1024, 768},
  289. {1152, 768},
  290. {1280, 720},
  291. {1280, 800},
  292. {1280, 854},
  293. {1280, 960},
  294. {1280, 1024},
  295. {1440, 900},
  296. {1400, 1050},
  297. {1680, 1050},
  298. {1600, 1200},
  299. {1920, 1080},
  300. {1920, 1200}
  301. };
  302. for (i = 0; i < 17; i++) {
  303. mode = drm_cvt_mode(dev, common_modes[i].w, common_modes[i].h, 60, false, false, false);
  304. drm_mode_probed_add(connector, mode);
  305. }
  306. return 0;
  307. }
  308. static int dce_virtual_mode_valid(struct drm_connector *connector,
  309. struct drm_display_mode *mode)
  310. {
  311. return MODE_OK;
  312. }
  313. static int
  314. dce_virtual_dpms(struct drm_connector *connector, int mode)
  315. {
  316. return 0;
  317. }
  318. static int
  319. dce_virtual_set_property(struct drm_connector *connector,
  320. struct drm_property *property,
  321. uint64_t val)
  322. {
  323. return 0;
  324. }
  325. static void dce_virtual_destroy(struct drm_connector *connector)
  326. {
  327. drm_connector_unregister(connector);
  328. drm_connector_cleanup(connector);
  329. kfree(connector);
  330. }
  331. static void dce_virtual_force(struct drm_connector *connector)
  332. {
  333. return;
  334. }
  335. static const struct drm_connector_helper_funcs dce_virtual_connector_helper_funcs = {
  336. .get_modes = dce_virtual_get_modes,
  337. .mode_valid = dce_virtual_mode_valid,
  338. .best_encoder = dce_virtual_encoder,
  339. };
  340. static const struct drm_connector_funcs dce_virtual_connector_funcs = {
  341. .dpms = dce_virtual_dpms,
  342. .fill_modes = drm_helper_probe_single_connector_modes,
  343. .set_property = dce_virtual_set_property,
  344. .destroy = dce_virtual_destroy,
  345. .force = dce_virtual_force,
  346. };
  347. static int dce_virtual_sw_init(void *handle)
  348. {
  349. int r, i;
  350. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  351. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
  352. if (r)
  353. return r;
  354. adev->ddev->max_vblank_count = 0;
  355. adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
  356. adev->ddev->mode_config.max_width = 16384;
  357. adev->ddev->mode_config.max_height = 16384;
  358. adev->ddev->mode_config.preferred_depth = 24;
  359. adev->ddev->mode_config.prefer_shadow = 1;
  360. adev->ddev->mode_config.fb_base = adev->mc.aper_base;
  361. r = amdgpu_modeset_create_props(adev);
  362. if (r)
  363. return r;
  364. adev->ddev->mode_config.max_width = 16384;
  365. adev->ddev->mode_config.max_height = 16384;
  366. /* allocate crtcs, encoders, connectors */
  367. for (i = 0; i < adev->mode_info.num_crtc; i++) {
  368. r = dce_virtual_crtc_init(adev, i);
  369. if (r)
  370. return r;
  371. r = dce_virtual_connector_encoder_init(adev, i);
  372. if (r)
  373. return r;
  374. }
  375. drm_kms_helper_poll_init(adev->ddev);
  376. adev->mode_info.mode_config_initialized = true;
  377. return 0;
  378. }
  379. static int dce_virtual_sw_fini(void *handle)
  380. {
  381. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  382. kfree(adev->mode_info.bios_hardcoded_edid);
  383. drm_kms_helper_poll_fini(adev->ddev);
  384. drm_mode_config_cleanup(adev->ddev);
  385. adev->mode_info.mode_config_initialized = false;
  386. return 0;
  387. }
  388. static int dce_virtual_hw_init(void *handle)
  389. {
  390. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  391. switch (adev->asic_type) {
  392. #ifdef CONFIG_DRM_AMDGPU_SI
  393. case CHIP_TAHITI:
  394. case CHIP_PITCAIRN:
  395. case CHIP_VERDE:
  396. case CHIP_OLAND:
  397. dce_v6_0_disable_dce(adev);
  398. break;
  399. #endif
  400. #ifdef CONFIG_DRM_AMDGPU_CIK
  401. case CHIP_BONAIRE:
  402. case CHIP_HAWAII:
  403. case CHIP_KAVERI:
  404. case CHIP_KABINI:
  405. case CHIP_MULLINS:
  406. dce_v8_0_disable_dce(adev);
  407. break;
  408. #endif
  409. case CHIP_FIJI:
  410. case CHIP_TONGA:
  411. dce_v10_0_disable_dce(adev);
  412. break;
  413. case CHIP_CARRIZO:
  414. case CHIP_STONEY:
  415. case CHIP_POLARIS11:
  416. case CHIP_POLARIS10:
  417. dce_v11_0_disable_dce(adev);
  418. break;
  419. case CHIP_TOPAZ:
  420. #ifdef CONFIG_DRM_AMDGPU_SI
  421. case CHIP_HAINAN:
  422. #endif
  423. /* no DCE */
  424. break;
  425. default:
  426. DRM_ERROR("Virtual display unsupported ASIC type: 0x%X\n", adev->asic_type);
  427. }
  428. return 0;
  429. }
  430. static int dce_virtual_hw_fini(void *handle)
  431. {
  432. return 0;
  433. }
  434. static int dce_virtual_suspend(void *handle)
  435. {
  436. return dce_virtual_hw_fini(handle);
  437. }
  438. static int dce_virtual_resume(void *handle)
  439. {
  440. return dce_virtual_hw_init(handle);
  441. }
  442. static bool dce_virtual_is_idle(void *handle)
  443. {
  444. return true;
  445. }
  446. static int dce_virtual_wait_for_idle(void *handle)
  447. {
  448. return 0;
  449. }
  450. static int dce_virtual_soft_reset(void *handle)
  451. {
  452. return 0;
  453. }
  454. static int dce_virtual_set_clockgating_state(void *handle,
  455. enum amd_clockgating_state state)
  456. {
  457. return 0;
  458. }
  459. static int dce_virtual_set_powergating_state(void *handle,
  460. enum amd_powergating_state state)
  461. {
  462. return 0;
  463. }
  464. static const struct amd_ip_funcs dce_virtual_ip_funcs = {
  465. .name = "dce_virtual",
  466. .early_init = dce_virtual_early_init,
  467. .late_init = NULL,
  468. .sw_init = dce_virtual_sw_init,
  469. .sw_fini = dce_virtual_sw_fini,
  470. .hw_init = dce_virtual_hw_init,
  471. .hw_fini = dce_virtual_hw_fini,
  472. .suspend = dce_virtual_suspend,
  473. .resume = dce_virtual_resume,
  474. .is_idle = dce_virtual_is_idle,
  475. .wait_for_idle = dce_virtual_wait_for_idle,
  476. .soft_reset = dce_virtual_soft_reset,
  477. .set_clockgating_state = dce_virtual_set_clockgating_state,
  478. .set_powergating_state = dce_virtual_set_powergating_state,
  479. };
  480. /* these are handled by the primary encoders */
  481. static void dce_virtual_encoder_prepare(struct drm_encoder *encoder)
  482. {
  483. return;
  484. }
  485. static void dce_virtual_encoder_commit(struct drm_encoder *encoder)
  486. {
  487. return;
  488. }
  489. static void
  490. dce_virtual_encoder_mode_set(struct drm_encoder *encoder,
  491. struct drm_display_mode *mode,
  492. struct drm_display_mode *adjusted_mode)
  493. {
  494. return;
  495. }
  496. static void dce_virtual_encoder_disable(struct drm_encoder *encoder)
  497. {
  498. return;
  499. }
  500. static void
  501. dce_virtual_encoder_dpms(struct drm_encoder *encoder, int mode)
  502. {
  503. return;
  504. }
  505. static bool dce_virtual_encoder_mode_fixup(struct drm_encoder *encoder,
  506. const struct drm_display_mode *mode,
  507. struct drm_display_mode *adjusted_mode)
  508. {
  509. return true;
  510. }
  511. static const struct drm_encoder_helper_funcs dce_virtual_encoder_helper_funcs = {
  512. .dpms = dce_virtual_encoder_dpms,
  513. .mode_fixup = dce_virtual_encoder_mode_fixup,
  514. .prepare = dce_virtual_encoder_prepare,
  515. .mode_set = dce_virtual_encoder_mode_set,
  516. .commit = dce_virtual_encoder_commit,
  517. .disable = dce_virtual_encoder_disable,
  518. };
  519. static void dce_virtual_encoder_destroy(struct drm_encoder *encoder)
  520. {
  521. drm_encoder_cleanup(encoder);
  522. kfree(encoder);
  523. }
  524. static const struct drm_encoder_funcs dce_virtual_encoder_funcs = {
  525. .destroy = dce_virtual_encoder_destroy,
  526. };
  527. static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
  528. int index)
  529. {
  530. struct drm_encoder *encoder;
  531. struct drm_connector *connector;
  532. /* add a new encoder */
  533. encoder = kzalloc(sizeof(struct drm_encoder), GFP_KERNEL);
  534. if (!encoder)
  535. return -ENOMEM;
  536. encoder->possible_crtcs = 1 << index;
  537. drm_encoder_init(adev->ddev, encoder, &dce_virtual_encoder_funcs,
  538. DRM_MODE_ENCODER_VIRTUAL, NULL);
  539. drm_encoder_helper_add(encoder, &dce_virtual_encoder_helper_funcs);
  540. connector = kzalloc(sizeof(struct drm_connector), GFP_KERNEL);
  541. if (!connector) {
  542. kfree(encoder);
  543. return -ENOMEM;
  544. }
  545. /* add a new connector */
  546. drm_connector_init(adev->ddev, connector, &dce_virtual_connector_funcs,
  547. DRM_MODE_CONNECTOR_VIRTUAL);
  548. drm_connector_helper_add(connector, &dce_virtual_connector_helper_funcs);
  549. connector->display_info.subpixel_order = SubPixelHorizontalRGB;
  550. connector->interlace_allowed = false;
  551. connector->doublescan_allowed = false;
  552. drm_connector_register(connector);
  553. /* link them */
  554. drm_mode_connector_attach_encoder(connector, encoder);
  555. return 0;
  556. }
  557. static const struct amdgpu_display_funcs dce_virtual_display_funcs = {
  558. .bandwidth_update = &dce_virtual_bandwidth_update,
  559. .vblank_get_counter = &dce_virtual_vblank_get_counter,
  560. .vblank_wait = &dce_virtual_vblank_wait,
  561. .backlight_set_level = NULL,
  562. .backlight_get_level = NULL,
  563. .hpd_sense = &dce_virtual_hpd_sense,
  564. .hpd_set_polarity = &dce_virtual_hpd_set_polarity,
  565. .hpd_get_gpio_reg = &dce_virtual_hpd_get_gpio_reg,
  566. .page_flip = &dce_virtual_page_flip,
  567. .page_flip_get_scanoutpos = &dce_virtual_crtc_get_scanoutpos,
  568. .add_encoder = NULL,
  569. .add_connector = NULL,
  570. };
  571. static void dce_virtual_set_display_funcs(struct amdgpu_device *adev)
  572. {
  573. if (adev->mode_info.funcs == NULL)
  574. adev->mode_info.funcs = &dce_virtual_display_funcs;
  575. }
  576. static int dce_virtual_pageflip(struct amdgpu_device *adev,
  577. unsigned crtc_id)
  578. {
  579. unsigned long flags;
  580. struct amdgpu_crtc *amdgpu_crtc;
  581. struct amdgpu_flip_work *works;
  582. amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
  583. if (crtc_id >= adev->mode_info.num_crtc) {
  584. DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
  585. return -EINVAL;
  586. }
  587. /* IRQ could occur when in initial stage */
  588. if (amdgpu_crtc == NULL)
  589. return 0;
  590. spin_lock_irqsave(&adev->ddev->event_lock, flags);
  591. works = amdgpu_crtc->pflip_works;
  592. if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
  593. DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
  594. "AMDGPU_FLIP_SUBMITTED(%d)\n",
  595. amdgpu_crtc->pflip_status,
  596. AMDGPU_FLIP_SUBMITTED);
  597. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  598. return 0;
  599. }
  600. /* page flip completed. clean up */
  601. amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
  602. amdgpu_crtc->pflip_works = NULL;
  603. /* wakeup usersapce */
  604. if (works->event)
  605. drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
  606. spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
  607. drm_crtc_vblank_put(&amdgpu_crtc->base);
  608. schedule_work(&works->unpin_work);
  609. return 0;
  610. }
  611. static enum hrtimer_restart dce_virtual_vblank_timer_handle(struct hrtimer *vblank_timer)
  612. {
  613. struct amdgpu_crtc *amdgpu_crtc = container_of(vblank_timer,
  614. struct amdgpu_crtc, vblank_timer);
  615. struct drm_device *ddev = amdgpu_crtc->base.dev;
  616. struct amdgpu_device *adev = ddev->dev_private;
  617. drm_handle_vblank(ddev, amdgpu_crtc->crtc_id);
  618. dce_virtual_pageflip(adev, amdgpu_crtc->crtc_id);
  619. hrtimer_start(vblank_timer, DCE_VIRTUAL_VBLANK_PERIOD,
  620. HRTIMER_MODE_REL);
  621. return HRTIMER_NORESTART;
  622. }
  623. static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
  624. int crtc,
  625. enum amdgpu_interrupt_state state)
  626. {
  627. if (crtc >= adev->mode_info.num_crtc) {
  628. DRM_DEBUG("invalid crtc %d\n", crtc);
  629. return;
  630. }
  631. if (state && !adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
  632. DRM_DEBUG("Enable software vsync timer\n");
  633. hrtimer_init(&adev->mode_info.crtcs[crtc]->vblank_timer,
  634. CLOCK_MONOTONIC, HRTIMER_MODE_REL);
  635. hrtimer_set_expires(&adev->mode_info.crtcs[crtc]->vblank_timer,
  636. DCE_VIRTUAL_VBLANK_PERIOD);
  637. adev->mode_info.crtcs[crtc]->vblank_timer.function =
  638. dce_virtual_vblank_timer_handle;
  639. hrtimer_start(&adev->mode_info.crtcs[crtc]->vblank_timer,
  640. DCE_VIRTUAL_VBLANK_PERIOD, HRTIMER_MODE_REL);
  641. } else if (!state && adev->mode_info.crtcs[crtc]->vsync_timer_enabled) {
  642. DRM_DEBUG("Disable software vsync timer\n");
  643. hrtimer_cancel(&adev->mode_info.crtcs[crtc]->vblank_timer);
  644. }
  645. adev->mode_info.crtcs[crtc]->vsync_timer_enabled = state;
  646. DRM_DEBUG("[FM]set crtc %d vblank interrupt state %d\n", crtc, state);
  647. }
  648. static int dce_virtual_set_crtc_irq_state(struct amdgpu_device *adev,
  649. struct amdgpu_irq_src *source,
  650. unsigned type,
  651. enum amdgpu_interrupt_state state)
  652. {
  653. if (type > AMDGPU_CRTC_IRQ_VBLANK6)
  654. return -EINVAL;
  655. dce_virtual_set_crtc_vblank_interrupt_state(adev, type, state);
  656. return 0;
  657. }
  658. static const struct amdgpu_irq_src_funcs dce_virtual_crtc_irq_funcs = {
  659. .set = dce_virtual_set_crtc_irq_state,
  660. .process = NULL,
  661. };
  662. static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev)
  663. {
  664. adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
  665. adev->crtc_irq.funcs = &dce_virtual_crtc_irq_funcs;
  666. }
  667. const struct amdgpu_ip_block_version dce_virtual_ip_block =
  668. {
  669. .type = AMD_IP_BLOCK_TYPE_DCE,
  670. .major = 1,
  671. .minor = 0,
  672. .rev = 0,
  673. .funcs = &dce_virtual_ip_funcs,
  674. };