gfx_v9_0.c 137 KB

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  1. /*
  2. * Copyright 2016 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #include <linux/firmware.h>
  24. #include <drm/drmP.h>
  25. #include "amdgpu.h"
  26. #include "amdgpu_gfx.h"
  27. #include "soc15.h"
  28. #include "soc15d.h"
  29. #include "vega10/soc15ip.h"
  30. #include "vega10/GC/gc_9_0_offset.h"
  31. #include "vega10/GC/gc_9_0_sh_mask.h"
  32. #include "vega10/vega10_enum.h"
  33. #include "vega10/HDP/hdp_4_0_offset.h"
  34. #include "soc15_common.h"
  35. #include "clearstate_gfx9.h"
  36. #include "v9_structs.h"
  37. #define GFX9_NUM_GFX_RINGS 1
  38. #define GFX9_MEC_HPD_SIZE 2048
  39. #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  40. #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  41. #define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
  42. #define mmPWR_MISC_CNTL_STATUS 0x0183
  43. #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 0
  44. #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
  45. #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
  46. #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
  47. #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
  48. MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  49. MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  50. MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  51. MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  52. MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  53. MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  54. MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  55. MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  56. MODULE_FIRMWARE("amdgpu/raven_me.bin");
  57. MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  58. MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  59. MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  60. static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
  61. {
  62. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
  63. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0)},
  64. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
  65. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1)},
  66. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
  67. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2)},
  68. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
  69. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3)},
  70. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
  71. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4)},
  72. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
  73. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5)},
  74. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
  75. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6)},
  76. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
  77. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7)},
  78. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
  79. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8)},
  80. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
  81. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9)},
  82. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
  83. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID10)},
  84. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID11_SIZE),
  85. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID11), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID11)},
  86. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID12_SIZE),
  87. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID12), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID12)},
  88. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID13_SIZE),
  89. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID13), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID13)},
  90. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID14_SIZE),
  91. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID14), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID14)},
  92. {SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_BASE), SOC15_REG_OFFSET(GC, 0, mmGDS_VMID15_SIZE),
  93. SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID15), SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID15)}
  94. };
  95. static const u32 golden_settings_gc_9_0[] =
  96. {
  97. SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
  98. SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
  99. SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
  100. SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
  101. SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
  102. SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
  103. SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
  104. SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
  105. SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
  106. SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
  107. SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
  108. SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
  109. SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
  110. SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
  111. SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_1), 0x0000000f, 0x01000107,
  112. SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
  113. SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x4a2c0e68,
  114. SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0xb5d3f197,
  115. SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
  116. SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000003ff,
  117. SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
  118. };
  119. static const u32 golden_settings_gc_9_0_vg10[] =
  120. {
  121. SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0x0000f000, 0x00012107,
  122. SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
  123. SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x2a114042,
  124. SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x2a114042,
  125. SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0x00008000, 0x00048000,
  126. SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
  127. SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x00001800, 0x00000800
  128. };
  129. static const u32 golden_settings_gc_9_1[] =
  130. {
  131. SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL), 0xfffdf3cf, 0x00014104,
  132. SOC15_REG_OFFSET(GC, 0, mmCPC_UTCL1_CNTL), 0x08000000, 0x08000080,
  133. SOC15_REG_OFFSET(GC, 0, mmCPF_UTCL1_CNTL), 0x08000000, 0x08000080,
  134. SOC15_REG_OFFSET(GC, 0, mmCPG_UTCL1_CNTL), 0x08000000, 0x08000080,
  135. SOC15_REG_OFFSET(GC, 0, mmDB_DEBUG2), 0xf00fffff, 0x00000420,
  136. SOC15_REG_OFFSET(GC, 0, mmGB_GPU_ID), 0x0000000f, 0x00000000,
  137. SOC15_REG_OFFSET(GC, 0, mmIA_UTCL1_CNTL), 0x08000000, 0x08000080,
  138. SOC15_REG_OFFSET(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3), 0x00000003, 0x82400024,
  139. SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE), 0x3fffffff, 0x00000001,
  140. SOC15_REG_OFFSET(GC, 0, mmPA_SC_LINE_STIPPLE_STATE), 0x0000ff0f, 0x00000000,
  141. SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_0), 0x08000000, 0x08000080,
  142. SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_1), 0x08000000, 0x08000080,
  143. SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_UTCL1_CNTL_2), 0x08000000, 0x08000080,
  144. SOC15_REG_OFFSET(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL), 0x08000000, 0x08000080,
  145. SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_UTCL1_CNTL), 0x08000000, 0x08000080,
  146. SOC15_REG_OFFSET(GC, 0, mmTA_CNTL_AUX), 0xfffffeef, 0x010b0000,
  147. SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_HI), 0xffffffff, 0x00000000,
  148. SOC15_REG_OFFSET(GC, 0, mmTCP_CHAN_STEER_LO), 0xffffffff, 0x00003120,
  149. SOC15_REG_OFFSET(GC, 0, mmVGT_CACHE_INVALIDATION), 0x3fff3af3, 0x19200000,
  150. SOC15_REG_OFFSET(GC, 0, mmVGT_GS_MAX_WAVE_ID), 0x00000fff, 0x000000ff,
  151. SOC15_REG_OFFSET(GC, 0, mmWD_UTCL1_CNTL), 0x08000000, 0x08000080
  152. };
  153. static const u32 golden_settings_gc_9_1_rv1[] =
  154. {
  155. SOC15_REG_OFFSET(GC, 0, mmCB_HW_CONTROL_3), 0x30000000, 0x10000000,
  156. SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG), 0xffff77ff, 0x24000042,
  157. SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG_READ), 0xffff77ff, 0x24000042,
  158. SOC15_REG_OFFSET(GC, 0, mmPA_SC_ENHANCE_1), 0xffffffff, 0x04048000,
  159. SOC15_REG_OFFSET(GC, 0, mmPA_SC_MODE_CNTL_1), 0x06000000, 0x06000000,
  160. SOC15_REG_OFFSET(GC, 0, mmRMI_UTCL1_CNTL2), 0x00030000, 0x00020000,
  161. SOC15_REG_OFFSET(GC, 0, mmTD_CNTL), 0x01bd9f33, 0x00000800
  162. };
  163. #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
  164. #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
  165. static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
  166. static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
  167. static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
  168. static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
  169. static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
  170. struct amdgpu_cu_info *cu_info);
  171. static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
  172. static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
  173. static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
  174. static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
  175. {
  176. switch (adev->asic_type) {
  177. case CHIP_VEGA10:
  178. amdgpu_program_register_sequence(adev,
  179. golden_settings_gc_9_0,
  180. (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
  181. amdgpu_program_register_sequence(adev,
  182. golden_settings_gc_9_0_vg10,
  183. (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
  184. break;
  185. case CHIP_RAVEN:
  186. amdgpu_program_register_sequence(adev,
  187. golden_settings_gc_9_1,
  188. (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
  189. amdgpu_program_register_sequence(adev,
  190. golden_settings_gc_9_1_rv1,
  191. (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
  192. break;
  193. default:
  194. break;
  195. }
  196. }
  197. static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
  198. {
  199. adev->gfx.scratch.num_reg = 8;
  200. adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
  201. adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
  202. }
  203. static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
  204. bool wc, uint32_t reg, uint32_t val)
  205. {
  206. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  207. amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
  208. WRITE_DATA_DST_SEL(0) |
  209. (wc ? WR_CONFIRM : 0));
  210. amdgpu_ring_write(ring, reg);
  211. amdgpu_ring_write(ring, 0);
  212. amdgpu_ring_write(ring, val);
  213. }
  214. static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
  215. int mem_space, int opt, uint32_t addr0,
  216. uint32_t addr1, uint32_t ref, uint32_t mask,
  217. uint32_t inv)
  218. {
  219. amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
  220. amdgpu_ring_write(ring,
  221. /* memory (1) or register (0) */
  222. (WAIT_REG_MEM_MEM_SPACE(mem_space) |
  223. WAIT_REG_MEM_OPERATION(opt) | /* wait */
  224. WAIT_REG_MEM_FUNCTION(3) | /* equal */
  225. WAIT_REG_MEM_ENGINE(eng_sel)));
  226. if (mem_space)
  227. BUG_ON(addr0 & 0x3); /* Dword align */
  228. amdgpu_ring_write(ring, addr0);
  229. amdgpu_ring_write(ring, addr1);
  230. amdgpu_ring_write(ring, ref);
  231. amdgpu_ring_write(ring, mask);
  232. amdgpu_ring_write(ring, inv); /* poll interval */
  233. }
  234. static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
  235. {
  236. struct amdgpu_device *adev = ring->adev;
  237. uint32_t scratch;
  238. uint32_t tmp = 0;
  239. unsigned i;
  240. int r;
  241. r = amdgpu_gfx_scratch_get(adev, &scratch);
  242. if (r) {
  243. DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
  244. return r;
  245. }
  246. WREG32(scratch, 0xCAFEDEAD);
  247. r = amdgpu_ring_alloc(ring, 3);
  248. if (r) {
  249. DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
  250. ring->idx, r);
  251. amdgpu_gfx_scratch_free(adev, scratch);
  252. return r;
  253. }
  254. amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
  255. amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
  256. amdgpu_ring_write(ring, 0xDEADBEEF);
  257. amdgpu_ring_commit(ring);
  258. for (i = 0; i < adev->usec_timeout; i++) {
  259. tmp = RREG32(scratch);
  260. if (tmp == 0xDEADBEEF)
  261. break;
  262. DRM_UDELAY(1);
  263. }
  264. if (i < adev->usec_timeout) {
  265. DRM_INFO("ring test on %d succeeded in %d usecs\n",
  266. ring->idx, i);
  267. } else {
  268. DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
  269. ring->idx, scratch, tmp);
  270. r = -EINVAL;
  271. }
  272. amdgpu_gfx_scratch_free(adev, scratch);
  273. return r;
  274. }
  275. static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
  276. {
  277. struct amdgpu_device *adev = ring->adev;
  278. struct amdgpu_ib ib;
  279. struct dma_fence *f = NULL;
  280. uint32_t scratch;
  281. uint32_t tmp = 0;
  282. long r;
  283. r = amdgpu_gfx_scratch_get(adev, &scratch);
  284. if (r) {
  285. DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
  286. return r;
  287. }
  288. WREG32(scratch, 0xCAFEDEAD);
  289. memset(&ib, 0, sizeof(ib));
  290. r = amdgpu_ib_get(adev, NULL, 256, &ib);
  291. if (r) {
  292. DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
  293. goto err1;
  294. }
  295. ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
  296. ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
  297. ib.ptr[2] = 0xDEADBEEF;
  298. ib.length_dw = 3;
  299. r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
  300. if (r)
  301. goto err2;
  302. r = dma_fence_wait_timeout(f, false, timeout);
  303. if (r == 0) {
  304. DRM_ERROR("amdgpu: IB test timed out.\n");
  305. r = -ETIMEDOUT;
  306. goto err2;
  307. } else if (r < 0) {
  308. DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
  309. goto err2;
  310. }
  311. tmp = RREG32(scratch);
  312. if (tmp == 0xDEADBEEF) {
  313. DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
  314. r = 0;
  315. } else {
  316. DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
  317. scratch, tmp);
  318. r = -EINVAL;
  319. }
  320. err2:
  321. amdgpu_ib_free(adev, &ib, NULL);
  322. dma_fence_put(f);
  323. err1:
  324. amdgpu_gfx_scratch_free(adev, scratch);
  325. return r;
  326. }
  327. static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
  328. {
  329. const char *chip_name;
  330. char fw_name[30];
  331. int err;
  332. struct amdgpu_firmware_info *info = NULL;
  333. const struct common_firmware_header *header = NULL;
  334. const struct gfx_firmware_header_v1_0 *cp_hdr;
  335. const struct rlc_firmware_header_v2_0 *rlc_hdr;
  336. unsigned int *tmp = NULL;
  337. unsigned int i = 0;
  338. DRM_DEBUG("\n");
  339. switch (adev->asic_type) {
  340. case CHIP_VEGA10:
  341. chip_name = "vega10";
  342. break;
  343. case CHIP_RAVEN:
  344. chip_name = "raven";
  345. break;
  346. default:
  347. BUG();
  348. }
  349. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
  350. err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
  351. if (err)
  352. goto out;
  353. err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
  354. if (err)
  355. goto out;
  356. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
  357. adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  358. adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  359. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
  360. err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
  361. if (err)
  362. goto out;
  363. err = amdgpu_ucode_validate(adev->gfx.me_fw);
  364. if (err)
  365. goto out;
  366. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
  367. adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  368. adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  369. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
  370. err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
  371. if (err)
  372. goto out;
  373. err = amdgpu_ucode_validate(adev->gfx.ce_fw);
  374. if (err)
  375. goto out;
  376. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
  377. adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  378. adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  379. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
  380. err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
  381. if (err)
  382. goto out;
  383. err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
  384. rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
  385. adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
  386. adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
  387. adev->gfx.rlc.save_and_restore_offset =
  388. le32_to_cpu(rlc_hdr->save_and_restore_offset);
  389. adev->gfx.rlc.clear_state_descriptor_offset =
  390. le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
  391. adev->gfx.rlc.avail_scratch_ram_locations =
  392. le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
  393. adev->gfx.rlc.reg_restore_list_size =
  394. le32_to_cpu(rlc_hdr->reg_restore_list_size);
  395. adev->gfx.rlc.reg_list_format_start =
  396. le32_to_cpu(rlc_hdr->reg_list_format_start);
  397. adev->gfx.rlc.reg_list_format_separate_start =
  398. le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
  399. adev->gfx.rlc.starting_offsets_start =
  400. le32_to_cpu(rlc_hdr->starting_offsets_start);
  401. adev->gfx.rlc.reg_list_format_size_bytes =
  402. le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
  403. adev->gfx.rlc.reg_list_size_bytes =
  404. le32_to_cpu(rlc_hdr->reg_list_size_bytes);
  405. adev->gfx.rlc.register_list_format =
  406. kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
  407. adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
  408. if (!adev->gfx.rlc.register_list_format) {
  409. err = -ENOMEM;
  410. goto out;
  411. }
  412. tmp = (unsigned int *)((uintptr_t)rlc_hdr +
  413. le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
  414. for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
  415. adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
  416. adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
  417. tmp = (unsigned int *)((uintptr_t)rlc_hdr +
  418. le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
  419. for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
  420. adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
  421. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
  422. err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
  423. if (err)
  424. goto out;
  425. err = amdgpu_ucode_validate(adev->gfx.mec_fw);
  426. if (err)
  427. goto out;
  428. cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
  429. adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
  430. adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
  431. snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
  432. err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
  433. if (!err) {
  434. err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
  435. if (err)
  436. goto out;
  437. cp_hdr = (const struct gfx_firmware_header_v1_0 *)
  438. adev->gfx.mec2_fw->data;
  439. adev->gfx.mec2_fw_version =
  440. le32_to_cpu(cp_hdr->header.ucode_version);
  441. adev->gfx.mec2_feature_version =
  442. le32_to_cpu(cp_hdr->ucode_feature_version);
  443. } else {
  444. err = 0;
  445. adev->gfx.mec2_fw = NULL;
  446. }
  447. if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
  448. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
  449. info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
  450. info->fw = adev->gfx.pfp_fw;
  451. header = (const struct common_firmware_header *)info->fw->data;
  452. adev->firmware.fw_size +=
  453. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  454. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
  455. info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
  456. info->fw = adev->gfx.me_fw;
  457. header = (const struct common_firmware_header *)info->fw->data;
  458. adev->firmware.fw_size +=
  459. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  460. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
  461. info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
  462. info->fw = adev->gfx.ce_fw;
  463. header = (const struct common_firmware_header *)info->fw->data;
  464. adev->firmware.fw_size +=
  465. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  466. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
  467. info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
  468. info->fw = adev->gfx.rlc_fw;
  469. header = (const struct common_firmware_header *)info->fw->data;
  470. adev->firmware.fw_size +=
  471. ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
  472. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
  473. info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
  474. info->fw = adev->gfx.mec_fw;
  475. header = (const struct common_firmware_header *)info->fw->data;
  476. cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
  477. adev->firmware.fw_size +=
  478. ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
  479. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
  480. info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
  481. info->fw = adev->gfx.mec_fw;
  482. adev->firmware.fw_size +=
  483. ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
  484. if (adev->gfx.mec2_fw) {
  485. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
  486. info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
  487. info->fw = adev->gfx.mec2_fw;
  488. header = (const struct common_firmware_header *)info->fw->data;
  489. cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
  490. adev->firmware.fw_size +=
  491. ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
  492. info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
  493. info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
  494. info->fw = adev->gfx.mec2_fw;
  495. adev->firmware.fw_size +=
  496. ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
  497. }
  498. }
  499. out:
  500. if (err) {
  501. dev_err(adev->dev,
  502. "gfx9: Failed to load firmware \"%s\"\n",
  503. fw_name);
  504. release_firmware(adev->gfx.pfp_fw);
  505. adev->gfx.pfp_fw = NULL;
  506. release_firmware(adev->gfx.me_fw);
  507. adev->gfx.me_fw = NULL;
  508. release_firmware(adev->gfx.ce_fw);
  509. adev->gfx.ce_fw = NULL;
  510. release_firmware(adev->gfx.rlc_fw);
  511. adev->gfx.rlc_fw = NULL;
  512. release_firmware(adev->gfx.mec_fw);
  513. adev->gfx.mec_fw = NULL;
  514. release_firmware(adev->gfx.mec2_fw);
  515. adev->gfx.mec2_fw = NULL;
  516. }
  517. return err;
  518. }
  519. static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
  520. {
  521. u32 count = 0;
  522. const struct cs_section_def *sect = NULL;
  523. const struct cs_extent_def *ext = NULL;
  524. /* begin clear state */
  525. count += 2;
  526. /* context control state */
  527. count += 3;
  528. for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
  529. for (ext = sect->section; ext->extent != NULL; ++ext) {
  530. if (sect->id == SECT_CONTEXT)
  531. count += 2 + ext->reg_count;
  532. else
  533. return 0;
  534. }
  535. }
  536. /* end clear state */
  537. count += 2;
  538. /* clear state */
  539. count += 2;
  540. return count;
  541. }
  542. static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
  543. volatile u32 *buffer)
  544. {
  545. u32 count = 0, i;
  546. const struct cs_section_def *sect = NULL;
  547. const struct cs_extent_def *ext = NULL;
  548. if (adev->gfx.rlc.cs_data == NULL)
  549. return;
  550. if (buffer == NULL)
  551. return;
  552. buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  553. buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  554. buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
  555. buffer[count++] = cpu_to_le32(0x80000000);
  556. buffer[count++] = cpu_to_le32(0x80000000);
  557. for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
  558. for (ext = sect->section; ext->extent != NULL; ++ext) {
  559. if (sect->id == SECT_CONTEXT) {
  560. buffer[count++] =
  561. cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
  562. buffer[count++] = cpu_to_le32(ext->reg_index -
  563. PACKET3_SET_CONTEXT_REG_START);
  564. for (i = 0; i < ext->reg_count; i++)
  565. buffer[count++] = cpu_to_le32(ext->extent[i]);
  566. } else {
  567. return;
  568. }
  569. }
  570. }
  571. buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  572. buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
  573. buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
  574. buffer[count++] = cpu_to_le32(0);
  575. }
  576. static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
  577. {
  578. uint32_t data;
  579. /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
  580. WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
  581. WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
  582. WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
  583. WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
  584. /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
  585. WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
  586. /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
  587. WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
  588. mutex_lock(&adev->grbm_idx_mutex);
  589. /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
  590. gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  591. WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
  592. /* set mmRLC_LB_PARAMS = 0x003F_1006 */
  593. data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
  594. data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
  595. data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
  596. WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
  597. /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
  598. data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
  599. data &= 0x0000FFFF;
  600. data |= 0x00C00000;
  601. WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
  602. /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
  603. WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
  604. /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
  605. * but used for RLC_LB_CNTL configuration */
  606. data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
  607. data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
  608. data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
  609. WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
  610. mutex_unlock(&adev->grbm_idx_mutex);
  611. }
  612. static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
  613. {
  614. WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
  615. }
  616. static void rv_init_cp_jump_table(struct amdgpu_device *adev)
  617. {
  618. const __le32 *fw_data;
  619. volatile u32 *dst_ptr;
  620. int me, i, max_me = 5;
  621. u32 bo_offset = 0;
  622. u32 table_offset, table_size;
  623. /* write the cp table buffer */
  624. dst_ptr = adev->gfx.rlc.cp_table_ptr;
  625. for (me = 0; me < max_me; me++) {
  626. if (me == 0) {
  627. const struct gfx_firmware_header_v1_0 *hdr =
  628. (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
  629. fw_data = (const __le32 *)
  630. (adev->gfx.ce_fw->data +
  631. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  632. table_offset = le32_to_cpu(hdr->jt_offset);
  633. table_size = le32_to_cpu(hdr->jt_size);
  634. } else if (me == 1) {
  635. const struct gfx_firmware_header_v1_0 *hdr =
  636. (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
  637. fw_data = (const __le32 *)
  638. (adev->gfx.pfp_fw->data +
  639. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  640. table_offset = le32_to_cpu(hdr->jt_offset);
  641. table_size = le32_to_cpu(hdr->jt_size);
  642. } else if (me == 2) {
  643. const struct gfx_firmware_header_v1_0 *hdr =
  644. (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
  645. fw_data = (const __le32 *)
  646. (adev->gfx.me_fw->data +
  647. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  648. table_offset = le32_to_cpu(hdr->jt_offset);
  649. table_size = le32_to_cpu(hdr->jt_size);
  650. } else if (me == 3) {
  651. const struct gfx_firmware_header_v1_0 *hdr =
  652. (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
  653. fw_data = (const __le32 *)
  654. (adev->gfx.mec_fw->data +
  655. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  656. table_offset = le32_to_cpu(hdr->jt_offset);
  657. table_size = le32_to_cpu(hdr->jt_size);
  658. } else if (me == 4) {
  659. const struct gfx_firmware_header_v1_0 *hdr =
  660. (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
  661. fw_data = (const __le32 *)
  662. (adev->gfx.mec2_fw->data +
  663. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  664. table_offset = le32_to_cpu(hdr->jt_offset);
  665. table_size = le32_to_cpu(hdr->jt_size);
  666. }
  667. for (i = 0; i < table_size; i ++) {
  668. dst_ptr[bo_offset + i] =
  669. cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
  670. }
  671. bo_offset += table_size;
  672. }
  673. }
  674. static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
  675. {
  676. /* clear state block */
  677. amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
  678. &adev->gfx.rlc.clear_state_gpu_addr,
  679. (void **)&adev->gfx.rlc.cs_ptr);
  680. /* jump table block */
  681. amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
  682. &adev->gfx.rlc.cp_table_gpu_addr,
  683. (void **)&adev->gfx.rlc.cp_table_ptr);
  684. }
  685. static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
  686. {
  687. volatile u32 *dst_ptr;
  688. u32 dws;
  689. const struct cs_section_def *cs_data;
  690. int r;
  691. adev->gfx.rlc.cs_data = gfx9_cs_data;
  692. cs_data = adev->gfx.rlc.cs_data;
  693. if (cs_data) {
  694. /* clear state block */
  695. adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
  696. if (adev->gfx.rlc.clear_state_obj == NULL) {
  697. r = amdgpu_bo_create_kernel(adev, dws * 4, PAGE_SIZE,
  698. AMDGPU_GEM_DOMAIN_VRAM,
  699. &adev->gfx.rlc.clear_state_obj,
  700. &adev->gfx.rlc.clear_state_gpu_addr,
  701. (void **)&adev->gfx.rlc.cs_ptr);
  702. if (r) {
  703. dev_err(adev->dev,
  704. "(%d) failed to create rlc csb bo\n", r);
  705. gfx_v9_0_rlc_fini(adev);
  706. return r;
  707. }
  708. }
  709. /* set up the cs buffer */
  710. dst_ptr = adev->gfx.rlc.cs_ptr;
  711. gfx_v9_0_get_csb_buffer(adev, dst_ptr);
  712. amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
  713. amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
  714. }
  715. if (adev->asic_type == CHIP_RAVEN) {
  716. /* TODO: double check the cp_table_size for RV */
  717. adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
  718. if (adev->gfx.rlc.cp_table_obj == NULL) {
  719. r = amdgpu_bo_create_kernel(adev, adev->gfx.rlc.cp_table_size,
  720. PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
  721. &adev->gfx.rlc.cp_table_obj,
  722. &adev->gfx.rlc.cp_table_gpu_addr,
  723. (void **)&adev->gfx.rlc.cp_table_ptr);
  724. if (r) {
  725. dev_err(adev->dev,
  726. "(%d) failed to create cp table bo\n", r);
  727. gfx_v9_0_rlc_fini(adev);
  728. return r;
  729. }
  730. }
  731. rv_init_cp_jump_table(adev);
  732. amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
  733. amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
  734. gfx_v9_0_init_lbpw(adev);
  735. }
  736. return 0;
  737. }
  738. static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
  739. {
  740. int r;
  741. if (adev->gfx.mec.hpd_eop_obj) {
  742. r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, true);
  743. if (unlikely(r != 0))
  744. dev_warn(adev->dev, "(%d) reserve HPD EOP bo failed\n", r);
  745. amdgpu_bo_unpin(adev->gfx.mec.hpd_eop_obj);
  746. amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
  747. amdgpu_bo_unref(&adev->gfx.mec.hpd_eop_obj);
  748. adev->gfx.mec.hpd_eop_obj = NULL;
  749. }
  750. if (adev->gfx.mec.mec_fw_obj) {
  751. r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, true);
  752. if (unlikely(r != 0))
  753. dev_warn(adev->dev, "(%d) reserve mec firmware bo failed\n", r);
  754. amdgpu_bo_unpin(adev->gfx.mec.mec_fw_obj);
  755. amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
  756. amdgpu_bo_unref(&adev->gfx.mec.mec_fw_obj);
  757. adev->gfx.mec.mec_fw_obj = NULL;
  758. }
  759. }
  760. static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
  761. {
  762. int r;
  763. u32 *hpd;
  764. const __le32 *fw_data;
  765. unsigned fw_size;
  766. u32 *fw;
  767. size_t mec_hpd_size;
  768. const struct gfx_firmware_header_v1_0 *mec_hdr;
  769. bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
  770. /* take ownership of the relevant compute queues */
  771. amdgpu_gfx_compute_queue_acquire(adev);
  772. mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
  773. if (adev->gfx.mec.hpd_eop_obj == NULL) {
  774. r = amdgpu_bo_create(adev,
  775. mec_hpd_size,
  776. PAGE_SIZE, true,
  777. AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
  778. &adev->gfx.mec.hpd_eop_obj);
  779. if (r) {
  780. dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
  781. return r;
  782. }
  783. }
  784. r = amdgpu_bo_reserve(adev->gfx.mec.hpd_eop_obj, false);
  785. if (unlikely(r != 0)) {
  786. gfx_v9_0_mec_fini(adev);
  787. return r;
  788. }
  789. r = amdgpu_bo_pin(adev->gfx.mec.hpd_eop_obj, AMDGPU_GEM_DOMAIN_GTT,
  790. &adev->gfx.mec.hpd_eop_gpu_addr);
  791. if (r) {
  792. dev_warn(adev->dev, "(%d) pin HDP EOP bo failed\n", r);
  793. gfx_v9_0_mec_fini(adev);
  794. return r;
  795. }
  796. r = amdgpu_bo_kmap(adev->gfx.mec.hpd_eop_obj, (void **)&hpd);
  797. if (r) {
  798. dev_warn(adev->dev, "(%d) map HDP EOP bo failed\n", r);
  799. gfx_v9_0_mec_fini(adev);
  800. return r;
  801. }
  802. memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
  803. amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
  804. amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
  805. mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
  806. fw_data = (const __le32 *)
  807. (adev->gfx.mec_fw->data +
  808. le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
  809. fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
  810. if (adev->gfx.mec.mec_fw_obj == NULL) {
  811. r = amdgpu_bo_create(adev,
  812. mec_hdr->header.ucode_size_bytes,
  813. PAGE_SIZE, true,
  814. AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
  815. &adev->gfx.mec.mec_fw_obj);
  816. if (r) {
  817. dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
  818. return r;
  819. }
  820. }
  821. r = amdgpu_bo_reserve(adev->gfx.mec.mec_fw_obj, false);
  822. if (unlikely(r != 0)) {
  823. gfx_v9_0_mec_fini(adev);
  824. return r;
  825. }
  826. r = amdgpu_bo_pin(adev->gfx.mec.mec_fw_obj, AMDGPU_GEM_DOMAIN_GTT,
  827. &adev->gfx.mec.mec_fw_gpu_addr);
  828. if (r) {
  829. dev_warn(adev->dev, "(%d) pin mec firmware bo failed\n", r);
  830. gfx_v9_0_mec_fini(adev);
  831. return r;
  832. }
  833. r = amdgpu_bo_kmap(adev->gfx.mec.mec_fw_obj, (void **)&fw);
  834. if (r) {
  835. dev_warn(adev->dev, "(%d) map firmware bo failed\n", r);
  836. gfx_v9_0_mec_fini(adev);
  837. return r;
  838. }
  839. memcpy(fw, fw_data, fw_size);
  840. amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
  841. amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
  842. return 0;
  843. }
  844. static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
  845. {
  846. WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
  847. (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
  848. (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
  849. (address << SQ_IND_INDEX__INDEX__SHIFT) |
  850. (SQ_IND_INDEX__FORCE_READ_MASK));
  851. return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
  852. }
  853. static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
  854. uint32_t wave, uint32_t thread,
  855. uint32_t regno, uint32_t num, uint32_t *out)
  856. {
  857. WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
  858. (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
  859. (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
  860. (regno << SQ_IND_INDEX__INDEX__SHIFT) |
  861. (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
  862. (SQ_IND_INDEX__FORCE_READ_MASK) |
  863. (SQ_IND_INDEX__AUTO_INCR_MASK));
  864. while (num--)
  865. *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
  866. }
  867. static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
  868. {
  869. /* type 1 wave data */
  870. dst[(*no_fields)++] = 1;
  871. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
  872. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
  873. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
  874. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
  875. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
  876. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
  877. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
  878. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
  879. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
  880. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
  881. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
  882. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
  883. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
  884. dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
  885. }
  886. static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
  887. uint32_t wave, uint32_t start,
  888. uint32_t size, uint32_t *dst)
  889. {
  890. wave_read_regs(
  891. adev, simd, wave, 0,
  892. start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
  893. }
  894. static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
  895. .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
  896. .select_se_sh = &gfx_v9_0_select_se_sh,
  897. .read_wave_data = &gfx_v9_0_read_wave_data,
  898. .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
  899. };
  900. static void gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
  901. {
  902. u32 gb_addr_config;
  903. adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
  904. switch (adev->asic_type) {
  905. case CHIP_VEGA10:
  906. adev->gfx.config.max_hw_contexts = 8;
  907. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  908. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  909. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  910. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
  911. gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
  912. break;
  913. case CHIP_RAVEN:
  914. adev->gfx.config.max_hw_contexts = 8;
  915. adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
  916. adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
  917. adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
  918. adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
  919. gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
  920. break;
  921. default:
  922. BUG();
  923. break;
  924. }
  925. adev->gfx.config.gb_addr_config = gb_addr_config;
  926. adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
  927. REG_GET_FIELD(
  928. adev->gfx.config.gb_addr_config,
  929. GB_ADDR_CONFIG,
  930. NUM_PIPES);
  931. adev->gfx.config.max_tile_pipes =
  932. adev->gfx.config.gb_addr_config_fields.num_pipes;
  933. adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
  934. REG_GET_FIELD(
  935. adev->gfx.config.gb_addr_config,
  936. GB_ADDR_CONFIG,
  937. NUM_BANKS);
  938. adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
  939. REG_GET_FIELD(
  940. adev->gfx.config.gb_addr_config,
  941. GB_ADDR_CONFIG,
  942. MAX_COMPRESSED_FRAGS);
  943. adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
  944. REG_GET_FIELD(
  945. adev->gfx.config.gb_addr_config,
  946. GB_ADDR_CONFIG,
  947. NUM_RB_PER_SE);
  948. adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
  949. REG_GET_FIELD(
  950. adev->gfx.config.gb_addr_config,
  951. GB_ADDR_CONFIG,
  952. NUM_SHADER_ENGINES);
  953. adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
  954. REG_GET_FIELD(
  955. adev->gfx.config.gb_addr_config,
  956. GB_ADDR_CONFIG,
  957. PIPE_INTERLEAVE_SIZE));
  958. }
  959. static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
  960. struct amdgpu_ngg_buf *ngg_buf,
  961. int size_se,
  962. int default_size_se)
  963. {
  964. int r;
  965. if (size_se < 0) {
  966. dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
  967. return -EINVAL;
  968. }
  969. size_se = size_se ? size_se : default_size_se;
  970. ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
  971. r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
  972. PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
  973. &ngg_buf->bo,
  974. &ngg_buf->gpu_addr,
  975. NULL);
  976. if (r) {
  977. dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
  978. return r;
  979. }
  980. ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
  981. return r;
  982. }
  983. static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
  984. {
  985. int i;
  986. for (i = 0; i < NGG_BUF_MAX; i++)
  987. amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
  988. &adev->gfx.ngg.buf[i].gpu_addr,
  989. NULL);
  990. memset(&adev->gfx.ngg.buf[0], 0,
  991. sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
  992. adev->gfx.ngg.init = false;
  993. return 0;
  994. }
  995. static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
  996. {
  997. int r;
  998. if (!amdgpu_ngg || adev->gfx.ngg.init == true)
  999. return 0;
  1000. /* GDS reserve memory: 64 bytes alignment */
  1001. adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
  1002. adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
  1003. adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
  1004. adev->gfx.ngg.gds_reserve_addr = amdgpu_gds_reg_offset[0].mem_base;
  1005. adev->gfx.ngg.gds_reserve_addr += adev->gds.mem.gfx_partition_size;
  1006. /* Primitive Buffer */
  1007. r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
  1008. amdgpu_prim_buf_per_se,
  1009. 64 * 1024);
  1010. if (r) {
  1011. dev_err(adev->dev, "Failed to create Primitive Buffer\n");
  1012. goto err;
  1013. }
  1014. /* Position Buffer */
  1015. r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
  1016. amdgpu_pos_buf_per_se,
  1017. 256 * 1024);
  1018. if (r) {
  1019. dev_err(adev->dev, "Failed to create Position Buffer\n");
  1020. goto err;
  1021. }
  1022. /* Control Sideband */
  1023. r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
  1024. amdgpu_cntl_sb_buf_per_se,
  1025. 256);
  1026. if (r) {
  1027. dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
  1028. goto err;
  1029. }
  1030. /* Parameter Cache, not created by default */
  1031. if (amdgpu_param_buf_per_se <= 0)
  1032. goto out;
  1033. r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
  1034. amdgpu_param_buf_per_se,
  1035. 512 * 1024);
  1036. if (r) {
  1037. dev_err(adev->dev, "Failed to create Parameter Cache\n");
  1038. goto err;
  1039. }
  1040. out:
  1041. adev->gfx.ngg.init = true;
  1042. return 0;
  1043. err:
  1044. gfx_v9_0_ngg_fini(adev);
  1045. return r;
  1046. }
  1047. static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
  1048. {
  1049. struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
  1050. int r;
  1051. u32 data;
  1052. u32 size;
  1053. u32 base;
  1054. if (!amdgpu_ngg)
  1055. return 0;
  1056. /* Program buffer size */
  1057. data = 0;
  1058. size = adev->gfx.ngg.buf[NGG_PRIM].size / 256;
  1059. data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE, size);
  1060. size = adev->gfx.ngg.buf[NGG_POS].size / 256;
  1061. data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE, size);
  1062. WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
  1063. data = 0;
  1064. size = adev->gfx.ngg.buf[NGG_CNTL].size / 256;
  1065. data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE, size);
  1066. size = adev->gfx.ngg.buf[NGG_PARAM].size / 1024;
  1067. data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE, size);
  1068. WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
  1069. /* Program buffer base address */
  1070. base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
  1071. data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
  1072. WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
  1073. base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
  1074. data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
  1075. WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
  1076. base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
  1077. data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
  1078. WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
  1079. base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
  1080. data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
  1081. WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
  1082. base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
  1083. data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
  1084. WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
  1085. base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
  1086. data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
  1087. WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
  1088. /* Clear GDS reserved memory */
  1089. r = amdgpu_ring_alloc(ring, 17);
  1090. if (r) {
  1091. DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
  1092. ring->idx, r);
  1093. return r;
  1094. }
  1095. gfx_v9_0_write_data_to_reg(ring, 0, false,
  1096. amdgpu_gds_reg_offset[0].mem_size,
  1097. (adev->gds.mem.total_size +
  1098. adev->gfx.ngg.gds_reserve_size) >>
  1099. AMDGPU_GDS_SHIFT);
  1100. amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
  1101. amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
  1102. PACKET3_DMA_DATA_SRC_SEL(2)));
  1103. amdgpu_ring_write(ring, 0);
  1104. amdgpu_ring_write(ring, 0);
  1105. amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
  1106. amdgpu_ring_write(ring, 0);
  1107. amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_size);
  1108. gfx_v9_0_write_data_to_reg(ring, 0, false,
  1109. amdgpu_gds_reg_offset[0].mem_size, 0);
  1110. amdgpu_ring_commit(ring);
  1111. return 0;
  1112. }
  1113. static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
  1114. int mec, int pipe, int queue)
  1115. {
  1116. int r;
  1117. unsigned irq_type;
  1118. struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
  1119. ring = &adev->gfx.compute_ring[ring_id];
  1120. /* mec0 is me1 */
  1121. ring->me = mec + 1;
  1122. ring->pipe = pipe;
  1123. ring->queue = queue;
  1124. ring->ring_obj = NULL;
  1125. ring->use_doorbell = true;
  1126. ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
  1127. ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
  1128. + (ring_id * GFX9_MEC_HPD_SIZE);
  1129. sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
  1130. irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
  1131. + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
  1132. + ring->pipe;
  1133. /* type-2 packets are deprecated on MEC, use type-3 instead */
  1134. r = amdgpu_ring_init(adev, ring, 1024,
  1135. &adev->gfx.eop_irq, irq_type);
  1136. if (r)
  1137. return r;
  1138. return 0;
  1139. }
  1140. static int gfx_v9_0_sw_init(void *handle)
  1141. {
  1142. int i, j, k, r, ring_id;
  1143. struct amdgpu_ring *ring;
  1144. struct amdgpu_kiq *kiq;
  1145. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1146. switch (adev->asic_type) {
  1147. case CHIP_VEGA10:
  1148. case CHIP_RAVEN:
  1149. adev->gfx.mec.num_mec = 2;
  1150. break;
  1151. default:
  1152. adev->gfx.mec.num_mec = 1;
  1153. break;
  1154. }
  1155. adev->gfx.mec.num_pipe_per_mec = 4;
  1156. adev->gfx.mec.num_queue_per_pipe = 8;
  1157. /* KIQ event */
  1158. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 178, &adev->gfx.kiq.irq);
  1159. if (r)
  1160. return r;
  1161. /* EOP Event */
  1162. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 181, &adev->gfx.eop_irq);
  1163. if (r)
  1164. return r;
  1165. /* Privileged reg */
  1166. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 184,
  1167. &adev->gfx.priv_reg_irq);
  1168. if (r)
  1169. return r;
  1170. /* Privileged inst */
  1171. r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_GRBM_CP, 185,
  1172. &adev->gfx.priv_inst_irq);
  1173. if (r)
  1174. return r;
  1175. adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
  1176. gfx_v9_0_scratch_init(adev);
  1177. r = gfx_v9_0_init_microcode(adev);
  1178. if (r) {
  1179. DRM_ERROR("Failed to load gfx firmware!\n");
  1180. return r;
  1181. }
  1182. r = gfx_v9_0_rlc_init(adev);
  1183. if (r) {
  1184. DRM_ERROR("Failed to init rlc BOs!\n");
  1185. return r;
  1186. }
  1187. r = gfx_v9_0_mec_init(adev);
  1188. if (r) {
  1189. DRM_ERROR("Failed to init MEC BOs!\n");
  1190. return r;
  1191. }
  1192. /* set up the gfx ring */
  1193. for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
  1194. ring = &adev->gfx.gfx_ring[i];
  1195. ring->ring_obj = NULL;
  1196. sprintf(ring->name, "gfx");
  1197. ring->use_doorbell = true;
  1198. ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
  1199. r = amdgpu_ring_init(adev, ring, 1024,
  1200. &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
  1201. if (r)
  1202. return r;
  1203. }
  1204. /* set up the compute queues - allocate horizontally across pipes */
  1205. ring_id = 0;
  1206. for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
  1207. for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
  1208. for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
  1209. if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
  1210. continue;
  1211. r = gfx_v9_0_compute_ring_init(adev,
  1212. ring_id,
  1213. i, k, j);
  1214. if (r)
  1215. return r;
  1216. ring_id++;
  1217. }
  1218. }
  1219. }
  1220. r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
  1221. if (r) {
  1222. DRM_ERROR("Failed to init KIQ BOs!\n");
  1223. return r;
  1224. }
  1225. kiq = &adev->gfx.kiq;
  1226. r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
  1227. if (r)
  1228. return r;
  1229. /* create MQD for all compute queues as wel as KIQ for SRIOV case */
  1230. r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd));
  1231. if (r)
  1232. return r;
  1233. /* reserve GDS, GWS and OA resource for gfx */
  1234. r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
  1235. PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
  1236. &adev->gds.gds_gfx_bo, NULL, NULL);
  1237. if (r)
  1238. return r;
  1239. r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
  1240. PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
  1241. &adev->gds.gws_gfx_bo, NULL, NULL);
  1242. if (r)
  1243. return r;
  1244. r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
  1245. PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
  1246. &adev->gds.oa_gfx_bo, NULL, NULL);
  1247. if (r)
  1248. return r;
  1249. adev->gfx.ce_ram_size = 0x8000;
  1250. gfx_v9_0_gpu_early_init(adev);
  1251. r = gfx_v9_0_ngg_init(adev);
  1252. if (r)
  1253. return r;
  1254. return 0;
  1255. }
  1256. static int gfx_v9_0_sw_fini(void *handle)
  1257. {
  1258. int i;
  1259. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  1260. amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
  1261. amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
  1262. amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
  1263. for (i = 0; i < adev->gfx.num_gfx_rings; i++)
  1264. amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
  1265. for (i = 0; i < adev->gfx.num_compute_rings; i++)
  1266. amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
  1267. amdgpu_gfx_compute_mqd_sw_fini(adev);
  1268. amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
  1269. amdgpu_gfx_kiq_fini(adev);
  1270. gfx_v9_0_mec_fini(adev);
  1271. gfx_v9_0_ngg_fini(adev);
  1272. return 0;
  1273. }
  1274. static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
  1275. {
  1276. /* TODO */
  1277. }
  1278. static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
  1279. {
  1280. u32 data;
  1281. if (instance == 0xffffffff)
  1282. data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
  1283. else
  1284. data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
  1285. if (se_num == 0xffffffff)
  1286. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
  1287. else
  1288. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
  1289. if (sh_num == 0xffffffff)
  1290. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
  1291. else
  1292. data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
  1293. WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
  1294. }
  1295. static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
  1296. {
  1297. u32 data, mask;
  1298. data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
  1299. data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
  1300. data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
  1301. data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
  1302. mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
  1303. adev->gfx.config.max_sh_per_se);
  1304. return (~data) & mask;
  1305. }
  1306. static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
  1307. {
  1308. int i, j;
  1309. u32 data;
  1310. u32 active_rbs = 0;
  1311. u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
  1312. adev->gfx.config.max_sh_per_se;
  1313. mutex_lock(&adev->grbm_idx_mutex);
  1314. for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
  1315. for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
  1316. gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
  1317. data = gfx_v9_0_get_rb_active_bitmap(adev);
  1318. active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
  1319. rb_bitmap_width_per_sh);
  1320. }
  1321. }
  1322. gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  1323. mutex_unlock(&adev->grbm_idx_mutex);
  1324. adev->gfx.config.backend_enable_mask = active_rbs;
  1325. adev->gfx.config.num_rbs = hweight32(active_rbs);
  1326. }
  1327. #define DEFAULT_SH_MEM_BASES (0x6000)
  1328. #define FIRST_COMPUTE_VMID (8)
  1329. #define LAST_COMPUTE_VMID (16)
  1330. static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
  1331. {
  1332. int i;
  1333. uint32_t sh_mem_config;
  1334. uint32_t sh_mem_bases;
  1335. /*
  1336. * Configure apertures:
  1337. * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
  1338. * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
  1339. * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
  1340. */
  1341. sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
  1342. sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
  1343. SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
  1344. SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
  1345. mutex_lock(&adev->srbm_mutex);
  1346. for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
  1347. soc15_grbm_select(adev, 0, 0, 0, i);
  1348. /* CP and shaders */
  1349. WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
  1350. WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
  1351. }
  1352. soc15_grbm_select(adev, 0, 0, 0, 0);
  1353. mutex_unlock(&adev->srbm_mutex);
  1354. }
  1355. static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
  1356. {
  1357. u32 tmp;
  1358. int i;
  1359. WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
  1360. gfx_v9_0_tiling_mode_table_init(adev);
  1361. gfx_v9_0_setup_rb(adev);
  1362. gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
  1363. /* XXX SH_MEM regs */
  1364. /* where to put LDS, scratch, GPUVM in FSA64 space */
  1365. mutex_lock(&adev->srbm_mutex);
  1366. for (i = 0; i < 16; i++) {
  1367. soc15_grbm_select(adev, 0, 0, 0, i);
  1368. /* CP and shaders */
  1369. tmp = 0;
  1370. tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
  1371. SH_MEM_ALIGNMENT_MODE_UNALIGNED);
  1372. WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
  1373. WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
  1374. }
  1375. soc15_grbm_select(adev, 0, 0, 0, 0);
  1376. mutex_unlock(&adev->srbm_mutex);
  1377. gfx_v9_0_init_compute_vmid(adev);
  1378. mutex_lock(&adev->grbm_idx_mutex);
  1379. /*
  1380. * making sure that the following register writes will be broadcasted
  1381. * to all the shaders
  1382. */
  1383. gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  1384. WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
  1385. (adev->gfx.config.sc_prim_fifo_size_frontend <<
  1386. PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
  1387. (adev->gfx.config.sc_prim_fifo_size_backend <<
  1388. PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
  1389. (adev->gfx.config.sc_hiz_tile_fifo_size <<
  1390. PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
  1391. (adev->gfx.config.sc_earlyz_tile_fifo_size <<
  1392. PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
  1393. mutex_unlock(&adev->grbm_idx_mutex);
  1394. }
  1395. static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
  1396. {
  1397. u32 i, j, k;
  1398. u32 mask;
  1399. mutex_lock(&adev->grbm_idx_mutex);
  1400. for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
  1401. for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
  1402. gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
  1403. for (k = 0; k < adev->usec_timeout; k++) {
  1404. if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
  1405. break;
  1406. udelay(1);
  1407. }
  1408. }
  1409. }
  1410. gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  1411. mutex_unlock(&adev->grbm_idx_mutex);
  1412. mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
  1413. RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
  1414. RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
  1415. RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
  1416. for (k = 0; k < adev->usec_timeout; k++) {
  1417. if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
  1418. break;
  1419. udelay(1);
  1420. }
  1421. }
  1422. static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
  1423. bool enable)
  1424. {
  1425. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
  1426. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
  1427. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
  1428. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
  1429. tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
  1430. WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
  1431. }
  1432. static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
  1433. {
  1434. /* csib */
  1435. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
  1436. adev->gfx.rlc.clear_state_gpu_addr >> 32);
  1437. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
  1438. adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
  1439. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
  1440. adev->gfx.rlc.clear_state_size);
  1441. }
  1442. static void gfx_v9_0_parse_ind_reg_list(int *register_list_format,
  1443. int indirect_offset,
  1444. int list_size,
  1445. int *unique_indirect_regs,
  1446. int *unique_indirect_reg_count,
  1447. int max_indirect_reg_count,
  1448. int *indirect_start_offsets,
  1449. int *indirect_start_offsets_count,
  1450. int max_indirect_start_offsets_count)
  1451. {
  1452. int idx;
  1453. bool new_entry = true;
  1454. for (; indirect_offset < list_size; indirect_offset++) {
  1455. if (new_entry) {
  1456. new_entry = false;
  1457. indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
  1458. *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
  1459. BUG_ON(*indirect_start_offsets_count >= max_indirect_start_offsets_count);
  1460. }
  1461. if (register_list_format[indirect_offset] == 0xFFFFFFFF) {
  1462. new_entry = true;
  1463. continue;
  1464. }
  1465. indirect_offset += 2;
  1466. /* look for the matching indice */
  1467. for (idx = 0; idx < *unique_indirect_reg_count; idx++) {
  1468. if (unique_indirect_regs[idx] ==
  1469. register_list_format[indirect_offset])
  1470. break;
  1471. }
  1472. if (idx >= *unique_indirect_reg_count) {
  1473. unique_indirect_regs[*unique_indirect_reg_count] =
  1474. register_list_format[indirect_offset];
  1475. idx = *unique_indirect_reg_count;
  1476. *unique_indirect_reg_count = *unique_indirect_reg_count + 1;
  1477. BUG_ON(*unique_indirect_reg_count >= max_indirect_reg_count);
  1478. }
  1479. register_list_format[indirect_offset] = idx;
  1480. }
  1481. }
  1482. static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev)
  1483. {
  1484. int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
  1485. int unique_indirect_reg_count = 0;
  1486. int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
  1487. int indirect_start_offsets_count = 0;
  1488. int list_size = 0;
  1489. int i = 0;
  1490. u32 tmp = 0;
  1491. u32 *register_list_format =
  1492. kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
  1493. if (!register_list_format)
  1494. return -ENOMEM;
  1495. memcpy(register_list_format, adev->gfx.rlc.register_list_format,
  1496. adev->gfx.rlc.reg_list_format_size_bytes);
  1497. /* setup unique_indirect_regs array and indirect_start_offsets array */
  1498. gfx_v9_0_parse_ind_reg_list(register_list_format,
  1499. GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
  1500. adev->gfx.rlc.reg_list_format_size_bytes >> 2,
  1501. unique_indirect_regs,
  1502. &unique_indirect_reg_count,
  1503. sizeof(unique_indirect_regs)/sizeof(int),
  1504. indirect_start_offsets,
  1505. &indirect_start_offsets_count,
  1506. sizeof(indirect_start_offsets)/sizeof(int));
  1507. /* enable auto inc in case it is disabled */
  1508. tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
  1509. tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
  1510. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
  1511. /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
  1512. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
  1513. RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
  1514. for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
  1515. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
  1516. adev->gfx.rlc.register_restore[i]);
  1517. /* load direct register */
  1518. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
  1519. for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
  1520. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
  1521. adev->gfx.rlc.register_restore[i]);
  1522. /* load indirect register */
  1523. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
  1524. adev->gfx.rlc.reg_list_format_start);
  1525. for (i = 0; i < adev->gfx.rlc.reg_list_format_size_bytes >> 2; i++)
  1526. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
  1527. register_list_format[i]);
  1528. /* set save/restore list size */
  1529. list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
  1530. list_size = list_size >> 1;
  1531. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
  1532. adev->gfx.rlc.reg_restore_list_size);
  1533. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
  1534. /* write the starting offsets to RLC scratch ram */
  1535. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
  1536. adev->gfx.rlc.starting_offsets_start);
  1537. for (i = 0; i < sizeof(indirect_start_offsets)/sizeof(int); i++)
  1538. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
  1539. indirect_start_offsets[i]);
  1540. /* load unique indirect regs*/
  1541. for (i = 0; i < sizeof(unique_indirect_regs)/sizeof(int); i++) {
  1542. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i,
  1543. unique_indirect_regs[i] & 0x3FFFF);
  1544. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i,
  1545. unique_indirect_regs[i] >> 20);
  1546. }
  1547. kfree(register_list_format);
  1548. return 0;
  1549. }
  1550. static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
  1551. {
  1552. u32 tmp = 0;
  1553. tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
  1554. tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
  1555. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
  1556. }
  1557. static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
  1558. bool enable)
  1559. {
  1560. uint32_t data = 0;
  1561. uint32_t default_data = 0;
  1562. default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
  1563. if (enable == true) {
  1564. /* enable GFXIP control over CGPG */
  1565. data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
  1566. if(default_data != data)
  1567. WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
  1568. /* update status */
  1569. data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
  1570. data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
  1571. if(default_data != data)
  1572. WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
  1573. } else {
  1574. /* restore GFXIP control over GCPG */
  1575. data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
  1576. if(default_data != data)
  1577. WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
  1578. }
  1579. }
  1580. static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
  1581. {
  1582. uint32_t data = 0;
  1583. if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
  1584. AMD_PG_SUPPORT_GFX_SMG |
  1585. AMD_PG_SUPPORT_GFX_DMG)) {
  1586. /* init IDLE_POLL_COUNT = 60 */
  1587. data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
  1588. data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
  1589. data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
  1590. WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
  1591. /* init RLC PG Delay */
  1592. data = 0;
  1593. data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
  1594. data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
  1595. data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
  1596. data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
  1597. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
  1598. data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
  1599. data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
  1600. data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
  1601. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
  1602. data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
  1603. data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
  1604. data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
  1605. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
  1606. data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
  1607. data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
  1608. /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
  1609. data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
  1610. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
  1611. pwr_10_0_gfxip_control_over_cgpg(adev, true);
  1612. }
  1613. }
  1614. static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
  1615. bool enable)
  1616. {
  1617. uint32_t data = 0;
  1618. uint32_t default_data = 0;
  1619. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1620. if (enable == true) {
  1621. data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
  1622. if (default_data != data)
  1623. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1624. } else {
  1625. data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
  1626. if(default_data != data)
  1627. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1628. }
  1629. }
  1630. static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
  1631. bool enable)
  1632. {
  1633. uint32_t data = 0;
  1634. uint32_t default_data = 0;
  1635. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1636. if (enable == true) {
  1637. data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
  1638. if(default_data != data)
  1639. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1640. } else {
  1641. data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
  1642. if(default_data != data)
  1643. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1644. }
  1645. }
  1646. static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
  1647. bool enable)
  1648. {
  1649. uint32_t data = 0;
  1650. uint32_t default_data = 0;
  1651. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1652. if (enable == true) {
  1653. data &= ~RLC_PG_CNTL__CP_PG_DISABLE_MASK;
  1654. if(default_data != data)
  1655. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1656. } else {
  1657. data |= RLC_PG_CNTL__CP_PG_DISABLE_MASK;
  1658. if(default_data != data)
  1659. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1660. }
  1661. }
  1662. static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
  1663. bool enable)
  1664. {
  1665. uint32_t data, default_data;
  1666. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1667. if (enable == true)
  1668. data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
  1669. else
  1670. data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
  1671. if(default_data != data)
  1672. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1673. }
  1674. static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
  1675. bool enable)
  1676. {
  1677. uint32_t data, default_data;
  1678. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1679. if (enable == true)
  1680. data |= RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
  1681. else
  1682. data &= ~RLC_PG_CNTL__GFX_PIPELINE_PG_ENABLE_MASK;
  1683. if(default_data != data)
  1684. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1685. if (!enable)
  1686. /* read any GFX register to wake up GFX */
  1687. data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
  1688. }
  1689. static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
  1690. bool enable)
  1691. {
  1692. uint32_t data, default_data;
  1693. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1694. if (enable == true)
  1695. data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
  1696. else
  1697. data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
  1698. if(default_data != data)
  1699. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1700. }
  1701. static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
  1702. bool enable)
  1703. {
  1704. uint32_t data, default_data;
  1705. default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
  1706. if (enable == true)
  1707. data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
  1708. else
  1709. data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
  1710. if(default_data != data)
  1711. WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
  1712. }
  1713. static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
  1714. {
  1715. if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
  1716. AMD_PG_SUPPORT_GFX_SMG |
  1717. AMD_PG_SUPPORT_GFX_DMG |
  1718. AMD_PG_SUPPORT_CP |
  1719. AMD_PG_SUPPORT_GDS |
  1720. AMD_PG_SUPPORT_RLC_SMU_HS)) {
  1721. gfx_v9_0_init_csb(adev);
  1722. gfx_v9_0_init_rlc_save_restore_list(adev);
  1723. gfx_v9_0_enable_save_restore_machine(adev);
  1724. if (adev->asic_type == CHIP_RAVEN) {
  1725. WREG32(mmRLC_JUMP_TABLE_RESTORE,
  1726. adev->gfx.rlc.cp_table_gpu_addr >> 8);
  1727. gfx_v9_0_init_gfx_power_gating(adev);
  1728. if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
  1729. gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
  1730. gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
  1731. } else {
  1732. gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
  1733. gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
  1734. }
  1735. if (adev->pg_flags & AMD_PG_SUPPORT_CP)
  1736. gfx_v9_0_enable_cp_power_gating(adev, true);
  1737. else
  1738. gfx_v9_0_enable_cp_power_gating(adev, false);
  1739. }
  1740. }
  1741. }
  1742. void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
  1743. {
  1744. u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
  1745. tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
  1746. WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
  1747. gfx_v9_0_enable_gui_idle_interrupt(adev, false);
  1748. gfx_v9_0_wait_for_rlc_serdes(adev);
  1749. }
  1750. static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
  1751. {
  1752. WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
  1753. udelay(50);
  1754. WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
  1755. udelay(50);
  1756. }
  1757. static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
  1758. {
  1759. #ifdef AMDGPU_RLC_DEBUG_RETRY
  1760. u32 rlc_ucode_ver;
  1761. #endif
  1762. WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
  1763. /* carrizo do enable cp interrupt after cp inited */
  1764. if (!(adev->flags & AMD_IS_APU))
  1765. gfx_v9_0_enable_gui_idle_interrupt(adev, true);
  1766. udelay(50);
  1767. #ifdef AMDGPU_RLC_DEBUG_RETRY
  1768. /* RLC_GPM_GENERAL_6 : RLC Ucode version */
  1769. rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
  1770. if(rlc_ucode_ver == 0x108) {
  1771. DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
  1772. rlc_ucode_ver, adev->gfx.rlc_fw_version);
  1773. /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
  1774. * default is 0x9C4 to create a 100us interval */
  1775. WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
  1776. /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
  1777. * to disable the page fault retry interrupts, default is
  1778. * 0x100 (256) */
  1779. WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
  1780. }
  1781. #endif
  1782. }
  1783. static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
  1784. {
  1785. const struct rlc_firmware_header_v2_0 *hdr;
  1786. const __le32 *fw_data;
  1787. unsigned i, fw_size;
  1788. if (!adev->gfx.rlc_fw)
  1789. return -EINVAL;
  1790. hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
  1791. amdgpu_ucode_print_rlc_hdr(&hdr->header);
  1792. fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
  1793. le32_to_cpu(hdr->header.ucode_array_offset_bytes));
  1794. fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
  1795. WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
  1796. RLCG_UCODE_LOADING_START_ADDRESS);
  1797. for (i = 0; i < fw_size; i++)
  1798. WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
  1799. WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
  1800. return 0;
  1801. }
  1802. static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
  1803. {
  1804. int r;
  1805. if (amdgpu_sriov_vf(adev))
  1806. return 0;
  1807. gfx_v9_0_rlc_stop(adev);
  1808. /* disable CG */
  1809. WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
  1810. /* disable PG */
  1811. WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
  1812. gfx_v9_0_rlc_reset(adev);
  1813. gfx_v9_0_init_pg(adev);
  1814. if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
  1815. /* legacy rlc firmware loading */
  1816. r = gfx_v9_0_rlc_load_microcode(adev);
  1817. if (r)
  1818. return r;
  1819. }
  1820. if (adev->asic_type == CHIP_RAVEN) {
  1821. if (amdgpu_lbpw != 0)
  1822. gfx_v9_0_enable_lbpw(adev, true);
  1823. else
  1824. gfx_v9_0_enable_lbpw(adev, false);
  1825. }
  1826. gfx_v9_0_rlc_start(adev);
  1827. return 0;
  1828. }
  1829. static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
  1830. {
  1831. int i;
  1832. u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
  1833. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
  1834. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
  1835. tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
  1836. if (!enable) {
  1837. for (i = 0; i < adev->gfx.num_gfx_rings; i++)
  1838. adev->gfx.gfx_ring[i].ready = false;
  1839. }
  1840. WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
  1841. udelay(50);
  1842. }
  1843. static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
  1844. {
  1845. const struct gfx_firmware_header_v1_0 *pfp_hdr;
  1846. const struct gfx_firmware_header_v1_0 *ce_hdr;
  1847. const struct gfx_firmware_header_v1_0 *me_hdr;
  1848. const __le32 *fw_data;
  1849. unsigned i, fw_size;
  1850. if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
  1851. return -EINVAL;
  1852. pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
  1853. adev->gfx.pfp_fw->data;
  1854. ce_hdr = (const struct gfx_firmware_header_v1_0 *)
  1855. adev->gfx.ce_fw->data;
  1856. me_hdr = (const struct gfx_firmware_header_v1_0 *)
  1857. adev->gfx.me_fw->data;
  1858. amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
  1859. amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
  1860. amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
  1861. gfx_v9_0_cp_gfx_enable(adev, false);
  1862. /* PFP */
  1863. fw_data = (const __le32 *)
  1864. (adev->gfx.pfp_fw->data +
  1865. le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
  1866. fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
  1867. WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
  1868. for (i = 0; i < fw_size; i++)
  1869. WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
  1870. WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
  1871. /* CE */
  1872. fw_data = (const __le32 *)
  1873. (adev->gfx.ce_fw->data +
  1874. le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
  1875. fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
  1876. WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
  1877. for (i = 0; i < fw_size; i++)
  1878. WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
  1879. WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
  1880. /* ME */
  1881. fw_data = (const __le32 *)
  1882. (adev->gfx.me_fw->data +
  1883. le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
  1884. fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
  1885. WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
  1886. for (i = 0; i < fw_size; i++)
  1887. WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
  1888. WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
  1889. return 0;
  1890. }
  1891. static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
  1892. {
  1893. struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
  1894. const struct cs_section_def *sect = NULL;
  1895. const struct cs_extent_def *ext = NULL;
  1896. int r, i;
  1897. /* init the CP */
  1898. WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
  1899. WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
  1900. gfx_v9_0_cp_gfx_enable(adev, true);
  1901. r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4);
  1902. if (r) {
  1903. DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
  1904. return r;
  1905. }
  1906. amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  1907. amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
  1908. amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
  1909. amdgpu_ring_write(ring, 0x80000000);
  1910. amdgpu_ring_write(ring, 0x80000000);
  1911. for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
  1912. for (ext = sect->section; ext->extent != NULL; ++ext) {
  1913. if (sect->id == SECT_CONTEXT) {
  1914. amdgpu_ring_write(ring,
  1915. PACKET3(PACKET3_SET_CONTEXT_REG,
  1916. ext->reg_count));
  1917. amdgpu_ring_write(ring,
  1918. ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
  1919. for (i = 0; i < ext->reg_count; i++)
  1920. amdgpu_ring_write(ring, ext->extent[i]);
  1921. }
  1922. }
  1923. }
  1924. amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
  1925. amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
  1926. amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
  1927. amdgpu_ring_write(ring, 0);
  1928. amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
  1929. amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
  1930. amdgpu_ring_write(ring, 0x8000);
  1931. amdgpu_ring_write(ring, 0x8000);
  1932. amdgpu_ring_commit(ring);
  1933. return 0;
  1934. }
  1935. static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
  1936. {
  1937. struct amdgpu_ring *ring;
  1938. u32 tmp;
  1939. u32 rb_bufsz;
  1940. u64 rb_addr, rptr_addr, wptr_gpu_addr;
  1941. /* Set the write pointer delay */
  1942. WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
  1943. /* set the RB to use vmid 0 */
  1944. WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
  1945. /* Set ring buffer size */
  1946. ring = &adev->gfx.gfx_ring[0];
  1947. rb_bufsz = order_base_2(ring->ring_size / 8);
  1948. tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
  1949. tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
  1950. #ifdef __BIG_ENDIAN
  1951. tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
  1952. #endif
  1953. WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
  1954. /* Initialize the ring buffer's write pointers */
  1955. ring->wptr = 0;
  1956. WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
  1957. WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
  1958. /* set the wb address wether it's enabled or not */
  1959. rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
  1960. WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
  1961. WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
  1962. wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  1963. WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
  1964. WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
  1965. mdelay(1);
  1966. WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
  1967. rb_addr = ring->gpu_addr >> 8;
  1968. WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
  1969. WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
  1970. tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
  1971. if (ring->use_doorbell) {
  1972. tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
  1973. DOORBELL_OFFSET, ring->doorbell_index);
  1974. tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
  1975. DOORBELL_EN, 1);
  1976. } else {
  1977. tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
  1978. }
  1979. WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
  1980. tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
  1981. DOORBELL_RANGE_LOWER, ring->doorbell_index);
  1982. WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
  1983. WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
  1984. CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
  1985. /* start the ring */
  1986. gfx_v9_0_cp_gfx_start(adev);
  1987. ring->ready = true;
  1988. return 0;
  1989. }
  1990. static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
  1991. {
  1992. int i;
  1993. if (enable) {
  1994. WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
  1995. } else {
  1996. WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
  1997. (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
  1998. for (i = 0; i < adev->gfx.num_compute_rings; i++)
  1999. adev->gfx.compute_ring[i].ready = false;
  2000. adev->gfx.kiq.ring.ready = false;
  2001. }
  2002. udelay(50);
  2003. }
  2004. static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
  2005. {
  2006. const struct gfx_firmware_header_v1_0 *mec_hdr;
  2007. const __le32 *fw_data;
  2008. unsigned i;
  2009. u32 tmp;
  2010. if (!adev->gfx.mec_fw)
  2011. return -EINVAL;
  2012. gfx_v9_0_cp_compute_enable(adev, false);
  2013. mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
  2014. amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
  2015. fw_data = (const __le32 *)
  2016. (adev->gfx.mec_fw->data +
  2017. le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
  2018. tmp = 0;
  2019. tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
  2020. tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
  2021. WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
  2022. WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
  2023. adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
  2024. WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
  2025. upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
  2026. /* MEC1 */
  2027. WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
  2028. mec_hdr->jt_offset);
  2029. for (i = 0; i < mec_hdr->jt_size; i++)
  2030. WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
  2031. le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
  2032. WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
  2033. adev->gfx.mec_fw_version);
  2034. /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
  2035. return 0;
  2036. }
  2037. /* KIQ functions */
  2038. static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
  2039. {
  2040. uint32_t tmp;
  2041. struct amdgpu_device *adev = ring->adev;
  2042. /* tell RLC which is KIQ queue */
  2043. tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
  2044. tmp &= 0xffffff00;
  2045. tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
  2046. WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
  2047. tmp |= 0x80;
  2048. WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
  2049. }
  2050. static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
  2051. {
  2052. struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
  2053. uint32_t scratch, tmp = 0;
  2054. uint64_t queue_mask = 0;
  2055. int r, i;
  2056. for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
  2057. if (!test_bit(i, adev->gfx.mec.queue_bitmap))
  2058. continue;
  2059. /* This situation may be hit in the future if a new HW
  2060. * generation exposes more than 64 queues. If so, the
  2061. * definition of queue_mask needs updating */
  2062. if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
  2063. DRM_ERROR("Invalid KCQ enabled: %d\n", i);
  2064. break;
  2065. }
  2066. queue_mask |= (1ull << i);
  2067. }
  2068. r = amdgpu_gfx_scratch_get(adev, &scratch);
  2069. if (r) {
  2070. DRM_ERROR("Failed to get scratch reg (%d).\n", r);
  2071. return r;
  2072. }
  2073. WREG32(scratch, 0xCAFEDEAD);
  2074. r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 11);
  2075. if (r) {
  2076. DRM_ERROR("Failed to lock KIQ (%d).\n", r);
  2077. amdgpu_gfx_scratch_free(adev, scratch);
  2078. return r;
  2079. }
  2080. /* set resources */
  2081. amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
  2082. amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
  2083. PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
  2084. amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
  2085. amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
  2086. amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
  2087. amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
  2088. amdgpu_ring_write(kiq_ring, 0); /* oac mask */
  2089. amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
  2090. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  2091. struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
  2092. uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
  2093. uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  2094. amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
  2095. /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
  2096. amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
  2097. PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
  2098. PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
  2099. PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
  2100. PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
  2101. PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
  2102. PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
  2103. PACKET3_MAP_QUEUES_ALLOC_FORMAT(1) | /* alloc format: all_on_one_pipe */
  2104. PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
  2105. PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
  2106. amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
  2107. amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
  2108. amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
  2109. amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
  2110. amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
  2111. }
  2112. /* write to scratch for completion */
  2113. amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
  2114. amdgpu_ring_write(kiq_ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
  2115. amdgpu_ring_write(kiq_ring, 0xDEADBEEF);
  2116. amdgpu_ring_commit(kiq_ring);
  2117. for (i = 0; i < adev->usec_timeout; i++) {
  2118. tmp = RREG32(scratch);
  2119. if (tmp == 0xDEADBEEF)
  2120. break;
  2121. DRM_UDELAY(1);
  2122. }
  2123. if (i >= adev->usec_timeout) {
  2124. DRM_ERROR("KCQ enable failed (scratch(0x%04X)=0x%08X)\n",
  2125. scratch, tmp);
  2126. r = -EINVAL;
  2127. }
  2128. amdgpu_gfx_scratch_free(adev, scratch);
  2129. return r;
  2130. }
  2131. static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
  2132. {
  2133. struct amdgpu_device *adev = ring->adev;
  2134. struct v9_mqd *mqd = ring->mqd_ptr;
  2135. uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
  2136. uint32_t tmp;
  2137. mqd->header = 0xC0310800;
  2138. mqd->compute_pipelinestat_enable = 0x00000001;
  2139. mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
  2140. mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
  2141. mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
  2142. mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
  2143. mqd->compute_misc_reserved = 0x00000003;
  2144. eop_base_addr = ring->eop_gpu_addr >> 8;
  2145. mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
  2146. mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
  2147. /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
  2148. tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
  2149. tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
  2150. (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
  2151. mqd->cp_hqd_eop_control = tmp;
  2152. /* enable doorbell? */
  2153. tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
  2154. if (ring->use_doorbell) {
  2155. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2156. DOORBELL_OFFSET, ring->doorbell_index);
  2157. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2158. DOORBELL_EN, 1);
  2159. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2160. DOORBELL_SOURCE, 0);
  2161. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2162. DOORBELL_HIT, 0);
  2163. }
  2164. else
  2165. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2166. DOORBELL_EN, 0);
  2167. mqd->cp_hqd_pq_doorbell_control = tmp;
  2168. /* disable the queue if it's active */
  2169. ring->wptr = 0;
  2170. mqd->cp_hqd_dequeue_request = 0;
  2171. mqd->cp_hqd_pq_rptr = 0;
  2172. mqd->cp_hqd_pq_wptr_lo = 0;
  2173. mqd->cp_hqd_pq_wptr_hi = 0;
  2174. /* set the pointer to the MQD */
  2175. mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
  2176. mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
  2177. /* set MQD vmid to 0 */
  2178. tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
  2179. tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
  2180. mqd->cp_mqd_control = tmp;
  2181. /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
  2182. hqd_gpu_addr = ring->gpu_addr >> 8;
  2183. mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
  2184. mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
  2185. /* set up the HQD, this is similar to CP_RB0_CNTL */
  2186. tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
  2187. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
  2188. (order_base_2(ring->ring_size / 4) - 1));
  2189. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
  2190. ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
  2191. #ifdef __BIG_ENDIAN
  2192. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
  2193. #endif
  2194. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
  2195. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
  2196. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
  2197. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
  2198. mqd->cp_hqd_pq_control = tmp;
  2199. /* set the wb address whether it's enabled or not */
  2200. wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
  2201. mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
  2202. mqd->cp_hqd_pq_rptr_report_addr_hi =
  2203. upper_32_bits(wb_gpu_addr) & 0xffff;
  2204. /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
  2205. wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
  2206. mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
  2207. mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
  2208. tmp = 0;
  2209. /* enable the doorbell if requested */
  2210. if (ring->use_doorbell) {
  2211. tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
  2212. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2213. DOORBELL_OFFSET, ring->doorbell_index);
  2214. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2215. DOORBELL_EN, 1);
  2216. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2217. DOORBELL_SOURCE, 0);
  2218. tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
  2219. DOORBELL_HIT, 0);
  2220. }
  2221. mqd->cp_hqd_pq_doorbell_control = tmp;
  2222. /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
  2223. ring->wptr = 0;
  2224. mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
  2225. /* set the vmid for the queue */
  2226. mqd->cp_hqd_vmid = 0;
  2227. tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
  2228. tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
  2229. mqd->cp_hqd_persistent_state = tmp;
  2230. /* set MIN_IB_AVAIL_SIZE */
  2231. tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
  2232. tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
  2233. mqd->cp_hqd_ib_control = tmp;
  2234. /* activate the queue */
  2235. mqd->cp_hqd_active = 1;
  2236. return 0;
  2237. }
  2238. static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
  2239. {
  2240. struct amdgpu_device *adev = ring->adev;
  2241. struct v9_mqd *mqd = ring->mqd_ptr;
  2242. int j;
  2243. /* disable wptr polling */
  2244. WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
  2245. WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
  2246. mqd->cp_hqd_eop_base_addr_lo);
  2247. WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
  2248. mqd->cp_hqd_eop_base_addr_hi);
  2249. /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
  2250. WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
  2251. mqd->cp_hqd_eop_control);
  2252. /* enable doorbell? */
  2253. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
  2254. mqd->cp_hqd_pq_doorbell_control);
  2255. /* disable the queue if it's active */
  2256. if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
  2257. WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
  2258. for (j = 0; j < adev->usec_timeout; j++) {
  2259. if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
  2260. break;
  2261. udelay(1);
  2262. }
  2263. WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
  2264. mqd->cp_hqd_dequeue_request);
  2265. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
  2266. mqd->cp_hqd_pq_rptr);
  2267. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
  2268. mqd->cp_hqd_pq_wptr_lo);
  2269. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
  2270. mqd->cp_hqd_pq_wptr_hi);
  2271. }
  2272. /* set the pointer to the MQD */
  2273. WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
  2274. mqd->cp_mqd_base_addr_lo);
  2275. WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
  2276. mqd->cp_mqd_base_addr_hi);
  2277. /* set MQD vmid to 0 */
  2278. WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
  2279. mqd->cp_mqd_control);
  2280. /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
  2281. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
  2282. mqd->cp_hqd_pq_base_lo);
  2283. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
  2284. mqd->cp_hqd_pq_base_hi);
  2285. /* set up the HQD, this is similar to CP_RB0_CNTL */
  2286. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
  2287. mqd->cp_hqd_pq_control);
  2288. /* set the wb address whether it's enabled or not */
  2289. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
  2290. mqd->cp_hqd_pq_rptr_report_addr_lo);
  2291. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
  2292. mqd->cp_hqd_pq_rptr_report_addr_hi);
  2293. /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
  2294. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
  2295. mqd->cp_hqd_pq_wptr_poll_addr_lo);
  2296. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
  2297. mqd->cp_hqd_pq_wptr_poll_addr_hi);
  2298. /* enable the doorbell if requested */
  2299. if (ring->use_doorbell) {
  2300. WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
  2301. (AMDGPU_DOORBELL64_KIQ *2) << 2);
  2302. WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
  2303. (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
  2304. }
  2305. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
  2306. mqd->cp_hqd_pq_doorbell_control);
  2307. /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
  2308. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
  2309. mqd->cp_hqd_pq_wptr_lo);
  2310. WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
  2311. mqd->cp_hqd_pq_wptr_hi);
  2312. /* set the vmid for the queue */
  2313. WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
  2314. WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
  2315. mqd->cp_hqd_persistent_state);
  2316. /* activate the queue */
  2317. WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
  2318. mqd->cp_hqd_active);
  2319. if (ring->use_doorbell)
  2320. WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
  2321. return 0;
  2322. }
  2323. static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
  2324. {
  2325. struct amdgpu_device *adev = ring->adev;
  2326. struct v9_mqd *mqd = ring->mqd_ptr;
  2327. int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
  2328. gfx_v9_0_kiq_setting(ring);
  2329. if (adev->gfx.in_reset) { /* for GPU_RESET case */
  2330. /* reset MQD to a clean status */
  2331. if (adev->gfx.mec.mqd_backup[mqd_idx])
  2332. memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
  2333. /* reset ring buffer */
  2334. ring->wptr = 0;
  2335. amdgpu_ring_clear_ring(ring);
  2336. mutex_lock(&adev->srbm_mutex);
  2337. soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
  2338. gfx_v9_0_kiq_init_register(ring);
  2339. soc15_grbm_select(adev, 0, 0, 0, 0);
  2340. mutex_unlock(&adev->srbm_mutex);
  2341. } else {
  2342. memset((void *)mqd, 0, sizeof(*mqd));
  2343. mutex_lock(&adev->srbm_mutex);
  2344. soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
  2345. gfx_v9_0_mqd_init(ring);
  2346. gfx_v9_0_kiq_init_register(ring);
  2347. soc15_grbm_select(adev, 0, 0, 0, 0);
  2348. mutex_unlock(&adev->srbm_mutex);
  2349. if (adev->gfx.mec.mqd_backup[mqd_idx])
  2350. memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
  2351. }
  2352. return 0;
  2353. }
  2354. static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
  2355. {
  2356. struct amdgpu_device *adev = ring->adev;
  2357. struct v9_mqd *mqd = ring->mqd_ptr;
  2358. int mqd_idx = ring - &adev->gfx.compute_ring[0];
  2359. if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
  2360. memset((void *)mqd, 0, sizeof(*mqd));
  2361. mutex_lock(&adev->srbm_mutex);
  2362. soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
  2363. gfx_v9_0_mqd_init(ring);
  2364. soc15_grbm_select(adev, 0, 0, 0, 0);
  2365. mutex_unlock(&adev->srbm_mutex);
  2366. if (adev->gfx.mec.mqd_backup[mqd_idx])
  2367. memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
  2368. } else if (adev->gfx.in_reset) { /* for GPU_RESET case */
  2369. /* reset MQD to a clean status */
  2370. if (adev->gfx.mec.mqd_backup[mqd_idx])
  2371. memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
  2372. /* reset ring buffer */
  2373. ring->wptr = 0;
  2374. amdgpu_ring_clear_ring(ring);
  2375. } else {
  2376. amdgpu_ring_clear_ring(ring);
  2377. }
  2378. return 0;
  2379. }
  2380. static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
  2381. {
  2382. struct amdgpu_ring *ring = NULL;
  2383. int r = 0, i;
  2384. gfx_v9_0_cp_compute_enable(adev, true);
  2385. ring = &adev->gfx.kiq.ring;
  2386. r = amdgpu_bo_reserve(ring->mqd_obj, false);
  2387. if (unlikely(r != 0))
  2388. goto done;
  2389. r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
  2390. if (!r) {
  2391. r = gfx_v9_0_kiq_init_queue(ring);
  2392. amdgpu_bo_kunmap(ring->mqd_obj);
  2393. ring->mqd_ptr = NULL;
  2394. }
  2395. amdgpu_bo_unreserve(ring->mqd_obj);
  2396. if (r)
  2397. goto done;
  2398. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  2399. ring = &adev->gfx.compute_ring[i];
  2400. r = amdgpu_bo_reserve(ring->mqd_obj, false);
  2401. if (unlikely(r != 0))
  2402. goto done;
  2403. r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
  2404. if (!r) {
  2405. r = gfx_v9_0_kcq_init_queue(ring);
  2406. amdgpu_bo_kunmap(ring->mqd_obj);
  2407. ring->mqd_ptr = NULL;
  2408. }
  2409. amdgpu_bo_unreserve(ring->mqd_obj);
  2410. if (r)
  2411. goto done;
  2412. }
  2413. r = gfx_v9_0_kiq_kcq_enable(adev);
  2414. done:
  2415. return r;
  2416. }
  2417. static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
  2418. {
  2419. int r, i;
  2420. struct amdgpu_ring *ring;
  2421. if (!(adev->flags & AMD_IS_APU))
  2422. gfx_v9_0_enable_gui_idle_interrupt(adev, false);
  2423. if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
  2424. /* legacy firmware loading */
  2425. r = gfx_v9_0_cp_gfx_load_microcode(adev);
  2426. if (r)
  2427. return r;
  2428. r = gfx_v9_0_cp_compute_load_microcode(adev);
  2429. if (r)
  2430. return r;
  2431. }
  2432. r = gfx_v9_0_cp_gfx_resume(adev);
  2433. if (r)
  2434. return r;
  2435. r = gfx_v9_0_kiq_resume(adev);
  2436. if (r)
  2437. return r;
  2438. ring = &adev->gfx.gfx_ring[0];
  2439. r = amdgpu_ring_test_ring(ring);
  2440. if (r) {
  2441. ring->ready = false;
  2442. return r;
  2443. }
  2444. ring = &adev->gfx.kiq.ring;
  2445. ring->ready = true;
  2446. r = amdgpu_ring_test_ring(ring);
  2447. if (r)
  2448. ring->ready = false;
  2449. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  2450. ring = &adev->gfx.compute_ring[i];
  2451. ring->ready = true;
  2452. r = amdgpu_ring_test_ring(ring);
  2453. if (r)
  2454. ring->ready = false;
  2455. }
  2456. gfx_v9_0_enable_gui_idle_interrupt(adev, true);
  2457. return 0;
  2458. }
  2459. static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
  2460. {
  2461. gfx_v9_0_cp_gfx_enable(adev, enable);
  2462. gfx_v9_0_cp_compute_enable(adev, enable);
  2463. }
  2464. static int gfx_v9_0_hw_init(void *handle)
  2465. {
  2466. int r;
  2467. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2468. gfx_v9_0_init_golden_registers(adev);
  2469. gfx_v9_0_gpu_init(adev);
  2470. r = gfx_v9_0_rlc_resume(adev);
  2471. if (r)
  2472. return r;
  2473. r = gfx_v9_0_cp_resume(adev);
  2474. if (r)
  2475. return r;
  2476. r = gfx_v9_0_ngg_en(adev);
  2477. if (r)
  2478. return r;
  2479. return r;
  2480. }
  2481. static int gfx_v9_0_hw_fini(void *handle)
  2482. {
  2483. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2484. amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
  2485. amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
  2486. if (amdgpu_sriov_vf(adev)) {
  2487. pr_debug("For SRIOV client, shouldn't do anything.\n");
  2488. return 0;
  2489. }
  2490. gfx_v9_0_cp_enable(adev, false);
  2491. gfx_v9_0_rlc_stop(adev);
  2492. return 0;
  2493. }
  2494. static int gfx_v9_0_suspend(void *handle)
  2495. {
  2496. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2497. adev->gfx.in_suspend = true;
  2498. return gfx_v9_0_hw_fini(adev);
  2499. }
  2500. static int gfx_v9_0_resume(void *handle)
  2501. {
  2502. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2503. int r;
  2504. r = gfx_v9_0_hw_init(adev);
  2505. adev->gfx.in_suspend = false;
  2506. return r;
  2507. }
  2508. static bool gfx_v9_0_is_idle(void *handle)
  2509. {
  2510. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2511. if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
  2512. GRBM_STATUS, GUI_ACTIVE))
  2513. return false;
  2514. else
  2515. return true;
  2516. }
  2517. static int gfx_v9_0_wait_for_idle(void *handle)
  2518. {
  2519. unsigned i;
  2520. u32 tmp;
  2521. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2522. for (i = 0; i < adev->usec_timeout; i++) {
  2523. /* read MC_STATUS */
  2524. tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
  2525. GRBM_STATUS__GUI_ACTIVE_MASK;
  2526. if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
  2527. return 0;
  2528. udelay(1);
  2529. }
  2530. return -ETIMEDOUT;
  2531. }
  2532. static int gfx_v9_0_soft_reset(void *handle)
  2533. {
  2534. u32 grbm_soft_reset = 0;
  2535. u32 tmp;
  2536. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2537. /* GRBM_STATUS */
  2538. tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
  2539. if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
  2540. GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
  2541. GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
  2542. GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
  2543. GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
  2544. GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
  2545. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  2546. GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
  2547. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  2548. GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
  2549. }
  2550. if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
  2551. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  2552. GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
  2553. }
  2554. /* GRBM_STATUS2 */
  2555. tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
  2556. if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
  2557. grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
  2558. GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
  2559. if (grbm_soft_reset) {
  2560. /* stop the rlc */
  2561. gfx_v9_0_rlc_stop(adev);
  2562. /* Disable GFX parsing/prefetching */
  2563. gfx_v9_0_cp_gfx_enable(adev, false);
  2564. /* Disable MEC parsing/prefetching */
  2565. gfx_v9_0_cp_compute_enable(adev, false);
  2566. if (grbm_soft_reset) {
  2567. tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
  2568. tmp |= grbm_soft_reset;
  2569. dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
  2570. WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
  2571. tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
  2572. udelay(50);
  2573. tmp &= ~grbm_soft_reset;
  2574. WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
  2575. tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
  2576. }
  2577. /* Wait a little for things to settle down */
  2578. udelay(50);
  2579. }
  2580. return 0;
  2581. }
  2582. static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
  2583. {
  2584. uint64_t clock;
  2585. mutex_lock(&adev->gfx.gpu_clock_mutex);
  2586. WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
  2587. clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
  2588. ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
  2589. mutex_unlock(&adev->gfx.gpu_clock_mutex);
  2590. return clock;
  2591. }
  2592. static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
  2593. uint32_t vmid,
  2594. uint32_t gds_base, uint32_t gds_size,
  2595. uint32_t gws_base, uint32_t gws_size,
  2596. uint32_t oa_base, uint32_t oa_size)
  2597. {
  2598. gds_base = gds_base >> AMDGPU_GDS_SHIFT;
  2599. gds_size = gds_size >> AMDGPU_GDS_SHIFT;
  2600. gws_base = gws_base >> AMDGPU_GWS_SHIFT;
  2601. gws_size = gws_size >> AMDGPU_GWS_SHIFT;
  2602. oa_base = oa_base >> AMDGPU_OA_SHIFT;
  2603. oa_size = oa_size >> AMDGPU_OA_SHIFT;
  2604. /* GDS Base */
  2605. gfx_v9_0_write_data_to_reg(ring, 0, false,
  2606. amdgpu_gds_reg_offset[vmid].mem_base,
  2607. gds_base);
  2608. /* GDS Size */
  2609. gfx_v9_0_write_data_to_reg(ring, 0, false,
  2610. amdgpu_gds_reg_offset[vmid].mem_size,
  2611. gds_size);
  2612. /* GWS */
  2613. gfx_v9_0_write_data_to_reg(ring, 0, false,
  2614. amdgpu_gds_reg_offset[vmid].gws,
  2615. gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
  2616. /* OA */
  2617. gfx_v9_0_write_data_to_reg(ring, 0, false,
  2618. amdgpu_gds_reg_offset[vmid].oa,
  2619. (1 << (oa_size + oa_base)) - (1 << oa_base));
  2620. }
  2621. static int gfx_v9_0_early_init(void *handle)
  2622. {
  2623. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2624. adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
  2625. adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
  2626. gfx_v9_0_set_ring_funcs(adev);
  2627. gfx_v9_0_set_irq_funcs(adev);
  2628. gfx_v9_0_set_gds_init(adev);
  2629. gfx_v9_0_set_rlc_funcs(adev);
  2630. return 0;
  2631. }
  2632. static int gfx_v9_0_late_init(void *handle)
  2633. {
  2634. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2635. int r;
  2636. r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
  2637. if (r)
  2638. return r;
  2639. r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
  2640. if (r)
  2641. return r;
  2642. return 0;
  2643. }
  2644. static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
  2645. {
  2646. uint32_t rlc_setting, data;
  2647. unsigned i;
  2648. if (adev->gfx.rlc.in_safe_mode)
  2649. return;
  2650. /* if RLC is not enabled, do nothing */
  2651. rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
  2652. if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
  2653. return;
  2654. if (adev->cg_flags &
  2655. (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
  2656. AMD_CG_SUPPORT_GFX_3D_CGCG)) {
  2657. data = RLC_SAFE_MODE__CMD_MASK;
  2658. data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
  2659. WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
  2660. /* wait for RLC_SAFE_MODE */
  2661. for (i = 0; i < adev->usec_timeout; i++) {
  2662. if (!REG_GET_FIELD(SOC15_REG_OFFSET(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
  2663. break;
  2664. udelay(1);
  2665. }
  2666. adev->gfx.rlc.in_safe_mode = true;
  2667. }
  2668. }
  2669. static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
  2670. {
  2671. uint32_t rlc_setting, data;
  2672. if (!adev->gfx.rlc.in_safe_mode)
  2673. return;
  2674. /* if RLC is not enabled, do nothing */
  2675. rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
  2676. if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
  2677. return;
  2678. if (adev->cg_flags &
  2679. (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
  2680. /*
  2681. * Try to exit safe mode only if it is already in safe
  2682. * mode.
  2683. */
  2684. data = RLC_SAFE_MODE__CMD_MASK;
  2685. WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
  2686. adev->gfx.rlc.in_safe_mode = false;
  2687. }
  2688. }
  2689. static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
  2690. bool enable)
  2691. {
  2692. /* TODO: double check if we need to perform under safe mdoe */
  2693. /* gfx_v9_0_enter_rlc_safe_mode(adev); */
  2694. if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
  2695. gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
  2696. if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
  2697. gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
  2698. } else {
  2699. gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
  2700. gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
  2701. }
  2702. /* gfx_v9_0_exit_rlc_safe_mode(adev); */
  2703. }
  2704. static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
  2705. bool enable)
  2706. {
  2707. /* TODO: double check if we need to perform under safe mode */
  2708. /* gfx_v9_0_enter_rlc_safe_mode(adev); */
  2709. if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
  2710. gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
  2711. else
  2712. gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
  2713. if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
  2714. gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
  2715. else
  2716. gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
  2717. /* gfx_v9_0_exit_rlc_safe_mode(adev); */
  2718. }
  2719. static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
  2720. bool enable)
  2721. {
  2722. uint32_t data, def;
  2723. /* It is disabled by HW by default */
  2724. if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
  2725. /* 1 - RLC_CGTT_MGCG_OVERRIDE */
  2726. def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
  2727. data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
  2728. RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
  2729. RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
  2730. RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
  2731. /* only for Vega10 & Raven1 */
  2732. data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
  2733. if (def != data)
  2734. WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
  2735. /* MGLS is a global flag to control all MGLS in GFX */
  2736. if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
  2737. /* 2 - RLC memory Light sleep */
  2738. if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
  2739. def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
  2740. data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
  2741. if (def != data)
  2742. WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
  2743. }
  2744. /* 3 - CP memory Light sleep */
  2745. if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
  2746. def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
  2747. data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
  2748. if (def != data)
  2749. WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
  2750. }
  2751. }
  2752. } else {
  2753. /* 1 - MGCG_OVERRIDE */
  2754. def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
  2755. data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
  2756. RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
  2757. RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
  2758. RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
  2759. RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
  2760. if (def != data)
  2761. WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
  2762. /* 2 - disable MGLS in RLC */
  2763. data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
  2764. if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
  2765. data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
  2766. WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
  2767. }
  2768. /* 3 - disable MGLS in CP */
  2769. data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
  2770. if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
  2771. data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
  2772. WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
  2773. }
  2774. }
  2775. }
  2776. static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
  2777. bool enable)
  2778. {
  2779. uint32_t data, def;
  2780. adev->gfx.rlc.funcs->enter_safe_mode(adev);
  2781. /* Enable 3D CGCG/CGLS */
  2782. if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
  2783. /* write cmd to clear cgcg/cgls ov */
  2784. def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
  2785. /* unset CGCG override */
  2786. data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
  2787. /* update CGCG and CGLS override bits */
  2788. if (def != data)
  2789. WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
  2790. /* enable 3Dcgcg FSM(0x0020003f) */
  2791. def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
  2792. data = (0x2000 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
  2793. RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
  2794. if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
  2795. data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
  2796. RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
  2797. if (def != data)
  2798. WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
  2799. /* set IDLE_POLL_COUNT(0x00900100) */
  2800. def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
  2801. data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
  2802. (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
  2803. if (def != data)
  2804. WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
  2805. } else {
  2806. /* Disable CGCG/CGLS */
  2807. def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
  2808. /* disable cgcg, cgls should be disabled */
  2809. data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
  2810. RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
  2811. /* disable cgcg and cgls in FSM */
  2812. if (def != data)
  2813. WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
  2814. }
  2815. adev->gfx.rlc.funcs->exit_safe_mode(adev);
  2816. }
  2817. static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
  2818. bool enable)
  2819. {
  2820. uint32_t def, data;
  2821. adev->gfx.rlc.funcs->enter_safe_mode(adev);
  2822. if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
  2823. def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
  2824. /* unset CGCG override */
  2825. data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
  2826. if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
  2827. data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
  2828. else
  2829. data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
  2830. /* update CGCG and CGLS override bits */
  2831. if (def != data)
  2832. WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
  2833. /* enable cgcg FSM(0x0020003F) */
  2834. def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
  2835. data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
  2836. RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
  2837. if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
  2838. data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
  2839. RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
  2840. if (def != data)
  2841. WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
  2842. /* set IDLE_POLL_COUNT(0x00900100) */
  2843. def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
  2844. data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
  2845. (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
  2846. if (def != data)
  2847. WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
  2848. } else {
  2849. def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
  2850. /* reset CGCG/CGLS bits */
  2851. data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
  2852. /* disable cgcg and cgls in FSM */
  2853. if (def != data)
  2854. WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
  2855. }
  2856. adev->gfx.rlc.funcs->exit_safe_mode(adev);
  2857. }
  2858. static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
  2859. bool enable)
  2860. {
  2861. if (enable) {
  2862. /* CGCG/CGLS should be enabled after MGCG/MGLS
  2863. * === MGCG + MGLS ===
  2864. */
  2865. gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
  2866. /* === CGCG /CGLS for GFX 3D Only === */
  2867. gfx_v9_0_update_3d_clock_gating(adev, enable);
  2868. /* === CGCG + CGLS === */
  2869. gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
  2870. } else {
  2871. /* CGCG/CGLS should be disabled before MGCG/MGLS
  2872. * === CGCG + CGLS ===
  2873. */
  2874. gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
  2875. /* === CGCG /CGLS for GFX 3D Only === */
  2876. gfx_v9_0_update_3d_clock_gating(adev, enable);
  2877. /* === MGCG + MGLS === */
  2878. gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
  2879. }
  2880. return 0;
  2881. }
  2882. static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
  2883. .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
  2884. .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
  2885. };
  2886. static int gfx_v9_0_set_powergating_state(void *handle,
  2887. enum amd_powergating_state state)
  2888. {
  2889. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2890. bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
  2891. switch (adev->asic_type) {
  2892. case CHIP_RAVEN:
  2893. if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
  2894. gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
  2895. gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
  2896. } else {
  2897. gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
  2898. gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
  2899. }
  2900. if (adev->pg_flags & AMD_PG_SUPPORT_CP)
  2901. gfx_v9_0_enable_cp_power_gating(adev, true);
  2902. else
  2903. gfx_v9_0_enable_cp_power_gating(adev, false);
  2904. /* update gfx cgpg state */
  2905. gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
  2906. /* update mgcg state */
  2907. gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
  2908. break;
  2909. default:
  2910. break;
  2911. }
  2912. return 0;
  2913. }
  2914. static int gfx_v9_0_set_clockgating_state(void *handle,
  2915. enum amd_clockgating_state state)
  2916. {
  2917. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2918. if (amdgpu_sriov_vf(adev))
  2919. return 0;
  2920. switch (adev->asic_type) {
  2921. case CHIP_VEGA10:
  2922. case CHIP_RAVEN:
  2923. gfx_v9_0_update_gfx_clock_gating(adev,
  2924. state == AMD_CG_STATE_GATE ? true : false);
  2925. break;
  2926. default:
  2927. break;
  2928. }
  2929. return 0;
  2930. }
  2931. static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
  2932. {
  2933. struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  2934. int data;
  2935. if (amdgpu_sriov_vf(adev))
  2936. *flags = 0;
  2937. /* AMD_CG_SUPPORT_GFX_MGCG */
  2938. data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
  2939. if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
  2940. *flags |= AMD_CG_SUPPORT_GFX_MGCG;
  2941. /* AMD_CG_SUPPORT_GFX_CGCG */
  2942. data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
  2943. if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
  2944. *flags |= AMD_CG_SUPPORT_GFX_CGCG;
  2945. /* AMD_CG_SUPPORT_GFX_CGLS */
  2946. if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
  2947. *flags |= AMD_CG_SUPPORT_GFX_CGLS;
  2948. /* AMD_CG_SUPPORT_GFX_RLC_LS */
  2949. data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
  2950. if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
  2951. *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
  2952. /* AMD_CG_SUPPORT_GFX_CP_LS */
  2953. data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
  2954. if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
  2955. *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
  2956. /* AMD_CG_SUPPORT_GFX_3D_CGCG */
  2957. data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
  2958. if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
  2959. *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
  2960. /* AMD_CG_SUPPORT_GFX_3D_CGLS */
  2961. if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
  2962. *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
  2963. }
  2964. static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
  2965. {
  2966. return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
  2967. }
  2968. static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
  2969. {
  2970. struct amdgpu_device *adev = ring->adev;
  2971. u64 wptr;
  2972. /* XXX check if swapping is necessary on BE */
  2973. if (ring->use_doorbell) {
  2974. wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
  2975. } else {
  2976. wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
  2977. wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
  2978. }
  2979. return wptr;
  2980. }
  2981. static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
  2982. {
  2983. struct amdgpu_device *adev = ring->adev;
  2984. if (ring->use_doorbell) {
  2985. /* XXX check if swapping is necessary on BE */
  2986. atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
  2987. WDOORBELL64(ring->doorbell_index, ring->wptr);
  2988. } else {
  2989. WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
  2990. WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
  2991. }
  2992. }
  2993. static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
  2994. {
  2995. u32 ref_and_mask, reg_mem_engine;
  2996. struct nbio_hdp_flush_reg *nbio_hf_reg;
  2997. if (ring->adev->asic_type == CHIP_VEGA10)
  2998. nbio_hf_reg = &nbio_v6_1_hdp_flush_reg;
  2999. if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
  3000. switch (ring->me) {
  3001. case 1:
  3002. ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
  3003. break;
  3004. case 2:
  3005. ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
  3006. break;
  3007. default:
  3008. return;
  3009. }
  3010. reg_mem_engine = 0;
  3011. } else {
  3012. ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
  3013. reg_mem_engine = 1; /* pfp */
  3014. }
  3015. gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
  3016. nbio_hf_reg->hdp_flush_req_offset,
  3017. nbio_hf_reg->hdp_flush_done_offset,
  3018. ref_and_mask, ref_and_mask, 0x20);
  3019. }
  3020. static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
  3021. {
  3022. gfx_v9_0_write_data_to_reg(ring, 0, true,
  3023. SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 1);
  3024. }
  3025. static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
  3026. struct amdgpu_ib *ib,
  3027. unsigned vm_id, bool ctx_switch)
  3028. {
  3029. u32 header, control = 0;
  3030. if (ib->flags & AMDGPU_IB_FLAG_CE)
  3031. header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
  3032. else
  3033. header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
  3034. control |= ib->length_dw | (vm_id << 24);
  3035. if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
  3036. control |= INDIRECT_BUFFER_PRE_ENB(1);
  3037. if (!(ib->flags & AMDGPU_IB_FLAG_CE))
  3038. gfx_v9_0_ring_emit_de_meta(ring);
  3039. }
  3040. amdgpu_ring_write(ring, header);
  3041. BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
  3042. amdgpu_ring_write(ring,
  3043. #ifdef __BIG_ENDIAN
  3044. (2 << 0) |
  3045. #endif
  3046. lower_32_bits(ib->gpu_addr));
  3047. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
  3048. amdgpu_ring_write(ring, control);
  3049. }
  3050. static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
  3051. struct amdgpu_ib *ib,
  3052. unsigned vm_id, bool ctx_switch)
  3053. {
  3054. u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
  3055. amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
  3056. BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
  3057. amdgpu_ring_write(ring,
  3058. #ifdef __BIG_ENDIAN
  3059. (2 << 0) |
  3060. #endif
  3061. lower_32_bits(ib->gpu_addr));
  3062. amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
  3063. amdgpu_ring_write(ring, control);
  3064. }
  3065. static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
  3066. u64 seq, unsigned flags)
  3067. {
  3068. bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
  3069. bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
  3070. /* RELEASE_MEM - flush caches, send int */
  3071. amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
  3072. amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
  3073. EOP_TC_ACTION_EN |
  3074. EOP_TC_WB_ACTION_EN |
  3075. EOP_TC_MD_ACTION_EN |
  3076. EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
  3077. EVENT_INDEX(5)));
  3078. amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
  3079. /*
  3080. * the address should be Qword aligned if 64bit write, Dword
  3081. * aligned if only send 32bit data low (discard data high)
  3082. */
  3083. if (write64bit)
  3084. BUG_ON(addr & 0x7);
  3085. else
  3086. BUG_ON(addr & 0x3);
  3087. amdgpu_ring_write(ring, lower_32_bits(addr));
  3088. amdgpu_ring_write(ring, upper_32_bits(addr));
  3089. amdgpu_ring_write(ring, lower_32_bits(seq));
  3090. amdgpu_ring_write(ring, upper_32_bits(seq));
  3091. amdgpu_ring_write(ring, 0);
  3092. }
  3093. static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  3094. {
  3095. int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
  3096. uint32_t seq = ring->fence_drv.sync_seq;
  3097. uint64_t addr = ring->fence_drv.gpu_addr;
  3098. gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
  3099. lower_32_bits(addr), upper_32_bits(addr),
  3100. seq, 0xffffffff, 4);
  3101. }
  3102. static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
  3103. unsigned vm_id, uint64_t pd_addr)
  3104. {
  3105. struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
  3106. int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
  3107. uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
  3108. unsigned eng = ring->vm_inv_eng;
  3109. pd_addr = amdgpu_gart_get_vm_pde(ring->adev, pd_addr);
  3110. pd_addr |= AMDGPU_PTE_VALID;
  3111. gfx_v9_0_write_data_to_reg(ring, usepfp, true,
  3112. hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
  3113. lower_32_bits(pd_addr));
  3114. gfx_v9_0_write_data_to_reg(ring, usepfp, true,
  3115. hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
  3116. upper_32_bits(pd_addr));
  3117. gfx_v9_0_write_data_to_reg(ring, usepfp, true,
  3118. hub->vm_inv_eng0_req + eng, req);
  3119. /* wait for the invalidate to complete */
  3120. gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
  3121. eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
  3122. /* compute doesn't have PFP */
  3123. if (usepfp) {
  3124. /* sync PFP to ME, otherwise we might get invalid PFP reads */
  3125. amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
  3126. amdgpu_ring_write(ring, 0x0);
  3127. }
  3128. }
  3129. static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
  3130. {
  3131. return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
  3132. }
  3133. static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
  3134. {
  3135. u64 wptr;
  3136. /* XXX check if swapping is necessary on BE */
  3137. if (ring->use_doorbell)
  3138. wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
  3139. else
  3140. BUG();
  3141. return wptr;
  3142. }
  3143. static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
  3144. {
  3145. struct amdgpu_device *adev = ring->adev;
  3146. /* XXX check if swapping is necessary on BE */
  3147. if (ring->use_doorbell) {
  3148. atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
  3149. WDOORBELL64(ring->doorbell_index, ring->wptr);
  3150. } else{
  3151. BUG(); /* only DOORBELL method supported on gfx9 now */
  3152. }
  3153. }
  3154. static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
  3155. u64 seq, unsigned int flags)
  3156. {
  3157. /* we only allocate 32bit for each seq wb address */
  3158. BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
  3159. /* write fence seq to the "addr" */
  3160. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3161. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3162. WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
  3163. amdgpu_ring_write(ring, lower_32_bits(addr));
  3164. amdgpu_ring_write(ring, upper_32_bits(addr));
  3165. amdgpu_ring_write(ring, lower_32_bits(seq));
  3166. if (flags & AMDGPU_FENCE_FLAG_INT) {
  3167. /* set register to trigger INT */
  3168. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3169. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
  3170. WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
  3171. amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
  3172. amdgpu_ring_write(ring, 0);
  3173. amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
  3174. }
  3175. }
  3176. static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
  3177. {
  3178. amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
  3179. amdgpu_ring_write(ring, 0);
  3180. }
  3181. static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
  3182. {
  3183. static struct v9_ce_ib_state ce_payload = {0};
  3184. uint64_t csa_addr;
  3185. int cnt;
  3186. cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
  3187. csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
  3188. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
  3189. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
  3190. WRITE_DATA_DST_SEL(8) |
  3191. WR_CONFIRM) |
  3192. WRITE_DATA_CACHE_POLICY(0));
  3193. amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
  3194. amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
  3195. amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
  3196. }
  3197. static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
  3198. {
  3199. static struct v9_de_ib_state de_payload = {0};
  3200. uint64_t csa_addr, gds_addr;
  3201. int cnt;
  3202. csa_addr = AMDGPU_VA_RESERVED_SIZE - 2 * 4096;
  3203. gds_addr = csa_addr + 4096;
  3204. de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
  3205. de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
  3206. cnt = (sizeof(de_payload) >> 2) + 4 - 2;
  3207. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
  3208. amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
  3209. WRITE_DATA_DST_SEL(8) |
  3210. WR_CONFIRM) |
  3211. WRITE_DATA_CACHE_POLICY(0));
  3212. amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
  3213. amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
  3214. amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
  3215. }
  3216. static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
  3217. {
  3218. uint32_t dw2 = 0;
  3219. if (amdgpu_sriov_vf(ring->adev))
  3220. gfx_v9_0_ring_emit_ce_meta(ring);
  3221. dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
  3222. if (flags & AMDGPU_HAVE_CTX_SWITCH) {
  3223. /* set load_global_config & load_global_uconfig */
  3224. dw2 |= 0x8001;
  3225. /* set load_cs_sh_regs */
  3226. dw2 |= 0x01000000;
  3227. /* set load_per_context_state & load_gfx_sh_regs for GFX */
  3228. dw2 |= 0x10002;
  3229. /* set load_ce_ram if preamble presented */
  3230. if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
  3231. dw2 |= 0x10000000;
  3232. } else {
  3233. /* still load_ce_ram if this is the first time preamble presented
  3234. * although there is no context switch happens.
  3235. */
  3236. if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
  3237. dw2 |= 0x10000000;
  3238. }
  3239. amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
  3240. amdgpu_ring_write(ring, dw2);
  3241. amdgpu_ring_write(ring, 0);
  3242. }
  3243. static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
  3244. {
  3245. unsigned ret;
  3246. amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
  3247. amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
  3248. amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
  3249. amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
  3250. ret = ring->wptr & ring->buf_mask;
  3251. amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
  3252. return ret;
  3253. }
  3254. static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
  3255. {
  3256. unsigned cur;
  3257. BUG_ON(offset > ring->buf_mask);
  3258. BUG_ON(ring->ring[offset] != 0x55aa55aa);
  3259. cur = (ring->wptr & ring->buf_mask) - 1;
  3260. if (likely(cur > offset))
  3261. ring->ring[offset] = cur - offset;
  3262. else
  3263. ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
  3264. }
  3265. static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
  3266. {
  3267. amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
  3268. amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
  3269. }
  3270. static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
  3271. {
  3272. struct amdgpu_device *adev = ring->adev;
  3273. amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
  3274. amdgpu_ring_write(ring, 0 | /* src: register*/
  3275. (5 << 8) | /* dst: memory */
  3276. (1 << 20)); /* write confirm */
  3277. amdgpu_ring_write(ring, reg);
  3278. amdgpu_ring_write(ring, 0);
  3279. amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
  3280. adev->virt.reg_val_offs * 4));
  3281. amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
  3282. adev->virt.reg_val_offs * 4));
  3283. }
  3284. static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
  3285. uint32_t val)
  3286. {
  3287. amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
  3288. amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
  3289. amdgpu_ring_write(ring, reg);
  3290. amdgpu_ring_write(ring, 0);
  3291. amdgpu_ring_write(ring, val);
  3292. }
  3293. static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
  3294. enum amdgpu_interrupt_state state)
  3295. {
  3296. switch (state) {
  3297. case AMDGPU_IRQ_STATE_DISABLE:
  3298. case AMDGPU_IRQ_STATE_ENABLE:
  3299. WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
  3300. TIME_STAMP_INT_ENABLE,
  3301. state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
  3302. break;
  3303. default:
  3304. break;
  3305. }
  3306. }
  3307. static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
  3308. int me, int pipe,
  3309. enum amdgpu_interrupt_state state)
  3310. {
  3311. u32 mec_int_cntl, mec_int_cntl_reg;
  3312. /*
  3313. * amdgpu controls only the first MEC. That's why this function only
  3314. * handles the setting of interrupts for this specific MEC. All other
  3315. * pipes' interrupts are set by amdkfd.
  3316. */
  3317. if (me == 1) {
  3318. switch (pipe) {
  3319. case 0:
  3320. mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
  3321. break;
  3322. case 1:
  3323. mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
  3324. break;
  3325. case 2:
  3326. mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
  3327. break;
  3328. case 3:
  3329. mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
  3330. break;
  3331. default:
  3332. DRM_DEBUG("invalid pipe %d\n", pipe);
  3333. return;
  3334. }
  3335. } else {
  3336. DRM_DEBUG("invalid me %d\n", me);
  3337. return;
  3338. }
  3339. switch (state) {
  3340. case AMDGPU_IRQ_STATE_DISABLE:
  3341. mec_int_cntl = RREG32(mec_int_cntl_reg);
  3342. mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
  3343. TIME_STAMP_INT_ENABLE, 0);
  3344. WREG32(mec_int_cntl_reg, mec_int_cntl);
  3345. break;
  3346. case AMDGPU_IRQ_STATE_ENABLE:
  3347. mec_int_cntl = RREG32(mec_int_cntl_reg);
  3348. mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
  3349. TIME_STAMP_INT_ENABLE, 1);
  3350. WREG32(mec_int_cntl_reg, mec_int_cntl);
  3351. break;
  3352. default:
  3353. break;
  3354. }
  3355. }
  3356. static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
  3357. struct amdgpu_irq_src *source,
  3358. unsigned type,
  3359. enum amdgpu_interrupt_state state)
  3360. {
  3361. switch (state) {
  3362. case AMDGPU_IRQ_STATE_DISABLE:
  3363. case AMDGPU_IRQ_STATE_ENABLE:
  3364. WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
  3365. PRIV_REG_INT_ENABLE,
  3366. state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
  3367. break;
  3368. default:
  3369. break;
  3370. }
  3371. return 0;
  3372. }
  3373. static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
  3374. struct amdgpu_irq_src *source,
  3375. unsigned type,
  3376. enum amdgpu_interrupt_state state)
  3377. {
  3378. switch (state) {
  3379. case AMDGPU_IRQ_STATE_DISABLE:
  3380. case AMDGPU_IRQ_STATE_ENABLE:
  3381. WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
  3382. PRIV_INSTR_INT_ENABLE,
  3383. state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
  3384. default:
  3385. break;
  3386. }
  3387. return 0;
  3388. }
  3389. static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
  3390. struct amdgpu_irq_src *src,
  3391. unsigned type,
  3392. enum amdgpu_interrupt_state state)
  3393. {
  3394. switch (type) {
  3395. case AMDGPU_CP_IRQ_GFX_EOP:
  3396. gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
  3397. break;
  3398. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
  3399. gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
  3400. break;
  3401. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
  3402. gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
  3403. break;
  3404. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
  3405. gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
  3406. break;
  3407. case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
  3408. gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
  3409. break;
  3410. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
  3411. gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
  3412. break;
  3413. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
  3414. gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
  3415. break;
  3416. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
  3417. gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
  3418. break;
  3419. case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
  3420. gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
  3421. break;
  3422. default:
  3423. break;
  3424. }
  3425. return 0;
  3426. }
  3427. static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
  3428. struct amdgpu_irq_src *source,
  3429. struct amdgpu_iv_entry *entry)
  3430. {
  3431. int i;
  3432. u8 me_id, pipe_id, queue_id;
  3433. struct amdgpu_ring *ring;
  3434. DRM_DEBUG("IH: CP EOP\n");
  3435. me_id = (entry->ring_id & 0x0c) >> 2;
  3436. pipe_id = (entry->ring_id & 0x03) >> 0;
  3437. queue_id = (entry->ring_id & 0x70) >> 4;
  3438. switch (me_id) {
  3439. case 0:
  3440. amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
  3441. break;
  3442. case 1:
  3443. case 2:
  3444. for (i = 0; i < adev->gfx.num_compute_rings; i++) {
  3445. ring = &adev->gfx.compute_ring[i];
  3446. /* Per-queue interrupt is supported for MEC starting from VI.
  3447. * The interrupt can only be enabled/disabled per pipe instead of per queue.
  3448. */
  3449. if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
  3450. amdgpu_fence_process(ring);
  3451. }
  3452. break;
  3453. }
  3454. return 0;
  3455. }
  3456. static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
  3457. struct amdgpu_irq_src *source,
  3458. struct amdgpu_iv_entry *entry)
  3459. {
  3460. DRM_ERROR("Illegal register access in command stream\n");
  3461. schedule_work(&adev->reset_work);
  3462. return 0;
  3463. }
  3464. static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
  3465. struct amdgpu_irq_src *source,
  3466. struct amdgpu_iv_entry *entry)
  3467. {
  3468. DRM_ERROR("Illegal instruction in command stream\n");
  3469. schedule_work(&adev->reset_work);
  3470. return 0;
  3471. }
  3472. static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
  3473. struct amdgpu_irq_src *src,
  3474. unsigned int type,
  3475. enum amdgpu_interrupt_state state)
  3476. {
  3477. uint32_t tmp, target;
  3478. struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
  3479. if (ring->me == 1)
  3480. target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
  3481. else
  3482. target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
  3483. target += ring->pipe;
  3484. switch (type) {
  3485. case AMDGPU_CP_KIQ_IRQ_DRIVER0:
  3486. if (state == AMDGPU_IRQ_STATE_DISABLE) {
  3487. tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
  3488. tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
  3489. GENERIC2_INT_ENABLE, 0);
  3490. WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
  3491. tmp = RREG32(target);
  3492. tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
  3493. GENERIC2_INT_ENABLE, 0);
  3494. WREG32(target, tmp);
  3495. } else {
  3496. tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
  3497. tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
  3498. GENERIC2_INT_ENABLE, 1);
  3499. WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
  3500. tmp = RREG32(target);
  3501. tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
  3502. GENERIC2_INT_ENABLE, 1);
  3503. WREG32(target, tmp);
  3504. }
  3505. break;
  3506. default:
  3507. BUG(); /* kiq only support GENERIC2_INT now */
  3508. break;
  3509. }
  3510. return 0;
  3511. }
  3512. static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
  3513. struct amdgpu_irq_src *source,
  3514. struct amdgpu_iv_entry *entry)
  3515. {
  3516. u8 me_id, pipe_id, queue_id;
  3517. struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
  3518. me_id = (entry->ring_id & 0x0c) >> 2;
  3519. pipe_id = (entry->ring_id & 0x03) >> 0;
  3520. queue_id = (entry->ring_id & 0x70) >> 4;
  3521. DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
  3522. me_id, pipe_id, queue_id);
  3523. amdgpu_fence_process(ring);
  3524. return 0;
  3525. }
  3526. const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
  3527. .name = "gfx_v9_0",
  3528. .early_init = gfx_v9_0_early_init,
  3529. .late_init = gfx_v9_0_late_init,
  3530. .sw_init = gfx_v9_0_sw_init,
  3531. .sw_fini = gfx_v9_0_sw_fini,
  3532. .hw_init = gfx_v9_0_hw_init,
  3533. .hw_fini = gfx_v9_0_hw_fini,
  3534. .suspend = gfx_v9_0_suspend,
  3535. .resume = gfx_v9_0_resume,
  3536. .is_idle = gfx_v9_0_is_idle,
  3537. .wait_for_idle = gfx_v9_0_wait_for_idle,
  3538. .soft_reset = gfx_v9_0_soft_reset,
  3539. .set_clockgating_state = gfx_v9_0_set_clockgating_state,
  3540. .set_powergating_state = gfx_v9_0_set_powergating_state,
  3541. .get_clockgating_state = gfx_v9_0_get_clockgating_state,
  3542. };
  3543. static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
  3544. .type = AMDGPU_RING_TYPE_GFX,
  3545. .align_mask = 0xff,
  3546. .nop = PACKET3(PACKET3_NOP, 0x3FFF),
  3547. .support_64bit_ptrs = true,
  3548. .vmhub = AMDGPU_GFXHUB,
  3549. .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
  3550. .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
  3551. .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
  3552. .emit_frame_size = /* totally 242 maximum if 16 IBs */
  3553. 5 + /* COND_EXEC */
  3554. 7 + /* PIPELINE_SYNC */
  3555. 24 + /* VM_FLUSH */
  3556. 8 + /* FENCE for VM_FLUSH */
  3557. 20 + /* GDS switch */
  3558. 4 + /* double SWITCH_BUFFER,
  3559. the first COND_EXEC jump to the place just
  3560. prior to this double SWITCH_BUFFER */
  3561. 5 + /* COND_EXEC */
  3562. 7 + /* HDP_flush */
  3563. 4 + /* VGT_flush */
  3564. 14 + /* CE_META */
  3565. 31 + /* DE_META */
  3566. 3 + /* CNTX_CTRL */
  3567. 5 + /* HDP_INVL */
  3568. 8 + 8 + /* FENCE x2 */
  3569. 2, /* SWITCH_BUFFER */
  3570. .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
  3571. .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
  3572. .emit_fence = gfx_v9_0_ring_emit_fence,
  3573. .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
  3574. .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
  3575. .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
  3576. .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
  3577. .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
  3578. .test_ring = gfx_v9_0_ring_test_ring,
  3579. .test_ib = gfx_v9_0_ring_test_ib,
  3580. .insert_nop = amdgpu_ring_insert_nop,
  3581. .pad_ib = amdgpu_ring_generic_pad_ib,
  3582. .emit_switch_buffer = gfx_v9_ring_emit_sb,
  3583. .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
  3584. .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
  3585. .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
  3586. .emit_tmz = gfx_v9_0_ring_emit_tmz,
  3587. };
  3588. static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
  3589. .type = AMDGPU_RING_TYPE_COMPUTE,
  3590. .align_mask = 0xff,
  3591. .nop = PACKET3(PACKET3_NOP, 0x3FFF),
  3592. .support_64bit_ptrs = true,
  3593. .vmhub = AMDGPU_GFXHUB,
  3594. .get_rptr = gfx_v9_0_ring_get_rptr_compute,
  3595. .get_wptr = gfx_v9_0_ring_get_wptr_compute,
  3596. .set_wptr = gfx_v9_0_ring_set_wptr_compute,
  3597. .emit_frame_size =
  3598. 20 + /* gfx_v9_0_ring_emit_gds_switch */
  3599. 7 + /* gfx_v9_0_ring_emit_hdp_flush */
  3600. 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
  3601. 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
  3602. 24 + /* gfx_v9_0_ring_emit_vm_flush */
  3603. 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
  3604. .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
  3605. .emit_ib = gfx_v9_0_ring_emit_ib_compute,
  3606. .emit_fence = gfx_v9_0_ring_emit_fence,
  3607. .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
  3608. .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
  3609. .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
  3610. .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
  3611. .emit_hdp_invalidate = gfx_v9_0_ring_emit_hdp_invalidate,
  3612. .test_ring = gfx_v9_0_ring_test_ring,
  3613. .test_ib = gfx_v9_0_ring_test_ib,
  3614. .insert_nop = amdgpu_ring_insert_nop,
  3615. .pad_ib = amdgpu_ring_generic_pad_ib,
  3616. };
  3617. static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
  3618. .type = AMDGPU_RING_TYPE_KIQ,
  3619. .align_mask = 0xff,
  3620. .nop = PACKET3(PACKET3_NOP, 0x3FFF),
  3621. .support_64bit_ptrs = true,
  3622. .vmhub = AMDGPU_GFXHUB,
  3623. .get_rptr = gfx_v9_0_ring_get_rptr_compute,
  3624. .get_wptr = gfx_v9_0_ring_get_wptr_compute,
  3625. .set_wptr = gfx_v9_0_ring_set_wptr_compute,
  3626. .emit_frame_size =
  3627. 20 + /* gfx_v9_0_ring_emit_gds_switch */
  3628. 7 + /* gfx_v9_0_ring_emit_hdp_flush */
  3629. 5 + /* gfx_v9_0_ring_emit_hdp_invalidate */
  3630. 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
  3631. 24 + /* gfx_v9_0_ring_emit_vm_flush */
  3632. 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
  3633. .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
  3634. .emit_ib = gfx_v9_0_ring_emit_ib_compute,
  3635. .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
  3636. .test_ring = gfx_v9_0_ring_test_ring,
  3637. .test_ib = gfx_v9_0_ring_test_ib,
  3638. .insert_nop = amdgpu_ring_insert_nop,
  3639. .pad_ib = amdgpu_ring_generic_pad_ib,
  3640. .emit_rreg = gfx_v9_0_ring_emit_rreg,
  3641. .emit_wreg = gfx_v9_0_ring_emit_wreg,
  3642. };
  3643. static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
  3644. {
  3645. int i;
  3646. adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
  3647. for (i = 0; i < adev->gfx.num_gfx_rings; i++)
  3648. adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
  3649. for (i = 0; i < adev->gfx.num_compute_rings; i++)
  3650. adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
  3651. }
  3652. static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
  3653. .set = gfx_v9_0_kiq_set_interrupt_state,
  3654. .process = gfx_v9_0_kiq_irq,
  3655. };
  3656. static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
  3657. .set = gfx_v9_0_set_eop_interrupt_state,
  3658. .process = gfx_v9_0_eop_irq,
  3659. };
  3660. static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
  3661. .set = gfx_v9_0_set_priv_reg_fault_state,
  3662. .process = gfx_v9_0_priv_reg_irq,
  3663. };
  3664. static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
  3665. .set = gfx_v9_0_set_priv_inst_fault_state,
  3666. .process = gfx_v9_0_priv_inst_irq,
  3667. };
  3668. static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
  3669. {
  3670. adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
  3671. adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
  3672. adev->gfx.priv_reg_irq.num_types = 1;
  3673. adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
  3674. adev->gfx.priv_inst_irq.num_types = 1;
  3675. adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
  3676. adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
  3677. adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
  3678. }
  3679. static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
  3680. {
  3681. switch (adev->asic_type) {
  3682. case CHIP_VEGA10:
  3683. case CHIP_RAVEN:
  3684. adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
  3685. break;
  3686. default:
  3687. break;
  3688. }
  3689. }
  3690. static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
  3691. {
  3692. /* init asci gds info */
  3693. adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
  3694. adev->gds.gws.total_size = 64;
  3695. adev->gds.oa.total_size = 16;
  3696. if (adev->gds.mem.total_size == 64 * 1024) {
  3697. adev->gds.mem.gfx_partition_size = 4096;
  3698. adev->gds.mem.cs_partition_size = 4096;
  3699. adev->gds.gws.gfx_partition_size = 4;
  3700. adev->gds.gws.cs_partition_size = 4;
  3701. adev->gds.oa.gfx_partition_size = 4;
  3702. adev->gds.oa.cs_partition_size = 1;
  3703. } else {
  3704. adev->gds.mem.gfx_partition_size = 1024;
  3705. adev->gds.mem.cs_partition_size = 1024;
  3706. adev->gds.gws.gfx_partition_size = 16;
  3707. adev->gds.gws.cs_partition_size = 16;
  3708. adev->gds.oa.gfx_partition_size = 4;
  3709. adev->gds.oa.cs_partition_size = 4;
  3710. }
  3711. }
  3712. static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
  3713. u32 bitmap)
  3714. {
  3715. u32 data;
  3716. if (!bitmap)
  3717. return;
  3718. data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
  3719. data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
  3720. WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
  3721. }
  3722. static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
  3723. {
  3724. u32 data, mask;
  3725. data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
  3726. data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
  3727. data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
  3728. data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
  3729. mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
  3730. return (~data) & mask;
  3731. }
  3732. static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
  3733. struct amdgpu_cu_info *cu_info)
  3734. {
  3735. int i, j, k, counter, active_cu_number = 0;
  3736. u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
  3737. unsigned disable_masks[4 * 2];
  3738. if (!adev || !cu_info)
  3739. return -EINVAL;
  3740. amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
  3741. mutex_lock(&adev->grbm_idx_mutex);
  3742. for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
  3743. for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
  3744. mask = 1;
  3745. ao_bitmap = 0;
  3746. counter = 0;
  3747. gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
  3748. if (i < 4 && j < 2)
  3749. gfx_v9_0_set_user_cu_inactive_bitmap(
  3750. adev, disable_masks[i * 2 + j]);
  3751. bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
  3752. cu_info->bitmap[i][j] = bitmap;
  3753. for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
  3754. if (bitmap & mask) {
  3755. if (counter < adev->gfx.config.max_cu_per_sh)
  3756. ao_bitmap |= mask;
  3757. counter ++;
  3758. }
  3759. mask <<= 1;
  3760. }
  3761. active_cu_number += counter;
  3762. if (i < 2 && j < 2)
  3763. ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
  3764. cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
  3765. }
  3766. }
  3767. gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
  3768. mutex_unlock(&adev->grbm_idx_mutex);
  3769. cu_info->number = active_cu_number;
  3770. cu_info->ao_cu_mask = ao_cu_mask;
  3771. return 0;
  3772. }
  3773. const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
  3774. {
  3775. .type = AMD_IP_BLOCK_TYPE_GFX,
  3776. .major = 9,
  3777. .minor = 0,
  3778. .rev = 0,
  3779. .funcs = &gfx_v9_0_ip_funcs,
  3780. };