skl.c 12 KB

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  1. /*
  2. * skl.c - Implementation of ASoC Intel SKL HD Audio driver
  3. *
  4. * Copyright (C) 2014-2015 Intel Corp
  5. * Author: Jeeja KP <jeeja.kp@intel.com>
  6. *
  7. * Derived mostly from Intel HDA driver with following copyrights:
  8. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  9. * PeiSen Hou <pshou@realtek.com.tw>
  10. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; version 2 of the License.
  15. *
  16. * This program is distributed in the hope that it will be useful, but
  17. * WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  22. */
  23. #include <linux/module.h>
  24. #include <linux/pci.h>
  25. #include <linux/pm_runtime.h>
  26. #include <linux/platform_device.h>
  27. #include <sound/pcm.h>
  28. #include "skl.h"
  29. /*
  30. * initialize the PCI registers
  31. */
  32. static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
  33. unsigned char mask, unsigned char val)
  34. {
  35. unsigned char data;
  36. pci_read_config_byte(pci, reg, &data);
  37. data &= ~mask;
  38. data |= (val & mask);
  39. pci_write_config_byte(pci, reg, data);
  40. }
  41. static void skl_init_pci(struct skl *skl)
  42. {
  43. struct hdac_ext_bus *ebus = &skl->ebus;
  44. /*
  45. * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
  46. * TCSEL == Traffic Class Select Register, which sets PCI express QOS
  47. * Ensuring these bits are 0 clears playback static on some HD Audio
  48. * codecs.
  49. * The PCI register TCSEL is defined in the Intel manuals.
  50. */
  51. dev_dbg(ebus_to_hbus(ebus)->dev, "Clearing TCSEL\n");
  52. skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
  53. }
  54. /* called from IRQ */
  55. static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
  56. {
  57. snd_pcm_period_elapsed(hstr->substream);
  58. }
  59. static irqreturn_t skl_interrupt(int irq, void *dev_id)
  60. {
  61. struct hdac_ext_bus *ebus = dev_id;
  62. struct hdac_bus *bus = ebus_to_hbus(ebus);
  63. u32 status;
  64. if (!pm_runtime_active(bus->dev))
  65. return IRQ_NONE;
  66. spin_lock(&bus->reg_lock);
  67. status = snd_hdac_chip_readl(bus, INTSTS);
  68. if (status == 0 || status == 0xffffffff) {
  69. spin_unlock(&bus->reg_lock);
  70. return IRQ_NONE;
  71. }
  72. /* clear rirb int */
  73. status = snd_hdac_chip_readb(bus, RIRBSTS);
  74. if (status & RIRB_INT_MASK) {
  75. if (status & RIRB_INT_RESPONSE)
  76. snd_hdac_bus_update_rirb(bus);
  77. snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
  78. }
  79. spin_unlock(&bus->reg_lock);
  80. return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
  81. }
  82. static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
  83. {
  84. struct hdac_ext_bus *ebus = dev_id;
  85. struct hdac_bus *bus = ebus_to_hbus(ebus);
  86. u32 status;
  87. status = snd_hdac_chip_readl(bus, INTSTS);
  88. snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
  89. return IRQ_HANDLED;
  90. }
  91. static int skl_acquire_irq(struct hdac_ext_bus *ebus, int do_disconnect)
  92. {
  93. struct skl *skl = ebus_to_skl(ebus);
  94. struct hdac_bus *bus = ebus_to_hbus(ebus);
  95. int ret;
  96. ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
  97. skl_threaded_handler,
  98. IRQF_SHARED,
  99. KBUILD_MODNAME, ebus);
  100. if (ret) {
  101. dev_err(bus->dev,
  102. "unable to grab IRQ %d, disabling device\n",
  103. skl->pci->irq);
  104. return ret;
  105. }
  106. bus->irq = skl->pci->irq;
  107. pci_intx(skl->pci, 1);
  108. return 0;
  109. }
  110. #ifdef CONFIG_PM_SLEEP
  111. /*
  112. * power management
  113. */
  114. static int skl_suspend(struct device *dev)
  115. {
  116. struct pci_dev *pci = to_pci_dev(dev);
  117. struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
  118. struct hdac_bus *bus = ebus_to_hbus(ebus);
  119. snd_hdac_bus_stop_chip(bus);
  120. snd_hdac_bus_enter_link_reset(bus);
  121. return 0;
  122. }
  123. static int skl_resume(struct device *dev)
  124. {
  125. struct pci_dev *pci = to_pci_dev(dev);
  126. struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
  127. struct hdac_bus *bus = ebus_to_hbus(ebus);
  128. struct skl *hda = ebus_to_skl(ebus);
  129. skl_init_pci(hda);
  130. snd_hdac_bus_init_chip(bus, 1);
  131. return 0;
  132. }
  133. #endif /* CONFIG_PM_SLEEP */
  134. #ifdef CONFIG_PM
  135. static int skl_runtime_suspend(struct device *dev)
  136. {
  137. struct pci_dev *pci = to_pci_dev(dev);
  138. struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
  139. struct hdac_bus *bus = ebus_to_hbus(ebus);
  140. dev_dbg(bus->dev, "in %s\n", __func__);
  141. /* enable controller wake up event */
  142. snd_hdac_chip_updatew(bus, WAKEEN, 0, STATESTS_INT_MASK);
  143. snd_hdac_bus_stop_chip(bus);
  144. snd_hdac_bus_enter_link_reset(bus);
  145. return 0;
  146. }
  147. static int skl_runtime_resume(struct device *dev)
  148. {
  149. struct pci_dev *pci = to_pci_dev(dev);
  150. struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
  151. struct hdac_bus *bus = ebus_to_hbus(ebus);
  152. struct skl *hda = ebus_to_skl(ebus);
  153. int status;
  154. dev_dbg(bus->dev, "in %s\n", __func__);
  155. /* Read STATESTS before controller reset */
  156. status = snd_hdac_chip_readw(bus, STATESTS);
  157. skl_init_pci(hda);
  158. snd_hdac_bus_init_chip(bus, true);
  159. /* disable controller Wake Up event */
  160. snd_hdac_chip_updatew(bus, WAKEEN, STATESTS_INT_MASK, 0);
  161. return 0;
  162. }
  163. #endif /* CONFIG_PM */
  164. static const struct dev_pm_ops skl_pm = {
  165. SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
  166. SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
  167. };
  168. /*
  169. * destructor
  170. */
  171. static int skl_free(struct hdac_ext_bus *ebus)
  172. {
  173. struct skl *skl = ebus_to_skl(ebus);
  174. struct hdac_bus *bus = ebus_to_hbus(ebus);
  175. skl->init_failed = 1; /* to be sure */
  176. snd_hdac_ext_stop_streams(ebus);
  177. if (bus->irq >= 0)
  178. free_irq(bus->irq, (void *)bus);
  179. if (bus->remap_addr)
  180. iounmap(bus->remap_addr);
  181. snd_hdac_bus_free_stream_pages(bus);
  182. snd_hdac_stream_free_all(ebus);
  183. snd_hdac_link_free_all(ebus);
  184. pci_release_regions(skl->pci);
  185. pci_disable_device(skl->pci);
  186. snd_hdac_ext_bus_exit(ebus);
  187. return 0;
  188. }
  189. static int skl_dmic_device_register(struct skl *skl)
  190. {
  191. struct hdac_bus *bus = ebus_to_hbus(&skl->ebus);
  192. struct platform_device *pdev;
  193. int ret;
  194. /* SKL has one dmic port, so allocate dmic device for this */
  195. pdev = platform_device_alloc("dmic-codec", -1);
  196. if (!pdev) {
  197. dev_err(bus->dev, "failed to allocate dmic device\n");
  198. return -ENOMEM;
  199. }
  200. ret = platform_device_add(pdev);
  201. if (ret) {
  202. dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
  203. platform_device_put(pdev);
  204. return ret;
  205. }
  206. skl->dmic_dev = pdev;
  207. return 0;
  208. }
  209. static void skl_dmic_device_unregister(struct skl *skl)
  210. {
  211. if (skl->dmic_dev)
  212. platform_device_unregister(skl->dmic_dev);
  213. }
  214. /*
  215. * Probe the given codec address
  216. */
  217. static int probe_codec(struct hdac_ext_bus *ebus, int addr)
  218. {
  219. struct hdac_bus *bus = ebus_to_hbus(ebus);
  220. unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
  221. (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
  222. unsigned int res;
  223. mutex_lock(&bus->cmd_mutex);
  224. snd_hdac_bus_send_cmd(bus, cmd);
  225. snd_hdac_bus_get_response(bus, addr, &res);
  226. mutex_unlock(&bus->cmd_mutex);
  227. if (res == -1)
  228. return -EIO;
  229. dev_dbg(bus->dev, "codec #%d probed OK\n", addr);
  230. return snd_hdac_ext_bus_device_init(ebus, addr);
  231. }
  232. /* Codec initialization */
  233. static int skl_codec_create(struct hdac_ext_bus *ebus)
  234. {
  235. struct hdac_bus *bus = ebus_to_hbus(ebus);
  236. int c, max_slots;
  237. max_slots = HDA_MAX_CODECS;
  238. /* First try to probe all given codec slots */
  239. for (c = 0; c < max_slots; c++) {
  240. if ((bus->codec_mask & (1 << c))) {
  241. if (probe_codec(ebus, c) < 0) {
  242. /*
  243. * Some BIOSen give you wrong codec addresses
  244. * that don't exist
  245. */
  246. dev_warn(bus->dev,
  247. "Codec #%d probe error; disabling it...\n", c);
  248. bus->codec_mask &= ~(1 << c);
  249. /*
  250. * More badly, accessing to a non-existing
  251. * codec often screws up the controller bus,
  252. * and disturbs the further communications.
  253. * Thus if an error occurs during probing,
  254. * better to reset the controller bus to get
  255. * back to the sanity state.
  256. */
  257. snd_hdac_bus_stop_chip(bus);
  258. snd_hdac_bus_init_chip(bus, true);
  259. }
  260. }
  261. }
  262. return 0;
  263. }
  264. static const struct hdac_bus_ops bus_core_ops = {
  265. .command = snd_hdac_bus_send_cmd,
  266. .get_response = snd_hdac_bus_get_response,
  267. };
  268. /*
  269. * constructor
  270. */
  271. static int skl_create(struct pci_dev *pci,
  272. const struct hdac_io_ops *io_ops,
  273. struct skl **rskl)
  274. {
  275. struct skl *skl;
  276. struct hdac_ext_bus *ebus;
  277. int err;
  278. *rskl = NULL;
  279. err = pci_enable_device(pci);
  280. if (err < 0)
  281. return err;
  282. skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
  283. if (!skl) {
  284. pci_disable_device(pci);
  285. return -ENOMEM;
  286. }
  287. ebus = &skl->ebus;
  288. snd_hdac_ext_bus_init(ebus, &pci->dev, &bus_core_ops, io_ops);
  289. ebus->bus.use_posbuf = 1;
  290. skl->pci = pci;
  291. ebus->bus.bdl_pos_adj = 0;
  292. *rskl = skl;
  293. return 0;
  294. }
  295. static int skl_first_init(struct hdac_ext_bus *ebus)
  296. {
  297. struct skl *skl = ebus_to_skl(ebus);
  298. struct hdac_bus *bus = ebus_to_hbus(ebus);
  299. struct pci_dev *pci = skl->pci;
  300. int err;
  301. unsigned short gcap;
  302. int cp_streams, pb_streams, start_idx;
  303. err = pci_request_regions(pci, "Skylake HD audio");
  304. if (err < 0)
  305. return err;
  306. bus->addr = pci_resource_start(pci, 0);
  307. bus->remap_addr = pci_ioremap_bar(pci, 0);
  308. if (bus->remap_addr == NULL) {
  309. dev_err(bus->dev, "ioremap error\n");
  310. return -ENXIO;
  311. }
  312. snd_hdac_ext_bus_parse_capabilities(ebus);
  313. if (skl_acquire_irq(ebus, 0) < 0)
  314. return -EBUSY;
  315. pci_set_master(pci);
  316. synchronize_irq(bus->irq);
  317. gcap = snd_hdac_chip_readw(bus, GCAP);
  318. dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
  319. /* allow 64bit DMA address if supported by H/W */
  320. if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
  321. dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
  322. } else {
  323. dma_set_mask(bus->dev, DMA_BIT_MASK(32));
  324. dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
  325. }
  326. /* read number of streams from GCAP register */
  327. cp_streams = (gcap >> 8) & 0x0f;
  328. pb_streams = (gcap >> 12) & 0x0f;
  329. if (!pb_streams && !cp_streams)
  330. return -EIO;
  331. ebus->num_streams = cp_streams + pb_streams;
  332. /* initialize streams */
  333. snd_hdac_ext_stream_init_all
  334. (ebus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
  335. start_idx = cp_streams;
  336. snd_hdac_ext_stream_init_all
  337. (ebus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
  338. err = snd_hdac_bus_alloc_stream_pages(bus);
  339. if (err < 0)
  340. return err;
  341. /* initialize chip */
  342. skl_init_pci(skl);
  343. snd_hdac_bus_init_chip(bus, true);
  344. /* codec detection */
  345. if (!bus->codec_mask) {
  346. dev_err(bus->dev, "no codecs found!\n");
  347. return -ENODEV;
  348. }
  349. return 0;
  350. }
  351. static int skl_probe(struct pci_dev *pci,
  352. const struct pci_device_id *pci_id)
  353. {
  354. struct skl *skl;
  355. struct hdac_ext_bus *ebus = NULL;
  356. struct hdac_bus *bus = NULL;
  357. int err;
  358. /* we use ext core ops, so provide NULL for ops here */
  359. err = skl_create(pci, NULL, &skl);
  360. if (err < 0)
  361. return err;
  362. ebus = &skl->ebus;
  363. bus = ebus_to_hbus(ebus);
  364. err = skl_first_init(ebus);
  365. if (err < 0)
  366. goto out_free;
  367. pci_set_drvdata(skl->pci, ebus);
  368. /* check if dsp is there */
  369. if (ebus->ppcap) {
  370. /* TODO register with dsp IPC */
  371. dev_dbg(bus->dev, "Register dsp\n");
  372. }
  373. if (ebus->mlcap)
  374. snd_hdac_ext_bus_get_ml_capabilities(ebus);
  375. /* create device for soc dmic */
  376. err = skl_dmic_device_register(skl);
  377. if (err < 0)
  378. goto out_free;
  379. /* register platform dai and controls */
  380. err = skl_platform_register(bus->dev);
  381. if (err < 0)
  382. goto out_dmic_free;
  383. /* create codec instances */
  384. err = skl_codec_create(ebus);
  385. if (err < 0)
  386. goto out_unregister;
  387. /*configure PM */
  388. pm_runtime_set_autosuspend_delay(bus->dev, SKL_SUSPEND_DELAY);
  389. pm_runtime_use_autosuspend(bus->dev);
  390. pm_runtime_put_noidle(bus->dev);
  391. pm_runtime_allow(bus->dev);
  392. return 0;
  393. out_unregister:
  394. skl_platform_unregister(bus->dev);
  395. out_dmic_free:
  396. skl_dmic_device_unregister(skl);
  397. out_free:
  398. skl->init_failed = 1;
  399. skl_free(ebus);
  400. return err;
  401. }
  402. static void skl_remove(struct pci_dev *pci)
  403. {
  404. struct hdac_ext_bus *ebus = pci_get_drvdata(pci);
  405. struct skl *skl = ebus_to_skl(ebus);
  406. if (pci_dev_run_wake(pci))
  407. pm_runtime_get_noresume(&pci->dev);
  408. pci_dev_put(pci);
  409. skl_platform_unregister(&pci->dev);
  410. skl_dmic_device_unregister(skl);
  411. skl_free(ebus);
  412. dev_set_drvdata(&pci->dev, NULL);
  413. }
  414. /* PCI IDs */
  415. static const struct pci_device_id skl_ids[] = {
  416. /* Sunrise Point-LP */
  417. { PCI_DEVICE(0x8086, 0x9d70), 0},
  418. { 0, }
  419. };
  420. MODULE_DEVICE_TABLE(pci, skl_ids);
  421. /* pci_driver definition */
  422. static struct pci_driver skl_driver = {
  423. .name = KBUILD_MODNAME,
  424. .id_table = skl_ids,
  425. .probe = skl_probe,
  426. .remove = skl_remove,
  427. .driver = {
  428. .pm = &skl_pm,
  429. },
  430. };
  431. module_pci_driver(skl_driver);
  432. MODULE_LICENSE("GPL v2");
  433. MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");