hdmi5.c 17 KB

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  1. /*
  2. * HDMI driver for OMAP5
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. *
  6. * Authors:
  7. * Yong Zhi
  8. * Mythri pk
  9. * Archit Taneja <archit@ti.com>
  10. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License version 2 as published by
  14. * the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program. If not, see <http://www.gnu.org/licenses/>.
  23. */
  24. #define DSS_SUBSYS_NAME "HDMI"
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/err.h>
  28. #include <linux/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/string.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/clk.h>
  36. #include <linux/gpio.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/component.h>
  39. #include <video/omapdss.h>
  40. #include <sound/omap-hdmi-audio.h>
  41. #include "hdmi5_core.h"
  42. #include "dss.h"
  43. #include "dss_features.h"
  44. static struct omap_hdmi hdmi;
  45. static int hdmi_runtime_get(void)
  46. {
  47. int r;
  48. DSSDBG("hdmi_runtime_get\n");
  49. r = pm_runtime_get_sync(&hdmi.pdev->dev);
  50. WARN_ON(r < 0);
  51. if (r < 0)
  52. return r;
  53. return 0;
  54. }
  55. static void hdmi_runtime_put(void)
  56. {
  57. int r;
  58. DSSDBG("hdmi_runtime_put\n");
  59. r = pm_runtime_put_sync(&hdmi.pdev->dev);
  60. WARN_ON(r < 0 && r != -ENOSYS);
  61. }
  62. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  63. {
  64. struct hdmi_wp_data *wp = data;
  65. u32 irqstatus;
  66. irqstatus = hdmi_wp_get_irqstatus(wp);
  67. hdmi_wp_set_irqstatus(wp, irqstatus);
  68. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  69. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  70. u32 v;
  71. /*
  72. * If we get both connect and disconnect interrupts at the same
  73. * time, turn off the PHY, clear interrupts, and restart, which
  74. * raises connect interrupt if a cable is connected, or nothing
  75. * if cable is not connected.
  76. */
  77. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  78. /*
  79. * We always get bogus CONNECT & DISCONNECT interrupts when
  80. * setting the PHY to LDOON. To ignore those, we force the RXDET
  81. * line to 0 until the PHY power state has been changed.
  82. */
  83. v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  84. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  85. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  86. hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  87. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  88. HDMI_IRQ_LINK_DISCONNECT);
  89. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  90. REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  91. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  92. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  93. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  94. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  95. }
  96. return IRQ_HANDLED;
  97. }
  98. static int hdmi_init_regulator(void)
  99. {
  100. int r;
  101. struct regulator *reg;
  102. if (hdmi.vdda_reg != NULL)
  103. return 0;
  104. reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
  105. if (IS_ERR(reg)) {
  106. DSSERR("can't get VDDA regulator\n");
  107. return PTR_ERR(reg);
  108. }
  109. if (regulator_can_change_voltage(reg)) {
  110. r = regulator_set_voltage(reg, 1800000, 1800000);
  111. if (r) {
  112. devm_regulator_put(reg);
  113. DSSWARN("can't set the regulator voltage\n");
  114. return r;
  115. }
  116. }
  117. hdmi.vdda_reg = reg;
  118. return 0;
  119. }
  120. static int hdmi_power_on_core(struct omap_dss_device *dssdev)
  121. {
  122. int r;
  123. r = regulator_enable(hdmi.vdda_reg);
  124. if (r)
  125. return r;
  126. r = hdmi_runtime_get();
  127. if (r)
  128. goto err_runtime_get;
  129. /* Make selection of HDMI in DSS */
  130. dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
  131. hdmi.core_enabled = true;
  132. return 0;
  133. err_runtime_get:
  134. regulator_disable(hdmi.vdda_reg);
  135. return r;
  136. }
  137. static void hdmi_power_off_core(struct omap_dss_device *dssdev)
  138. {
  139. hdmi.core_enabled = false;
  140. hdmi_runtime_put();
  141. regulator_disable(hdmi.vdda_reg);
  142. }
  143. static int hdmi_power_on_full(struct omap_dss_device *dssdev)
  144. {
  145. int r;
  146. struct omap_video_timings *p;
  147. struct omap_overlay_manager *mgr = hdmi.output.manager;
  148. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  149. r = hdmi_power_on_core(dssdev);
  150. if (r)
  151. return r;
  152. p = &hdmi.cfg.timings;
  153. DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
  154. hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
  155. /* disable and clear irqs */
  156. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  157. hdmi_wp_set_irqstatus(&hdmi.wp,
  158. hdmi_wp_get_irqstatus(&hdmi.wp));
  159. r = dss_pll_enable(&hdmi.pll.pll);
  160. if (r) {
  161. DSSERR("Failed to enable PLL\n");
  162. goto err_pll_enable;
  163. }
  164. r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
  165. if (r) {
  166. DSSERR("Failed to configure PLL\n");
  167. goto err_pll_cfg;
  168. }
  169. r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
  170. hdmi_cinfo.clkout[0]);
  171. if (r) {
  172. DSSDBG("Failed to start PHY\n");
  173. goto err_phy_cfg;
  174. }
  175. r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
  176. if (r)
  177. goto err_phy_pwr;
  178. hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
  179. /* bypass TV gamma table */
  180. dispc_enable_gamma_table(0);
  181. /* tv size */
  182. dss_mgr_set_timings(mgr, p);
  183. r = hdmi_wp_video_start(&hdmi.wp);
  184. if (r)
  185. goto err_vid_enable;
  186. r = dss_mgr_enable(mgr);
  187. if (r)
  188. goto err_mgr_enable;
  189. hdmi_wp_set_irqenable(&hdmi.wp,
  190. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  191. return 0;
  192. err_mgr_enable:
  193. hdmi_wp_video_stop(&hdmi.wp);
  194. err_vid_enable:
  195. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  196. err_phy_pwr:
  197. err_phy_cfg:
  198. err_pll_cfg:
  199. dss_pll_disable(&hdmi.pll.pll);
  200. err_pll_enable:
  201. hdmi_power_off_core(dssdev);
  202. return -EIO;
  203. }
  204. static void hdmi_power_off_full(struct omap_dss_device *dssdev)
  205. {
  206. struct omap_overlay_manager *mgr = hdmi.output.manager;
  207. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  208. dss_mgr_disable(mgr);
  209. hdmi_wp_video_stop(&hdmi.wp);
  210. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  211. dss_pll_disable(&hdmi.pll.pll);
  212. hdmi_power_off_core(dssdev);
  213. }
  214. static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
  215. struct omap_video_timings *timings)
  216. {
  217. struct omap_dss_device *out = &hdmi.output;
  218. /* TODO: proper interlace support */
  219. if (timings->interlace)
  220. return -EINVAL;
  221. if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
  222. return -EINVAL;
  223. return 0;
  224. }
  225. static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
  226. struct omap_video_timings *timings)
  227. {
  228. mutex_lock(&hdmi.lock);
  229. hdmi.cfg.timings = *timings;
  230. dispc_set_tv_pclk(timings->pixelclock);
  231. mutex_unlock(&hdmi.lock);
  232. }
  233. static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
  234. struct omap_video_timings *timings)
  235. {
  236. *timings = hdmi.cfg.timings;
  237. }
  238. static void hdmi_dump_regs(struct seq_file *s)
  239. {
  240. mutex_lock(&hdmi.lock);
  241. if (hdmi_runtime_get()) {
  242. mutex_unlock(&hdmi.lock);
  243. return;
  244. }
  245. hdmi_wp_dump(&hdmi.wp, s);
  246. hdmi_pll_dump(&hdmi.pll, s);
  247. hdmi_phy_dump(&hdmi.phy, s);
  248. hdmi5_core_dump(&hdmi.core, s);
  249. hdmi_runtime_put();
  250. mutex_unlock(&hdmi.lock);
  251. }
  252. static int read_edid(u8 *buf, int len)
  253. {
  254. int r;
  255. int idlemode;
  256. mutex_lock(&hdmi.lock);
  257. r = hdmi_runtime_get();
  258. BUG_ON(r);
  259. idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  260. /* No-idle mode */
  261. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  262. r = hdmi5_read_edid(&hdmi.core, buf, len);
  263. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  264. hdmi_runtime_put();
  265. mutex_unlock(&hdmi.lock);
  266. return r;
  267. }
  268. static int hdmi_display_enable(struct omap_dss_device *dssdev)
  269. {
  270. struct omap_dss_device *out = &hdmi.output;
  271. int r = 0;
  272. DSSDBG("ENTER hdmi_display_enable\n");
  273. mutex_lock(&hdmi.lock);
  274. if (out == NULL || out->manager == NULL) {
  275. DSSERR("failed to enable display: no output/manager\n");
  276. r = -ENODEV;
  277. goto err0;
  278. }
  279. r = hdmi_power_on_full(dssdev);
  280. if (r) {
  281. DSSERR("failed to power on device\n");
  282. goto err0;
  283. }
  284. hdmi.display_enabled = true;
  285. mutex_unlock(&hdmi.lock);
  286. return 0;
  287. err0:
  288. mutex_unlock(&hdmi.lock);
  289. return r;
  290. }
  291. static void hdmi_display_disable(struct omap_dss_device *dssdev)
  292. {
  293. DSSDBG("Enter hdmi_display_disable\n");
  294. mutex_lock(&hdmi.lock);
  295. if (hdmi.audio_pdev && hdmi.audio_abort_cb)
  296. hdmi.audio_abort_cb(&hdmi.audio_pdev->dev);
  297. hdmi_power_off_full(dssdev);
  298. hdmi.display_enabled = false;
  299. mutex_unlock(&hdmi.lock);
  300. }
  301. static int hdmi_core_enable(struct omap_dss_device *dssdev)
  302. {
  303. int r = 0;
  304. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  305. mutex_lock(&hdmi.lock);
  306. r = hdmi_power_on_core(dssdev);
  307. if (r) {
  308. DSSERR("failed to power on device\n");
  309. goto err0;
  310. }
  311. mutex_unlock(&hdmi.lock);
  312. return 0;
  313. err0:
  314. mutex_unlock(&hdmi.lock);
  315. return r;
  316. }
  317. static void hdmi_core_disable(struct omap_dss_device *dssdev)
  318. {
  319. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  320. mutex_lock(&hdmi.lock);
  321. hdmi_power_off_core(dssdev);
  322. mutex_unlock(&hdmi.lock);
  323. }
  324. static int hdmi_connect(struct omap_dss_device *dssdev,
  325. struct omap_dss_device *dst)
  326. {
  327. struct omap_overlay_manager *mgr;
  328. int r;
  329. r = hdmi_init_regulator();
  330. if (r)
  331. return r;
  332. mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
  333. if (!mgr)
  334. return -ENODEV;
  335. r = dss_mgr_connect(mgr, dssdev);
  336. if (r)
  337. return r;
  338. r = omapdss_output_set_device(dssdev, dst);
  339. if (r) {
  340. DSSERR("failed to connect output to new device: %s\n",
  341. dst->name);
  342. dss_mgr_disconnect(mgr, dssdev);
  343. return r;
  344. }
  345. return 0;
  346. }
  347. static void hdmi_disconnect(struct omap_dss_device *dssdev,
  348. struct omap_dss_device *dst)
  349. {
  350. WARN_ON(dst != dssdev->dst);
  351. if (dst != dssdev->dst)
  352. return;
  353. omapdss_output_unset_device(dssdev);
  354. if (dssdev->manager)
  355. dss_mgr_disconnect(dssdev->manager, dssdev);
  356. }
  357. static int hdmi_read_edid(struct omap_dss_device *dssdev,
  358. u8 *edid, int len)
  359. {
  360. bool need_enable;
  361. int r;
  362. need_enable = hdmi.core_enabled == false;
  363. if (need_enable) {
  364. r = hdmi_core_enable(dssdev);
  365. if (r)
  366. return r;
  367. }
  368. r = read_edid(edid, len);
  369. if (need_enable)
  370. hdmi_core_disable(dssdev);
  371. return r;
  372. }
  373. static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
  374. const struct hdmi_avi_infoframe *avi)
  375. {
  376. hdmi.cfg.infoframe = *avi;
  377. return 0;
  378. }
  379. static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
  380. bool hdmi_mode)
  381. {
  382. hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
  383. return 0;
  384. }
  385. static const struct omapdss_hdmi_ops hdmi_ops = {
  386. .connect = hdmi_connect,
  387. .disconnect = hdmi_disconnect,
  388. .enable = hdmi_display_enable,
  389. .disable = hdmi_display_disable,
  390. .check_timings = hdmi_display_check_timing,
  391. .set_timings = hdmi_display_set_timing,
  392. .get_timings = hdmi_display_get_timings,
  393. .read_edid = hdmi_read_edid,
  394. .set_infoframe = hdmi_set_infoframe,
  395. .set_hdmi_mode = hdmi_set_hdmi_mode,
  396. };
  397. static void hdmi_init_output(struct platform_device *pdev)
  398. {
  399. struct omap_dss_device *out = &hdmi.output;
  400. out->dev = &pdev->dev;
  401. out->id = OMAP_DSS_OUTPUT_HDMI;
  402. out->output_type = OMAP_DISPLAY_TYPE_HDMI;
  403. out->name = "hdmi.0";
  404. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  405. out->ops.hdmi = &hdmi_ops;
  406. out->owner = THIS_MODULE;
  407. omapdss_register_output(out);
  408. }
  409. static void hdmi_uninit_output(struct platform_device *pdev)
  410. {
  411. struct omap_dss_device *out = &hdmi.output;
  412. omapdss_unregister_output(out);
  413. }
  414. static int hdmi_probe_of(struct platform_device *pdev)
  415. {
  416. struct device_node *node = pdev->dev.of_node;
  417. struct device_node *ep;
  418. int r;
  419. ep = omapdss_of_get_first_endpoint(node);
  420. if (!ep)
  421. return 0;
  422. r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
  423. if (r)
  424. goto err;
  425. of_node_put(ep);
  426. return 0;
  427. err:
  428. of_node_put(ep);
  429. return r;
  430. }
  431. /* Audio callbacks */
  432. static int hdmi_audio_startup(struct device *dev,
  433. void (*abort_cb)(struct device *dev))
  434. {
  435. struct omap_hdmi *hd = dev_get_drvdata(dev);
  436. int ret = 0;
  437. mutex_lock(&hd->lock);
  438. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  439. ret = -EPERM;
  440. goto out;
  441. }
  442. hd->audio_abort_cb = abort_cb;
  443. out:
  444. mutex_unlock(&hd->lock);
  445. return ret;
  446. }
  447. static int hdmi_audio_shutdown(struct device *dev)
  448. {
  449. struct omap_hdmi *hd = dev_get_drvdata(dev);
  450. mutex_lock(&hd->lock);
  451. hd->audio_abort_cb = NULL;
  452. mutex_unlock(&hd->lock);
  453. return 0;
  454. }
  455. static int hdmi_audio_start(struct device *dev)
  456. {
  457. struct omap_hdmi *hd = dev_get_drvdata(dev);
  458. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  459. WARN_ON(!hd->display_enabled);
  460. /* No-idle while playing audio, store the old value */
  461. hd->wp_idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  462. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  463. hdmi_wp_audio_enable(&hd->wp, true);
  464. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  465. return 0;
  466. }
  467. static void hdmi_audio_stop(struct device *dev)
  468. {
  469. struct omap_hdmi *hd = dev_get_drvdata(dev);
  470. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  471. WARN_ON(!hd->display_enabled);
  472. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  473. hdmi_wp_audio_enable(&hd->wp, false);
  474. /* Playback stopped, restore original idlemode */
  475. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  476. }
  477. static int hdmi_audio_config(struct device *dev,
  478. struct omap_dss_audio *dss_audio)
  479. {
  480. struct omap_hdmi *hd = dev_get_drvdata(dev);
  481. int ret;
  482. mutex_lock(&hd->lock);
  483. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  484. ret = -EPERM;
  485. goto out;
  486. }
  487. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  488. hd->cfg.timings.pixelclock);
  489. out:
  490. mutex_unlock(&hd->lock);
  491. return ret;
  492. }
  493. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  494. .audio_startup = hdmi_audio_startup,
  495. .audio_shutdown = hdmi_audio_shutdown,
  496. .audio_start = hdmi_audio_start,
  497. .audio_stop = hdmi_audio_stop,
  498. .audio_config = hdmi_audio_config,
  499. };
  500. static int hdmi_audio_register(struct device *dev)
  501. {
  502. struct omap_hdmi_audio_pdata pdata = {
  503. .dev = dev,
  504. .dss_version = omapdss_get_version(),
  505. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
  506. .ops = &hdmi_audio_ops,
  507. };
  508. hdmi.audio_pdev = platform_device_register_data(
  509. dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  510. &pdata, sizeof(pdata));
  511. if (IS_ERR(hdmi.audio_pdev))
  512. return PTR_ERR(hdmi.audio_pdev);
  513. return 0;
  514. }
  515. /* HDMI HW IP initialisation */
  516. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  517. {
  518. struct platform_device *pdev = to_platform_device(dev);
  519. int r;
  520. int irq;
  521. hdmi.pdev = pdev;
  522. dev_set_drvdata(&pdev->dev, &hdmi);
  523. mutex_init(&hdmi.lock);
  524. if (pdev->dev.of_node) {
  525. r = hdmi_probe_of(pdev);
  526. if (r)
  527. return r;
  528. }
  529. r = hdmi_wp_init(pdev, &hdmi.wp);
  530. if (r)
  531. return r;
  532. r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
  533. if (r)
  534. return r;
  535. r = hdmi_phy_init(pdev, &hdmi.phy);
  536. if (r)
  537. goto err;
  538. r = hdmi5_core_init(pdev, &hdmi.core);
  539. if (r)
  540. goto err;
  541. irq = platform_get_irq(pdev, 0);
  542. if (irq < 0) {
  543. DSSERR("platform_get_irq failed\n");
  544. r = -ENODEV;
  545. goto err;
  546. }
  547. r = devm_request_threaded_irq(&pdev->dev, irq,
  548. NULL, hdmi_irq_handler,
  549. IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
  550. if (r) {
  551. DSSERR("HDMI IRQ request failed\n");
  552. goto err;
  553. }
  554. pm_runtime_enable(&pdev->dev);
  555. hdmi_init_output(pdev);
  556. r = hdmi_audio_register(&pdev->dev);
  557. if (r) {
  558. DSSERR("Registering HDMI audio failed %d\n", r);
  559. hdmi_uninit_output(pdev);
  560. pm_runtime_disable(&pdev->dev);
  561. return r;
  562. }
  563. dss_debugfs_create_file("hdmi", hdmi_dump_regs);
  564. return 0;
  565. err:
  566. hdmi_pll_uninit(&hdmi.pll);
  567. return r;
  568. }
  569. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  570. {
  571. struct platform_device *pdev = to_platform_device(dev);
  572. if (hdmi.audio_pdev)
  573. platform_device_unregister(hdmi.audio_pdev);
  574. hdmi_uninit_output(pdev);
  575. hdmi_pll_uninit(&hdmi.pll);
  576. pm_runtime_disable(&pdev->dev);
  577. }
  578. static const struct component_ops hdmi5_component_ops = {
  579. .bind = hdmi5_bind,
  580. .unbind = hdmi5_unbind,
  581. };
  582. static int hdmi5_probe(struct platform_device *pdev)
  583. {
  584. return component_add(&pdev->dev, &hdmi5_component_ops);
  585. }
  586. static int hdmi5_remove(struct platform_device *pdev)
  587. {
  588. component_del(&pdev->dev, &hdmi5_component_ops);
  589. return 0;
  590. }
  591. static int hdmi_runtime_suspend(struct device *dev)
  592. {
  593. dispc_runtime_put();
  594. return 0;
  595. }
  596. static int hdmi_runtime_resume(struct device *dev)
  597. {
  598. int r;
  599. r = dispc_runtime_get();
  600. if (r < 0)
  601. return r;
  602. return 0;
  603. }
  604. static const struct dev_pm_ops hdmi_pm_ops = {
  605. .runtime_suspend = hdmi_runtime_suspend,
  606. .runtime_resume = hdmi_runtime_resume,
  607. };
  608. static const struct of_device_id hdmi_of_match[] = {
  609. { .compatible = "ti,omap5-hdmi", },
  610. { .compatible = "ti,dra7-hdmi", },
  611. {},
  612. };
  613. static struct platform_driver omapdss_hdmihw_driver = {
  614. .probe = hdmi5_probe,
  615. .remove = hdmi5_remove,
  616. .driver = {
  617. .name = "omapdss_hdmi5",
  618. .pm = &hdmi_pm_ops,
  619. .of_match_table = hdmi_of_match,
  620. .suppress_bind_attrs = true,
  621. },
  622. };
  623. int __init hdmi5_init_platform_driver(void)
  624. {
  625. return platform_driver_register(&omapdss_hdmihw_driver);
  626. }
  627. void hdmi5_uninit_platform_driver(void)
  628. {
  629. platform_driver_unregister(&omapdss_hdmihw_driver);
  630. }