xhci-hub.c 37 KB

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  1. /*
  2. * xHCI host controller driver
  3. *
  4. * Copyright (C) 2008 Intel Corp.
  5. *
  6. * Author: Sarah Sharp
  7. * Some code borrowed from the Linux EHCI driver.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15. * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  16. * for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software Foundation,
  20. * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. #include <linux/slab.h>
  23. #include <asm/unaligned.h>
  24. #include "xhci.h"
  25. #include "xhci-trace.h"
  26. #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
  27. #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
  28. PORT_RC | PORT_PLC | PORT_PE)
  29. /* USB 3.0 BOS descriptor and a capability descriptor, combined */
  30. static u8 usb_bos_descriptor [] = {
  31. USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
  32. USB_DT_BOS, /* __u8 bDescriptorType */
  33. 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
  34. 0x1, /* __u8 bNumDeviceCaps */
  35. /* First device capability */
  36. USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
  37. USB_DT_DEVICE_CAPABILITY, /* Device Capability */
  38. USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
  39. 0x00, /* bmAttributes, LTM off by default */
  40. USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
  41. 0x03, /* bFunctionalitySupport,
  42. USB 3.0 speed only */
  43. 0x00, /* bU1DevExitLat, set later. */
  44. 0x00, 0x00 /* __le16 bU2DevExitLat, set later. */
  45. };
  46. static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
  47. struct usb_hub_descriptor *desc, int ports)
  48. {
  49. u16 temp;
  50. desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
  51. desc->bHubContrCurrent = 0;
  52. desc->bNbrPorts = ports;
  53. temp = 0;
  54. /* Bits 1:0 - support per-port power switching, or power always on */
  55. if (HCC_PPC(xhci->hcc_params))
  56. temp |= HUB_CHAR_INDV_PORT_LPSM;
  57. else
  58. temp |= HUB_CHAR_NO_LPSM;
  59. /* Bit 2 - root hubs are not part of a compound device */
  60. /* Bits 4:3 - individual port over current protection */
  61. temp |= HUB_CHAR_INDV_PORT_OCPM;
  62. /* Bits 6:5 - no TTs in root ports */
  63. /* Bit 7 - no port indicators */
  64. desc->wHubCharacteristics = cpu_to_le16(temp);
  65. }
  66. /* Fill in the USB 2.0 roothub descriptor */
  67. static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  68. struct usb_hub_descriptor *desc)
  69. {
  70. int ports;
  71. u16 temp;
  72. __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
  73. u32 portsc;
  74. unsigned int i;
  75. ports = xhci->num_usb2_ports;
  76. xhci_common_hub_descriptor(xhci, desc, ports);
  77. desc->bDescriptorType = USB_DT_HUB;
  78. temp = 1 + (ports / 8);
  79. desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
  80. /* The Device Removable bits are reported on a byte granularity.
  81. * If the port doesn't exist within that byte, the bit is set to 0.
  82. */
  83. memset(port_removable, 0, sizeof(port_removable));
  84. for (i = 0; i < ports; i++) {
  85. portsc = readl(xhci->usb2_ports[i]);
  86. /* If a device is removable, PORTSC reports a 0, same as in the
  87. * hub descriptor DeviceRemovable bits.
  88. */
  89. if (portsc & PORT_DEV_REMOVE)
  90. /* This math is hairy because bit 0 of DeviceRemovable
  91. * is reserved, and bit 1 is for port 1, etc.
  92. */
  93. port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
  94. }
  95. /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
  96. * ports on it. The USB 2.0 specification says that there are two
  97. * variable length fields at the end of the hub descriptor:
  98. * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
  99. * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
  100. * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
  101. * 0xFF, so we initialize the both arrays (DeviceRemovable and
  102. * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
  103. * set of ports that actually exist.
  104. */
  105. memset(desc->u.hs.DeviceRemovable, 0xff,
  106. sizeof(desc->u.hs.DeviceRemovable));
  107. memset(desc->u.hs.PortPwrCtrlMask, 0xff,
  108. sizeof(desc->u.hs.PortPwrCtrlMask));
  109. for (i = 0; i < (ports + 1 + 7) / 8; i++)
  110. memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
  111. sizeof(__u8));
  112. }
  113. /* Fill in the USB 3.0 roothub descriptor */
  114. static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  115. struct usb_hub_descriptor *desc)
  116. {
  117. int ports;
  118. u16 port_removable;
  119. u32 portsc;
  120. unsigned int i;
  121. ports = xhci->num_usb3_ports;
  122. xhci_common_hub_descriptor(xhci, desc, ports);
  123. desc->bDescriptorType = USB_DT_SS_HUB;
  124. desc->bDescLength = USB_DT_SS_HUB_SIZE;
  125. /* header decode latency should be zero for roothubs,
  126. * see section 4.23.5.2.
  127. */
  128. desc->u.ss.bHubHdrDecLat = 0;
  129. desc->u.ss.wHubDelay = 0;
  130. port_removable = 0;
  131. /* bit 0 is reserved, bit 1 is for port 1, etc. */
  132. for (i = 0; i < ports; i++) {
  133. portsc = readl(xhci->usb3_ports[i]);
  134. if (portsc & PORT_DEV_REMOVE)
  135. port_removable |= 1 << (i + 1);
  136. }
  137. desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
  138. }
  139. static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  140. struct usb_hub_descriptor *desc)
  141. {
  142. if (hcd->speed == HCD_USB3)
  143. xhci_usb3_hub_descriptor(hcd, xhci, desc);
  144. else
  145. xhci_usb2_hub_descriptor(hcd, xhci, desc);
  146. }
  147. static unsigned int xhci_port_speed(unsigned int port_status)
  148. {
  149. if (DEV_LOWSPEED(port_status))
  150. return USB_PORT_STAT_LOW_SPEED;
  151. if (DEV_HIGHSPEED(port_status))
  152. return USB_PORT_STAT_HIGH_SPEED;
  153. /*
  154. * FIXME: Yes, we should check for full speed, but the core uses that as
  155. * a default in portspeed() in usb/core/hub.c (which is the only place
  156. * USB_PORT_STAT_*_SPEED is used).
  157. */
  158. return 0;
  159. }
  160. /*
  161. * These bits are Read Only (RO) and should be saved and written to the
  162. * registers: 0, 3, 10:13, 30
  163. * connect status, over-current status, port speed, and device removable.
  164. * connect status and port speed are also sticky - meaning they're in
  165. * the AUX well and they aren't changed by a hot, warm, or cold reset.
  166. */
  167. #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
  168. /*
  169. * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
  170. * bits 5:8, 9, 14:15, 25:27
  171. * link state, port power, port indicator state, "wake on" enable state
  172. */
  173. #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
  174. /*
  175. * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
  176. * bit 4 (port reset)
  177. */
  178. #define XHCI_PORT_RW1S ((1<<4))
  179. /*
  180. * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
  181. * bits 1, 17, 18, 19, 20, 21, 22, 23
  182. * port enable/disable, and
  183. * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
  184. * over-current, reset, link state, and L1 change
  185. */
  186. #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
  187. /*
  188. * Bit 16 is RW, and writing a '1' to it causes the link state control to be
  189. * latched in
  190. */
  191. #define XHCI_PORT_RW ((1<<16))
  192. /*
  193. * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
  194. * bits 2, 24, 28:31
  195. */
  196. #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
  197. /*
  198. * Given a port state, this function returns a value that would result in the
  199. * port being in the same state, if the value was written to the port status
  200. * control register.
  201. * Save Read Only (RO) bits and save read/write bits where
  202. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  203. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  204. */
  205. u32 xhci_port_state_to_neutral(u32 state)
  206. {
  207. /* Save read-only status and port state */
  208. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  209. }
  210. /*
  211. * find slot id based on port number.
  212. * @port: The one-based port number from one of the two split roothubs.
  213. */
  214. int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  215. u16 port)
  216. {
  217. int slot_id;
  218. int i;
  219. enum usb_device_speed speed;
  220. slot_id = 0;
  221. for (i = 0; i < MAX_HC_SLOTS; i++) {
  222. if (!xhci->devs[i])
  223. continue;
  224. speed = xhci->devs[i]->udev->speed;
  225. if (((speed == USB_SPEED_SUPER) == (hcd->speed == HCD_USB3))
  226. && xhci->devs[i]->fake_port == port) {
  227. slot_id = i;
  228. break;
  229. }
  230. }
  231. return slot_id;
  232. }
  233. /*
  234. * Stop device
  235. * It issues stop endpoint command for EP 0 to 30. And wait the last command
  236. * to complete.
  237. * suspend will set to 1, if suspend bit need to set in command.
  238. */
  239. static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
  240. {
  241. struct xhci_virt_device *virt_dev;
  242. struct xhci_command *cmd;
  243. unsigned long flags;
  244. int ret;
  245. int i;
  246. ret = 0;
  247. virt_dev = xhci->devs[slot_id];
  248. cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
  249. if (!cmd) {
  250. xhci_dbg(xhci, "Couldn't allocate command structure.\n");
  251. return -ENOMEM;
  252. }
  253. spin_lock_irqsave(&xhci->lock, flags);
  254. for (i = LAST_EP_INDEX; i > 0; i--) {
  255. if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
  256. struct xhci_command *command;
  257. command = xhci_alloc_command(xhci, false, false,
  258. GFP_NOWAIT);
  259. if (!command) {
  260. spin_unlock_irqrestore(&xhci->lock, flags);
  261. xhci_free_command(xhci, cmd);
  262. return -ENOMEM;
  263. }
  264. xhci_queue_stop_endpoint(xhci, command, slot_id, i,
  265. suspend);
  266. }
  267. }
  268. xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
  269. xhci_ring_cmd_db(xhci);
  270. spin_unlock_irqrestore(&xhci->lock, flags);
  271. /* Wait for last stop endpoint command to finish */
  272. wait_for_completion(cmd->completion);
  273. if (cmd->status == COMP_CMD_ABORT || cmd->status == COMP_CMD_STOP) {
  274. xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
  275. ret = -ETIME;
  276. }
  277. xhci_free_command(xhci, cmd);
  278. return ret;
  279. }
  280. /*
  281. * Ring device, it rings the all doorbells unconditionally.
  282. */
  283. void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
  284. {
  285. int i, s;
  286. struct xhci_virt_ep *ep;
  287. for (i = 0; i < LAST_EP_INDEX + 1; i++) {
  288. ep = &xhci->devs[slot_id]->eps[i];
  289. if (ep->ep_state & EP_HAS_STREAMS) {
  290. for (s = 1; s < ep->stream_info->num_streams; s++)
  291. xhci_ring_ep_doorbell(xhci, slot_id, i, s);
  292. } else if (ep->ring && ep->ring->dequeue) {
  293. xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
  294. }
  295. }
  296. return;
  297. }
  298. static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
  299. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  300. {
  301. /* Don't allow the USB core to disable SuperSpeed ports. */
  302. if (hcd->speed == HCD_USB3) {
  303. xhci_dbg(xhci, "Ignoring request to disable "
  304. "SuperSpeed port.\n");
  305. return;
  306. }
  307. /* Write 1 to disable the port */
  308. writel(port_status | PORT_PE, addr);
  309. port_status = readl(addr);
  310. xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
  311. wIndex, port_status);
  312. }
  313. static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
  314. u16 wIndex, __le32 __iomem *addr, u32 port_status)
  315. {
  316. char *port_change_bit;
  317. u32 status;
  318. switch (wValue) {
  319. case USB_PORT_FEAT_C_RESET:
  320. status = PORT_RC;
  321. port_change_bit = "reset";
  322. break;
  323. case USB_PORT_FEAT_C_BH_PORT_RESET:
  324. status = PORT_WRC;
  325. port_change_bit = "warm(BH) reset";
  326. break;
  327. case USB_PORT_FEAT_C_CONNECTION:
  328. status = PORT_CSC;
  329. port_change_bit = "connect";
  330. break;
  331. case USB_PORT_FEAT_C_OVER_CURRENT:
  332. status = PORT_OCC;
  333. port_change_bit = "over-current";
  334. break;
  335. case USB_PORT_FEAT_C_ENABLE:
  336. status = PORT_PEC;
  337. port_change_bit = "enable/disable";
  338. break;
  339. case USB_PORT_FEAT_C_SUSPEND:
  340. status = PORT_PLC;
  341. port_change_bit = "suspend/resume";
  342. break;
  343. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  344. status = PORT_PLC;
  345. port_change_bit = "link state";
  346. break;
  347. case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
  348. status = PORT_CEC;
  349. port_change_bit = "config error";
  350. break;
  351. default:
  352. /* Should never happen */
  353. return;
  354. }
  355. /* Change bits are all write 1 to clear */
  356. writel(port_status | status, addr);
  357. port_status = readl(addr);
  358. xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
  359. port_change_bit, wIndex, port_status);
  360. }
  361. static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
  362. {
  363. int max_ports;
  364. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  365. if (hcd->speed == HCD_USB3) {
  366. max_ports = xhci->num_usb3_ports;
  367. *port_array = xhci->usb3_ports;
  368. } else {
  369. max_ports = xhci->num_usb2_ports;
  370. *port_array = xhci->usb2_ports;
  371. }
  372. return max_ports;
  373. }
  374. void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  375. int port_id, u32 link_state)
  376. {
  377. u32 temp;
  378. temp = readl(port_array[port_id]);
  379. temp = xhci_port_state_to_neutral(temp);
  380. temp &= ~PORT_PLS_MASK;
  381. temp |= PORT_LINK_STROBE | link_state;
  382. writel(temp, port_array[port_id]);
  383. }
  384. static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
  385. __le32 __iomem **port_array, int port_id, u16 wake_mask)
  386. {
  387. u32 temp;
  388. temp = readl(port_array[port_id]);
  389. temp = xhci_port_state_to_neutral(temp);
  390. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
  391. temp |= PORT_WKCONN_E;
  392. else
  393. temp &= ~PORT_WKCONN_E;
  394. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
  395. temp |= PORT_WKDISC_E;
  396. else
  397. temp &= ~PORT_WKDISC_E;
  398. if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
  399. temp |= PORT_WKOC_E;
  400. else
  401. temp &= ~PORT_WKOC_E;
  402. writel(temp, port_array[port_id]);
  403. }
  404. /* Test and clear port RWC bit */
  405. void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
  406. int port_id, u32 port_bit)
  407. {
  408. u32 temp;
  409. temp = readl(port_array[port_id]);
  410. if (temp & port_bit) {
  411. temp = xhci_port_state_to_neutral(temp);
  412. temp |= port_bit;
  413. writel(temp, port_array[port_id]);
  414. }
  415. }
  416. /* Updates Link Status for USB 2.1 port */
  417. static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
  418. {
  419. if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
  420. *status |= USB_PORT_STAT_L1;
  421. }
  422. /* Updates Link Status for super Speed port */
  423. static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
  424. u32 *status, u32 status_reg)
  425. {
  426. u32 pls = status_reg & PORT_PLS_MASK;
  427. /* resume state is a xHCI internal state.
  428. * Do not report it to usb core, instead, pretend to be U3,
  429. * thus usb core knows it's not ready for transfer
  430. */
  431. if (pls == XDEV_RESUME) {
  432. *status |= USB_SS_PORT_LS_U3;
  433. return;
  434. }
  435. /* When the CAS bit is set then warm reset
  436. * should be performed on port
  437. */
  438. if (status_reg & PORT_CAS) {
  439. /* The CAS bit can be set while the port is
  440. * in any link state.
  441. * Only roothubs have CAS bit, so we
  442. * pretend to be in compliance mode
  443. * unless we're already in compliance
  444. * or the inactive state.
  445. */
  446. if (pls != USB_SS_PORT_LS_COMP_MOD &&
  447. pls != USB_SS_PORT_LS_SS_INACTIVE) {
  448. pls = USB_SS_PORT_LS_COMP_MOD;
  449. }
  450. /* Return also connection bit -
  451. * hub state machine resets port
  452. * when this bit is set.
  453. */
  454. pls |= USB_PORT_STAT_CONNECTION;
  455. } else {
  456. /*
  457. * If CAS bit isn't set but the Port is already at
  458. * Compliance Mode, fake a connection so the USB core
  459. * notices the Compliance state and resets the port.
  460. * This resolves an issue generated by the SN65LVPE502CP
  461. * in which sometimes the port enters compliance mode
  462. * caused by a delay on the host-device negotiation.
  463. */
  464. if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
  465. (pls == USB_SS_PORT_LS_COMP_MOD))
  466. pls |= USB_PORT_STAT_CONNECTION;
  467. }
  468. /* update status field */
  469. *status |= pls;
  470. }
  471. /*
  472. * Function for Compliance Mode Quirk.
  473. *
  474. * This Function verifies if all xhc USB3 ports have entered U0, if so,
  475. * the compliance mode timer is deleted. A port won't enter
  476. * compliance mode if it has previously entered U0.
  477. */
  478. static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
  479. u16 wIndex)
  480. {
  481. u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
  482. bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
  483. if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
  484. return;
  485. if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
  486. xhci->port_status_u0 |= 1 << wIndex;
  487. if (xhci->port_status_u0 == all_ports_seen_u0) {
  488. del_timer_sync(&xhci->comp_mode_recovery_timer);
  489. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  490. "All USB3 ports have entered U0 already!");
  491. xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
  492. "Compliance Mode Recovery Timer Deleted.");
  493. }
  494. }
  495. }
  496. /*
  497. * Converts a raw xHCI port status into the format that external USB 2.0 or USB
  498. * 3.0 hubs use.
  499. *
  500. * Possible side effects:
  501. * - Mark a port as being done with device resume,
  502. * and ring the endpoint doorbells.
  503. * - Stop the Synopsys redriver Compliance Mode polling.
  504. * - Drop and reacquire the xHCI lock, in order to wait for port resume.
  505. */
  506. static u32 xhci_get_port_status(struct usb_hcd *hcd,
  507. struct xhci_bus_state *bus_state,
  508. __le32 __iomem **port_array,
  509. u16 wIndex, u32 raw_port_status,
  510. unsigned long flags)
  511. __releases(&xhci->lock)
  512. __acquires(&xhci->lock)
  513. {
  514. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  515. u32 status = 0;
  516. int slot_id;
  517. /* wPortChange bits */
  518. if (raw_port_status & PORT_CSC)
  519. status |= USB_PORT_STAT_C_CONNECTION << 16;
  520. if (raw_port_status & PORT_PEC)
  521. status |= USB_PORT_STAT_C_ENABLE << 16;
  522. if ((raw_port_status & PORT_OCC))
  523. status |= USB_PORT_STAT_C_OVERCURRENT << 16;
  524. if ((raw_port_status & PORT_RC))
  525. status |= USB_PORT_STAT_C_RESET << 16;
  526. /* USB3.0 only */
  527. if (hcd->speed == HCD_USB3) {
  528. /* Port link change with port in resume state should not be
  529. * reported to usbcore, as this is an internal state to be
  530. * handled by xhci driver. Reporting PLC to usbcore may
  531. * cause usbcore clearing PLC first and port change event
  532. * irq won't be generated.
  533. */
  534. if ((raw_port_status & PORT_PLC) &&
  535. (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
  536. status |= USB_PORT_STAT_C_LINK_STATE << 16;
  537. if ((raw_port_status & PORT_WRC))
  538. status |= USB_PORT_STAT_C_BH_RESET << 16;
  539. if ((raw_port_status & PORT_CEC))
  540. status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
  541. }
  542. if (hcd->speed != HCD_USB3) {
  543. if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
  544. && (raw_port_status & PORT_POWER))
  545. status |= USB_PORT_STAT_SUSPEND;
  546. }
  547. if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
  548. !DEV_SUPERSPEED(raw_port_status)) {
  549. if ((raw_port_status & PORT_RESET) ||
  550. !(raw_port_status & PORT_PE))
  551. return 0xffffffff;
  552. if (time_after_eq(jiffies,
  553. bus_state->resume_done[wIndex])) {
  554. int time_left;
  555. xhci_dbg(xhci, "Resume USB2 port %d\n",
  556. wIndex + 1);
  557. bus_state->resume_done[wIndex] = 0;
  558. clear_bit(wIndex, &bus_state->resuming_ports);
  559. set_bit(wIndex, &bus_state->rexit_ports);
  560. xhci_set_link_state(xhci, port_array, wIndex,
  561. XDEV_U0);
  562. spin_unlock_irqrestore(&xhci->lock, flags);
  563. time_left = wait_for_completion_timeout(
  564. &bus_state->rexit_done[wIndex],
  565. msecs_to_jiffies(
  566. XHCI_MAX_REXIT_TIMEOUT));
  567. spin_lock_irqsave(&xhci->lock, flags);
  568. if (time_left) {
  569. slot_id = xhci_find_slot_id_by_port(hcd,
  570. xhci, wIndex + 1);
  571. if (!slot_id) {
  572. xhci_dbg(xhci, "slot_id is zero\n");
  573. return 0xffffffff;
  574. }
  575. xhci_ring_device(xhci, slot_id);
  576. } else {
  577. int port_status = readl(port_array[wIndex]);
  578. xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
  579. XHCI_MAX_REXIT_TIMEOUT,
  580. port_status);
  581. status |= USB_PORT_STAT_SUSPEND;
  582. clear_bit(wIndex, &bus_state->rexit_ports);
  583. }
  584. bus_state->port_c_suspend |= 1 << wIndex;
  585. bus_state->suspended_ports &= ~(1 << wIndex);
  586. } else {
  587. /*
  588. * The resume has been signaling for less than
  589. * 20ms. Report the port status as SUSPEND,
  590. * let the usbcore check port status again
  591. * and clear resume signaling later.
  592. */
  593. status |= USB_PORT_STAT_SUSPEND;
  594. }
  595. }
  596. if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0
  597. && (raw_port_status & PORT_POWER)
  598. && (bus_state->suspended_ports & (1 << wIndex))) {
  599. bus_state->suspended_ports &= ~(1 << wIndex);
  600. if (hcd->speed != HCD_USB3)
  601. bus_state->port_c_suspend |= 1 << wIndex;
  602. }
  603. if (raw_port_status & PORT_CONNECT) {
  604. status |= USB_PORT_STAT_CONNECTION;
  605. status |= xhci_port_speed(raw_port_status);
  606. }
  607. if (raw_port_status & PORT_PE)
  608. status |= USB_PORT_STAT_ENABLE;
  609. if (raw_port_status & PORT_OC)
  610. status |= USB_PORT_STAT_OVERCURRENT;
  611. if (raw_port_status & PORT_RESET)
  612. status |= USB_PORT_STAT_RESET;
  613. if (raw_port_status & PORT_POWER) {
  614. if (hcd->speed == HCD_USB3)
  615. status |= USB_SS_PORT_STAT_POWER;
  616. else
  617. status |= USB_PORT_STAT_POWER;
  618. }
  619. /* Update Port Link State */
  620. if (hcd->speed == HCD_USB3) {
  621. xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
  622. /*
  623. * Verify if all USB3 Ports Have entered U0 already.
  624. * Delete Compliance Mode Timer if so.
  625. */
  626. xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
  627. } else {
  628. xhci_hub_report_usb2_link_state(&status, raw_port_status);
  629. }
  630. if (bus_state->port_c_suspend & (1 << wIndex))
  631. status |= 1 << USB_PORT_FEAT_C_SUSPEND;
  632. return status;
  633. }
  634. int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
  635. u16 wIndex, char *buf, u16 wLength)
  636. {
  637. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  638. int max_ports;
  639. unsigned long flags;
  640. u32 temp, status;
  641. int retval = 0;
  642. __le32 __iomem **port_array;
  643. int slot_id;
  644. struct xhci_bus_state *bus_state;
  645. u16 link_state = 0;
  646. u16 wake_mask = 0;
  647. u16 timeout = 0;
  648. max_ports = xhci_get_ports(hcd, &port_array);
  649. bus_state = &xhci->bus_state[hcd_index(hcd)];
  650. spin_lock_irqsave(&xhci->lock, flags);
  651. switch (typeReq) {
  652. case GetHubStatus:
  653. /* No power source, over-current reported per port */
  654. memset(buf, 0, 4);
  655. break;
  656. case GetHubDescriptor:
  657. /* Check to make sure userspace is asking for the USB 3.0 hub
  658. * descriptor for the USB 3.0 roothub. If not, we stall the
  659. * endpoint, like external hubs do.
  660. */
  661. if (hcd->speed == HCD_USB3 &&
  662. (wLength < USB_DT_SS_HUB_SIZE ||
  663. wValue != (USB_DT_SS_HUB << 8))) {
  664. xhci_dbg(xhci, "Wrong hub descriptor type for "
  665. "USB 3.0 roothub.\n");
  666. goto error;
  667. }
  668. xhci_hub_descriptor(hcd, xhci,
  669. (struct usb_hub_descriptor *) buf);
  670. break;
  671. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  672. if ((wValue & 0xff00) != (USB_DT_BOS << 8))
  673. goto error;
  674. if (hcd->speed != HCD_USB3)
  675. goto error;
  676. /* Set the U1 and U2 exit latencies. */
  677. memcpy(buf, &usb_bos_descriptor,
  678. USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE);
  679. if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
  680. temp = readl(&xhci->cap_regs->hcs_params3);
  681. buf[12] = HCS_U1_LATENCY(temp);
  682. put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
  683. }
  684. /* Indicate whether the host has LTM support. */
  685. temp = readl(&xhci->cap_regs->hcc_params);
  686. if (HCC_LTC(temp))
  687. buf[8] |= USB_LTM_SUPPORT;
  688. spin_unlock_irqrestore(&xhci->lock, flags);
  689. return USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
  690. case GetPortStatus:
  691. if (!wIndex || wIndex > max_ports)
  692. goto error;
  693. wIndex--;
  694. temp = readl(port_array[wIndex]);
  695. if (temp == 0xffffffff) {
  696. retval = -ENODEV;
  697. break;
  698. }
  699. status = xhci_get_port_status(hcd, bus_state, port_array,
  700. wIndex, temp, flags);
  701. if (status == 0xffffffff)
  702. goto error;
  703. xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
  704. wIndex, temp);
  705. xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
  706. put_unaligned(cpu_to_le32(status), (__le32 *) buf);
  707. break;
  708. case SetPortFeature:
  709. if (wValue == USB_PORT_FEAT_LINK_STATE)
  710. link_state = (wIndex & 0xff00) >> 3;
  711. if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
  712. wake_mask = wIndex & 0xff00;
  713. /* The MSB of wIndex is the U1/U2 timeout */
  714. timeout = (wIndex & 0xff00) >> 8;
  715. wIndex &= 0xff;
  716. if (!wIndex || wIndex > max_ports)
  717. goto error;
  718. wIndex--;
  719. temp = readl(port_array[wIndex]);
  720. if (temp == 0xffffffff) {
  721. retval = -ENODEV;
  722. break;
  723. }
  724. temp = xhci_port_state_to_neutral(temp);
  725. /* FIXME: What new port features do we need to support? */
  726. switch (wValue) {
  727. case USB_PORT_FEAT_SUSPEND:
  728. temp = readl(port_array[wIndex]);
  729. if ((temp & PORT_PLS_MASK) != XDEV_U0) {
  730. /* Resume the port to U0 first */
  731. xhci_set_link_state(xhci, port_array, wIndex,
  732. XDEV_U0);
  733. spin_unlock_irqrestore(&xhci->lock, flags);
  734. msleep(10);
  735. spin_lock_irqsave(&xhci->lock, flags);
  736. }
  737. /* In spec software should not attempt to suspend
  738. * a port unless the port reports that it is in the
  739. * enabled (PED = ‘1’,PLS < ‘3’) state.
  740. */
  741. temp = readl(port_array[wIndex]);
  742. if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
  743. || (temp & PORT_PLS_MASK) >= XDEV_U3) {
  744. xhci_warn(xhci, "USB core suspending device "
  745. "not in U0/U1/U2.\n");
  746. goto error;
  747. }
  748. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  749. wIndex + 1);
  750. if (!slot_id) {
  751. xhci_warn(xhci, "slot_id is zero\n");
  752. goto error;
  753. }
  754. /* unlock to execute stop endpoint commands */
  755. spin_unlock_irqrestore(&xhci->lock, flags);
  756. xhci_stop_device(xhci, slot_id, 1);
  757. spin_lock_irqsave(&xhci->lock, flags);
  758. xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
  759. spin_unlock_irqrestore(&xhci->lock, flags);
  760. msleep(10); /* wait device to enter */
  761. spin_lock_irqsave(&xhci->lock, flags);
  762. temp = readl(port_array[wIndex]);
  763. bus_state->suspended_ports |= 1 << wIndex;
  764. break;
  765. case USB_PORT_FEAT_LINK_STATE:
  766. temp = readl(port_array[wIndex]);
  767. /* Disable port */
  768. if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
  769. xhci_dbg(xhci, "Disable port %d\n", wIndex);
  770. temp = xhci_port_state_to_neutral(temp);
  771. /*
  772. * Clear all change bits, so that we get a new
  773. * connection event.
  774. */
  775. temp |= PORT_CSC | PORT_PEC | PORT_WRC |
  776. PORT_OCC | PORT_RC | PORT_PLC |
  777. PORT_CEC;
  778. writel(temp | PORT_PE, port_array[wIndex]);
  779. temp = readl(port_array[wIndex]);
  780. break;
  781. }
  782. /* Put link in RxDetect (enable port) */
  783. if (link_state == USB_SS_PORT_LS_RX_DETECT) {
  784. xhci_dbg(xhci, "Enable port %d\n", wIndex);
  785. xhci_set_link_state(xhci, port_array, wIndex,
  786. link_state);
  787. temp = readl(port_array[wIndex]);
  788. break;
  789. }
  790. /* Software should not attempt to set
  791. * port link state above '3' (U3) and the port
  792. * must be enabled.
  793. */
  794. if ((temp & PORT_PE) == 0 ||
  795. (link_state > USB_SS_PORT_LS_U3)) {
  796. xhci_warn(xhci, "Cannot set link state.\n");
  797. goto error;
  798. }
  799. if (link_state == USB_SS_PORT_LS_U3) {
  800. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  801. wIndex + 1);
  802. if (slot_id) {
  803. /* unlock to execute stop endpoint
  804. * commands */
  805. spin_unlock_irqrestore(&xhci->lock,
  806. flags);
  807. xhci_stop_device(xhci, slot_id, 1);
  808. spin_lock_irqsave(&xhci->lock, flags);
  809. }
  810. }
  811. xhci_set_link_state(xhci, port_array, wIndex,
  812. link_state);
  813. spin_unlock_irqrestore(&xhci->lock, flags);
  814. msleep(20); /* wait device to enter */
  815. spin_lock_irqsave(&xhci->lock, flags);
  816. temp = readl(port_array[wIndex]);
  817. if (link_state == USB_SS_PORT_LS_U3)
  818. bus_state->suspended_ports |= 1 << wIndex;
  819. break;
  820. case USB_PORT_FEAT_POWER:
  821. /*
  822. * Turn on ports, even if there isn't per-port switching.
  823. * HC will report connect events even before this is set.
  824. * However, hub_wq will ignore the roothub events until
  825. * the roothub is registered.
  826. */
  827. writel(temp | PORT_POWER, port_array[wIndex]);
  828. temp = readl(port_array[wIndex]);
  829. xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n", wIndex, temp);
  830. spin_unlock_irqrestore(&xhci->lock, flags);
  831. temp = usb_acpi_power_manageable(hcd->self.root_hub,
  832. wIndex);
  833. if (temp)
  834. usb_acpi_set_power_state(hcd->self.root_hub,
  835. wIndex, true);
  836. spin_lock_irqsave(&xhci->lock, flags);
  837. break;
  838. case USB_PORT_FEAT_RESET:
  839. temp = (temp | PORT_RESET);
  840. writel(temp, port_array[wIndex]);
  841. temp = readl(port_array[wIndex]);
  842. xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
  843. break;
  844. case USB_PORT_FEAT_REMOTE_WAKE_MASK:
  845. xhci_set_remote_wake_mask(xhci, port_array,
  846. wIndex, wake_mask);
  847. temp = readl(port_array[wIndex]);
  848. xhci_dbg(xhci, "set port remote wake mask, "
  849. "actual port %d status = 0x%x\n",
  850. wIndex, temp);
  851. break;
  852. case USB_PORT_FEAT_BH_PORT_RESET:
  853. temp |= PORT_WR;
  854. writel(temp, port_array[wIndex]);
  855. temp = readl(port_array[wIndex]);
  856. break;
  857. case USB_PORT_FEAT_U1_TIMEOUT:
  858. if (hcd->speed != HCD_USB3)
  859. goto error;
  860. temp = readl(port_array[wIndex] + PORTPMSC);
  861. temp &= ~PORT_U1_TIMEOUT_MASK;
  862. temp |= PORT_U1_TIMEOUT(timeout);
  863. writel(temp, port_array[wIndex] + PORTPMSC);
  864. break;
  865. case USB_PORT_FEAT_U2_TIMEOUT:
  866. if (hcd->speed != HCD_USB3)
  867. goto error;
  868. temp = readl(port_array[wIndex] + PORTPMSC);
  869. temp &= ~PORT_U2_TIMEOUT_MASK;
  870. temp |= PORT_U2_TIMEOUT(timeout);
  871. writel(temp, port_array[wIndex] + PORTPMSC);
  872. break;
  873. default:
  874. goto error;
  875. }
  876. /* unblock any posted writes */
  877. temp = readl(port_array[wIndex]);
  878. break;
  879. case ClearPortFeature:
  880. if (!wIndex || wIndex > max_ports)
  881. goto error;
  882. wIndex--;
  883. temp = readl(port_array[wIndex]);
  884. if (temp == 0xffffffff) {
  885. retval = -ENODEV;
  886. break;
  887. }
  888. /* FIXME: What new port features do we need to support? */
  889. temp = xhci_port_state_to_neutral(temp);
  890. switch (wValue) {
  891. case USB_PORT_FEAT_SUSPEND:
  892. temp = readl(port_array[wIndex]);
  893. xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
  894. xhci_dbg(xhci, "PORTSC %04x\n", temp);
  895. if (temp & PORT_RESET)
  896. goto error;
  897. if ((temp & PORT_PLS_MASK) == XDEV_U3) {
  898. if ((temp & PORT_PE) == 0)
  899. goto error;
  900. xhci_set_link_state(xhci, port_array, wIndex,
  901. XDEV_RESUME);
  902. spin_unlock_irqrestore(&xhci->lock, flags);
  903. msleep(20);
  904. spin_lock_irqsave(&xhci->lock, flags);
  905. xhci_set_link_state(xhci, port_array, wIndex,
  906. XDEV_U0);
  907. }
  908. bus_state->port_c_suspend |= 1 << wIndex;
  909. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  910. wIndex + 1);
  911. if (!slot_id) {
  912. xhci_dbg(xhci, "slot_id is zero\n");
  913. goto error;
  914. }
  915. xhci_ring_device(xhci, slot_id);
  916. break;
  917. case USB_PORT_FEAT_C_SUSPEND:
  918. bus_state->port_c_suspend &= ~(1 << wIndex);
  919. case USB_PORT_FEAT_C_RESET:
  920. case USB_PORT_FEAT_C_BH_PORT_RESET:
  921. case USB_PORT_FEAT_C_CONNECTION:
  922. case USB_PORT_FEAT_C_OVER_CURRENT:
  923. case USB_PORT_FEAT_C_ENABLE:
  924. case USB_PORT_FEAT_C_PORT_LINK_STATE:
  925. case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
  926. xhci_clear_port_change_bit(xhci, wValue, wIndex,
  927. port_array[wIndex], temp);
  928. break;
  929. case USB_PORT_FEAT_ENABLE:
  930. xhci_disable_port(hcd, xhci, wIndex,
  931. port_array[wIndex], temp);
  932. break;
  933. case USB_PORT_FEAT_POWER:
  934. writel(temp & ~PORT_POWER, port_array[wIndex]);
  935. spin_unlock_irqrestore(&xhci->lock, flags);
  936. temp = usb_acpi_power_manageable(hcd->self.root_hub,
  937. wIndex);
  938. if (temp)
  939. usb_acpi_set_power_state(hcd->self.root_hub,
  940. wIndex, false);
  941. spin_lock_irqsave(&xhci->lock, flags);
  942. break;
  943. default:
  944. goto error;
  945. }
  946. break;
  947. default:
  948. error:
  949. /* "stall" on error */
  950. retval = -EPIPE;
  951. }
  952. spin_unlock_irqrestore(&xhci->lock, flags);
  953. return retval;
  954. }
  955. /*
  956. * Returns 0 if the status hasn't changed, or the number of bytes in buf.
  957. * Ports are 0-indexed from the HCD point of view,
  958. * and 1-indexed from the USB core pointer of view.
  959. *
  960. * Note that the status change bits will be cleared as soon as a port status
  961. * change event is generated, so we use the saved status from that event.
  962. */
  963. int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
  964. {
  965. unsigned long flags;
  966. u32 temp, status;
  967. u32 mask;
  968. int i, retval;
  969. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  970. int max_ports;
  971. __le32 __iomem **port_array;
  972. struct xhci_bus_state *bus_state;
  973. bool reset_change = false;
  974. max_ports = xhci_get_ports(hcd, &port_array);
  975. bus_state = &xhci->bus_state[hcd_index(hcd)];
  976. /* Initial status is no changes */
  977. retval = (max_ports + 8) / 8;
  978. memset(buf, 0, retval);
  979. /*
  980. * Inform the usbcore about resume-in-progress by returning
  981. * a non-zero value even if there are no status changes.
  982. */
  983. status = bus_state->resuming_ports;
  984. mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
  985. spin_lock_irqsave(&xhci->lock, flags);
  986. /* For each port, did anything change? If so, set that bit in buf. */
  987. for (i = 0; i < max_ports; i++) {
  988. temp = readl(port_array[i]);
  989. if (temp == 0xffffffff) {
  990. retval = -ENODEV;
  991. break;
  992. }
  993. if ((temp & mask) != 0 ||
  994. (bus_state->port_c_suspend & 1 << i) ||
  995. (bus_state->resume_done[i] && time_after_eq(
  996. jiffies, bus_state->resume_done[i]))) {
  997. buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
  998. status = 1;
  999. }
  1000. if ((temp & PORT_RC))
  1001. reset_change = true;
  1002. }
  1003. if (!status && !reset_change) {
  1004. xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
  1005. clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
  1006. }
  1007. spin_unlock_irqrestore(&xhci->lock, flags);
  1008. return status ? retval : 0;
  1009. }
  1010. #ifdef CONFIG_PM
  1011. int xhci_bus_suspend(struct usb_hcd *hcd)
  1012. {
  1013. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1014. int max_ports, port_index;
  1015. __le32 __iomem **port_array;
  1016. struct xhci_bus_state *bus_state;
  1017. unsigned long flags;
  1018. max_ports = xhci_get_ports(hcd, &port_array);
  1019. bus_state = &xhci->bus_state[hcd_index(hcd)];
  1020. spin_lock_irqsave(&xhci->lock, flags);
  1021. if (hcd->self.root_hub->do_remote_wakeup) {
  1022. if (bus_state->resuming_ports || /* USB2 */
  1023. bus_state->port_remote_wakeup) { /* USB3 */
  1024. spin_unlock_irqrestore(&xhci->lock, flags);
  1025. xhci_dbg(xhci, "suspend failed because a port is resuming\n");
  1026. return -EBUSY;
  1027. }
  1028. }
  1029. port_index = max_ports;
  1030. bus_state->bus_suspended = 0;
  1031. while (port_index--) {
  1032. /* suspend the port if the port is not suspended */
  1033. u32 t1, t2;
  1034. int slot_id;
  1035. t1 = readl(port_array[port_index]);
  1036. t2 = xhci_port_state_to_neutral(t1);
  1037. if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
  1038. xhci_dbg(xhci, "port %d not suspended\n", port_index);
  1039. slot_id = xhci_find_slot_id_by_port(hcd, xhci,
  1040. port_index + 1);
  1041. if (slot_id) {
  1042. spin_unlock_irqrestore(&xhci->lock, flags);
  1043. xhci_stop_device(xhci, slot_id, 1);
  1044. spin_lock_irqsave(&xhci->lock, flags);
  1045. }
  1046. t2 &= ~PORT_PLS_MASK;
  1047. t2 |= PORT_LINK_STROBE | XDEV_U3;
  1048. set_bit(port_index, &bus_state->bus_suspended);
  1049. }
  1050. /* USB core sets remote wake mask for USB 3.0 hubs,
  1051. * including the USB 3.0 roothub, but only if CONFIG_PM
  1052. * is enabled, so also enable remote wake here.
  1053. */
  1054. if (hcd->self.root_hub->do_remote_wakeup) {
  1055. if (t1 & PORT_CONNECT) {
  1056. t2 |= PORT_WKOC_E | PORT_WKDISC_E;
  1057. t2 &= ~PORT_WKCONN_E;
  1058. } else {
  1059. t2 |= PORT_WKOC_E | PORT_WKCONN_E;
  1060. t2 &= ~PORT_WKDISC_E;
  1061. }
  1062. } else
  1063. t2 &= ~PORT_WAKE_BITS;
  1064. t1 = xhci_port_state_to_neutral(t1);
  1065. if (t1 != t2)
  1066. writel(t2, port_array[port_index]);
  1067. }
  1068. hcd->state = HC_STATE_SUSPENDED;
  1069. bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
  1070. spin_unlock_irqrestore(&xhci->lock, flags);
  1071. return 0;
  1072. }
  1073. int xhci_bus_resume(struct usb_hcd *hcd)
  1074. {
  1075. struct xhci_hcd *xhci = hcd_to_xhci(hcd);
  1076. int max_ports, port_index;
  1077. __le32 __iomem **port_array;
  1078. struct xhci_bus_state *bus_state;
  1079. u32 temp;
  1080. unsigned long flags;
  1081. unsigned long port_was_suspended = 0;
  1082. bool need_usb2_u3_exit = false;
  1083. int slot_id;
  1084. int sret;
  1085. max_ports = xhci_get_ports(hcd, &port_array);
  1086. bus_state = &xhci->bus_state[hcd_index(hcd)];
  1087. if (time_before(jiffies, bus_state->next_statechange))
  1088. msleep(5);
  1089. spin_lock_irqsave(&xhci->lock, flags);
  1090. if (!HCD_HW_ACCESSIBLE(hcd)) {
  1091. spin_unlock_irqrestore(&xhci->lock, flags);
  1092. return -ESHUTDOWN;
  1093. }
  1094. /* delay the irqs */
  1095. temp = readl(&xhci->op_regs->command);
  1096. temp &= ~CMD_EIE;
  1097. writel(temp, &xhci->op_regs->command);
  1098. port_index = max_ports;
  1099. while (port_index--) {
  1100. /* Check whether need resume ports. If needed
  1101. resume port and disable remote wakeup */
  1102. u32 temp;
  1103. temp = readl(port_array[port_index]);
  1104. if (DEV_SUPERSPEED(temp))
  1105. temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
  1106. else
  1107. temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
  1108. if (test_bit(port_index, &bus_state->bus_suspended) &&
  1109. (temp & PORT_PLS_MASK)) {
  1110. set_bit(port_index, &port_was_suspended);
  1111. if (!DEV_SUPERSPEED(temp)) {
  1112. xhci_set_link_state(xhci, port_array,
  1113. port_index, XDEV_RESUME);
  1114. need_usb2_u3_exit = true;
  1115. }
  1116. } else
  1117. writel(temp, port_array[port_index]);
  1118. }
  1119. if (need_usb2_u3_exit) {
  1120. spin_unlock_irqrestore(&xhci->lock, flags);
  1121. msleep(20);
  1122. spin_lock_irqsave(&xhci->lock, flags);
  1123. }
  1124. port_index = max_ports;
  1125. while (port_index--) {
  1126. if (!(port_was_suspended & BIT(port_index)))
  1127. continue;
  1128. /* Clear PLC to poll it later after XDEV_U0 */
  1129. xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
  1130. xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
  1131. }
  1132. port_index = max_ports;
  1133. while (port_index--) {
  1134. if (!(port_was_suspended & BIT(port_index)))
  1135. continue;
  1136. /* Poll and Clear PLC */
  1137. sret = xhci_handshake(port_array[port_index], PORT_PLC,
  1138. PORT_PLC, 10 * 1000);
  1139. if (sret)
  1140. xhci_warn(xhci, "port %d resume PLC timeout\n",
  1141. port_index);
  1142. xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
  1143. slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
  1144. if (slot_id)
  1145. xhci_ring_device(xhci, slot_id);
  1146. }
  1147. (void) readl(&xhci->op_regs->command);
  1148. bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
  1149. /* re-enable irqs */
  1150. temp = readl(&xhci->op_regs->command);
  1151. temp |= CMD_EIE;
  1152. writel(temp, &xhci->op_regs->command);
  1153. temp = readl(&xhci->op_regs->command);
  1154. spin_unlock_irqrestore(&xhci->lock, flags);
  1155. return 0;
  1156. }
  1157. #endif /* CONFIG_PM */