bcma-hcd.c 9.9 KB

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  1. /*
  2. * Broadcom specific Advanced Microcontroller Bus
  3. * Broadcom USB-core driver (BCMA bus glue)
  4. *
  5. * Copyright 2011-2015 Hauke Mehrtens <hauke@hauke-m.de>
  6. * Copyright 2015 Felix Fietkau <nbd@openwrt.org>
  7. *
  8. * Based on ssb-ohci driver
  9. * Copyright 2007 Michael Buesch <m@bues.ch>
  10. *
  11. * Derived from the OHCI-PCI driver
  12. * Copyright 1999 Roman Weissgaerber
  13. * Copyright 2000-2002 David Brownell
  14. * Copyright 1999 Linus Torvalds
  15. * Copyright 1999 Gregory P. Smith
  16. *
  17. * Derived from the USBcore related parts of Broadcom-SB
  18. * Copyright 2005-2011 Broadcom Corporation
  19. *
  20. * Licensed under the GNU/GPL. See COPYING for details.
  21. */
  22. #include <linux/bcma/bcma.h>
  23. #include <linux/delay.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/module.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <linux/of_gpio.h>
  29. #include <linux/usb/ehci_pdriver.h>
  30. #include <linux/usb/ohci_pdriver.h>
  31. MODULE_AUTHOR("Hauke Mehrtens");
  32. MODULE_DESCRIPTION("Common USB driver for BCMA Bus");
  33. MODULE_LICENSE("GPL");
  34. struct bcma_hcd_device {
  35. struct platform_device *ehci_dev;
  36. struct platform_device *ohci_dev;
  37. };
  38. /* Wait for bitmask in a register to get set or cleared.
  39. * timeout is in units of ten-microseconds.
  40. */
  41. static int bcma_wait_bits(struct bcma_device *dev, u16 reg, u32 bitmask,
  42. int timeout)
  43. {
  44. int i;
  45. u32 val;
  46. for (i = 0; i < timeout; i++) {
  47. val = bcma_read32(dev, reg);
  48. if ((val & bitmask) == bitmask)
  49. return 0;
  50. udelay(10);
  51. }
  52. return -ETIMEDOUT;
  53. }
  54. static void bcma_hcd_4716wa(struct bcma_device *dev)
  55. {
  56. #ifdef CONFIG_BCMA_DRIVER_MIPS
  57. /* Work around for 4716 failures. */
  58. if (dev->bus->chipinfo.id == 0x4716) {
  59. u32 tmp;
  60. tmp = bcma_cpu_clock(&dev->bus->drv_mips);
  61. if (tmp >= 480000000)
  62. tmp = 0x1846b; /* set CDR to 0x11(fast) */
  63. else if (tmp == 453000000)
  64. tmp = 0x1046b; /* set CDR to 0x10(slow) */
  65. else
  66. tmp = 0;
  67. /* Change Shim mdio control reg to fix host not acking at
  68. * high frequencies
  69. */
  70. if (tmp) {
  71. bcma_write32(dev, 0x524, 0x1); /* write sel to enable */
  72. udelay(500);
  73. bcma_write32(dev, 0x524, tmp);
  74. udelay(500);
  75. bcma_write32(dev, 0x524, 0x4ab);
  76. udelay(500);
  77. bcma_read32(dev, 0x528);
  78. bcma_write32(dev, 0x528, 0x80000000);
  79. }
  80. }
  81. #endif /* CONFIG_BCMA_DRIVER_MIPS */
  82. }
  83. /* based on arch/mips/brcm-boards/bcm947xx/pcibios.c */
  84. static void bcma_hcd_init_chip_mips(struct bcma_device *dev)
  85. {
  86. u32 tmp;
  87. /*
  88. * USB 2.0 special considerations:
  89. *
  90. * 1. Since the core supports both OHCI and EHCI functions, it must
  91. * only be reset once.
  92. *
  93. * 2. In addition to the standard SI reset sequence, the Host Control
  94. * Register must be programmed to bring the USB core and various
  95. * phy components out of reset.
  96. */
  97. if (!bcma_core_is_enabled(dev)) {
  98. bcma_core_enable(dev, 0);
  99. mdelay(10);
  100. if (dev->id.rev >= 5) {
  101. /* Enable Misc PLL */
  102. tmp = bcma_read32(dev, 0x1e0);
  103. tmp |= 0x100;
  104. bcma_write32(dev, 0x1e0, tmp);
  105. if (bcma_wait_bits(dev, 0x1e0, 1 << 24, 100))
  106. printk(KERN_EMERG "Failed to enable misc PPL!\n");
  107. /* Take out of resets */
  108. bcma_write32(dev, 0x200, 0x4ff);
  109. udelay(25);
  110. bcma_write32(dev, 0x200, 0x6ff);
  111. udelay(25);
  112. /* Make sure digital and AFE are locked in USB PHY */
  113. bcma_write32(dev, 0x524, 0x6b);
  114. udelay(50);
  115. tmp = bcma_read32(dev, 0x524);
  116. udelay(50);
  117. bcma_write32(dev, 0x524, 0xab);
  118. udelay(50);
  119. tmp = bcma_read32(dev, 0x524);
  120. udelay(50);
  121. bcma_write32(dev, 0x524, 0x2b);
  122. udelay(50);
  123. tmp = bcma_read32(dev, 0x524);
  124. udelay(50);
  125. bcma_write32(dev, 0x524, 0x10ab);
  126. udelay(50);
  127. tmp = bcma_read32(dev, 0x524);
  128. if (bcma_wait_bits(dev, 0x528, 0xc000, 10000)) {
  129. tmp = bcma_read32(dev, 0x528);
  130. printk(KERN_EMERG
  131. "USB20H mdio_rddata 0x%08x\n", tmp);
  132. }
  133. bcma_write32(dev, 0x528, 0x80000000);
  134. tmp = bcma_read32(dev, 0x314);
  135. udelay(265);
  136. bcma_write32(dev, 0x200, 0x7ff);
  137. udelay(10);
  138. /* Take USB and HSIC out of non-driving modes */
  139. bcma_write32(dev, 0x510, 0);
  140. } else {
  141. bcma_write32(dev, 0x200, 0x7ff);
  142. udelay(1);
  143. }
  144. bcma_hcd_4716wa(dev);
  145. }
  146. }
  147. static void bcma_hcd_init_chip_arm_phy(struct bcma_device *dev)
  148. {
  149. struct bcma_device *arm_core;
  150. void __iomem *dmu;
  151. arm_core = bcma_find_core(dev->bus, BCMA_CORE_ARMCA9);
  152. if (!arm_core) {
  153. dev_err(&dev->dev, "can not find ARM Cortex A9 ihost core\n");
  154. return;
  155. }
  156. dmu = ioremap_nocache(arm_core->addr_s[0], 0x1000);
  157. if (!dmu) {
  158. dev_err(&dev->dev, "can not map ARM Cortex A9 ihost core\n");
  159. return;
  160. }
  161. /* Unlock DMU PLL settings */
  162. iowrite32(0x0000ea68, dmu + 0x180);
  163. /* Write USB 2.0 PLL control setting */
  164. iowrite32(0x00dd10c3, dmu + 0x164);
  165. /* Lock DMU PLL settings */
  166. iowrite32(0x00000000, dmu + 0x180);
  167. iounmap(dmu);
  168. }
  169. static void bcma_hcd_init_chip_arm_hc(struct bcma_device *dev)
  170. {
  171. u32 val;
  172. /*
  173. * Delay after PHY initialized to ensure HC is ready to be configured
  174. */
  175. usleep_range(1000, 2000);
  176. /* Set packet buffer OUT threshold */
  177. val = bcma_read32(dev, 0x94);
  178. val &= 0xffff;
  179. val |= 0x80 << 16;
  180. bcma_write32(dev, 0x94, val);
  181. /* Enable break memory transfer */
  182. val = bcma_read32(dev, 0x9c);
  183. val |= 1;
  184. bcma_write32(dev, 0x9c, val);
  185. }
  186. static void bcma_hcd_init_chip_arm(struct bcma_device *dev)
  187. {
  188. bcma_core_enable(dev, 0);
  189. if (dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM4707 ||
  190. dev->bus->chipinfo.id == BCMA_CHIP_ID_BCM53018) {
  191. if (dev->bus->chipinfo.pkg == BCMA_PKG_ID_BCM4707 ||
  192. dev->bus->chipinfo.pkg == BCMA_PKG_ID_BCM4708)
  193. bcma_hcd_init_chip_arm_phy(dev);
  194. bcma_hcd_init_chip_arm_hc(dev);
  195. }
  196. }
  197. static void bcma_hci_platform_power_gpio(struct bcma_device *dev, bool val)
  198. {
  199. int gpio;
  200. gpio = of_get_named_gpio(dev->dev.of_node, "vcc-gpio", 0);
  201. if (!gpio_is_valid(gpio))
  202. return;
  203. if (val) {
  204. gpio_request(gpio, "bcma-hcd-gpio");
  205. gpio_set_value(gpio, 1);
  206. } else {
  207. gpio_set_value(gpio, 0);
  208. gpio_free(gpio);
  209. }
  210. }
  211. static const struct usb_ehci_pdata ehci_pdata = {
  212. };
  213. static const struct usb_ohci_pdata ohci_pdata = {
  214. };
  215. static struct platform_device *bcma_hcd_create_pdev(struct bcma_device *dev, bool ohci, u32 addr)
  216. {
  217. struct platform_device *hci_dev;
  218. struct resource hci_res[2];
  219. int ret;
  220. memset(hci_res, 0, sizeof(hci_res));
  221. hci_res[0].start = addr;
  222. hci_res[0].end = hci_res[0].start + 0x1000 - 1;
  223. hci_res[0].flags = IORESOURCE_MEM;
  224. hci_res[1].start = dev->irq;
  225. hci_res[1].flags = IORESOURCE_IRQ;
  226. hci_dev = platform_device_alloc(ohci ? "ohci-platform" :
  227. "ehci-platform" , 0);
  228. if (!hci_dev)
  229. return ERR_PTR(-ENOMEM);
  230. hci_dev->dev.parent = &dev->dev;
  231. hci_dev->dev.dma_mask = &hci_dev->dev.coherent_dma_mask;
  232. ret = platform_device_add_resources(hci_dev, hci_res,
  233. ARRAY_SIZE(hci_res));
  234. if (ret)
  235. goto err_alloc;
  236. if (ohci)
  237. ret = platform_device_add_data(hci_dev, &ohci_pdata,
  238. sizeof(ohci_pdata));
  239. else
  240. ret = platform_device_add_data(hci_dev, &ehci_pdata,
  241. sizeof(ehci_pdata));
  242. if (ret)
  243. goto err_alloc;
  244. ret = platform_device_add(hci_dev);
  245. if (ret)
  246. goto err_alloc;
  247. return hci_dev;
  248. err_alloc:
  249. platform_device_put(hci_dev);
  250. return ERR_PTR(ret);
  251. }
  252. static int bcma_hcd_probe(struct bcma_device *dev)
  253. {
  254. int err;
  255. u32 ohci_addr;
  256. struct bcma_hcd_device *usb_dev;
  257. struct bcma_chipinfo *chipinfo;
  258. chipinfo = &dev->bus->chipinfo;
  259. /* TODO: Probably need checks here; is the core connected? */
  260. if (dma_set_mask_and_coherent(dev->dma_dev, DMA_BIT_MASK(32)))
  261. return -EOPNOTSUPP;
  262. usb_dev = devm_kzalloc(&dev->dev, sizeof(struct bcma_hcd_device),
  263. GFP_KERNEL);
  264. if (!usb_dev)
  265. return -ENOMEM;
  266. bcma_hci_platform_power_gpio(dev, true);
  267. switch (dev->id.id) {
  268. case BCMA_CORE_NS_USB20:
  269. bcma_hcd_init_chip_arm(dev);
  270. break;
  271. case BCMA_CORE_USB20_HOST:
  272. bcma_hcd_init_chip_mips(dev);
  273. break;
  274. default:
  275. return -ENODEV;
  276. }
  277. /* In AI chips EHCI is addrspace 0, OHCI is 1 */
  278. ohci_addr = dev->addr_s[0];
  279. if ((chipinfo->id == BCMA_CHIP_ID_BCM5357 ||
  280. chipinfo->id == BCMA_CHIP_ID_BCM4749)
  281. && chipinfo->rev == 0)
  282. ohci_addr = 0x18009000;
  283. usb_dev->ohci_dev = bcma_hcd_create_pdev(dev, true, ohci_addr);
  284. if (IS_ERR(usb_dev->ohci_dev))
  285. return PTR_ERR(usb_dev->ohci_dev);
  286. usb_dev->ehci_dev = bcma_hcd_create_pdev(dev, false, dev->addr);
  287. if (IS_ERR(usb_dev->ehci_dev)) {
  288. err = PTR_ERR(usb_dev->ehci_dev);
  289. goto err_unregister_ohci_dev;
  290. }
  291. bcma_set_drvdata(dev, usb_dev);
  292. return 0;
  293. err_unregister_ohci_dev:
  294. platform_device_unregister(usb_dev->ohci_dev);
  295. return err;
  296. }
  297. static void bcma_hcd_remove(struct bcma_device *dev)
  298. {
  299. struct bcma_hcd_device *usb_dev = bcma_get_drvdata(dev);
  300. struct platform_device *ohci_dev = usb_dev->ohci_dev;
  301. struct platform_device *ehci_dev = usb_dev->ehci_dev;
  302. if (ohci_dev)
  303. platform_device_unregister(ohci_dev);
  304. if (ehci_dev)
  305. platform_device_unregister(ehci_dev);
  306. bcma_core_disable(dev, 0);
  307. }
  308. static void bcma_hcd_shutdown(struct bcma_device *dev)
  309. {
  310. bcma_hci_platform_power_gpio(dev, false);
  311. bcma_core_disable(dev, 0);
  312. }
  313. #ifdef CONFIG_PM
  314. static int bcma_hcd_suspend(struct bcma_device *dev)
  315. {
  316. bcma_hci_platform_power_gpio(dev, false);
  317. bcma_core_disable(dev, 0);
  318. return 0;
  319. }
  320. static int bcma_hcd_resume(struct bcma_device *dev)
  321. {
  322. bcma_hci_platform_power_gpio(dev, true);
  323. bcma_core_enable(dev, 0);
  324. return 0;
  325. }
  326. #else /* !CONFIG_PM */
  327. #define bcma_hcd_suspend NULL
  328. #define bcma_hcd_resume NULL
  329. #endif /* CONFIG_PM */
  330. static const struct bcma_device_id bcma_hcd_table[] = {
  331. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_USB20_HOST, BCMA_ANY_REV, BCMA_ANY_CLASS),
  332. BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_USB20, BCMA_ANY_REV, BCMA_ANY_CLASS),
  333. {},
  334. };
  335. MODULE_DEVICE_TABLE(bcma, bcma_hcd_table);
  336. static struct bcma_driver bcma_hcd_driver = {
  337. .name = KBUILD_MODNAME,
  338. .id_table = bcma_hcd_table,
  339. .probe = bcma_hcd_probe,
  340. .remove = bcma_hcd_remove,
  341. .shutdown = bcma_hcd_shutdown,
  342. .suspend = bcma_hcd_suspend,
  343. .resume = bcma_hcd_resume,
  344. };
  345. static int __init bcma_hcd_init(void)
  346. {
  347. return bcma_driver_register(&bcma_hcd_driver);
  348. }
  349. module_init(bcma_hcd_init);
  350. static void __exit bcma_hcd_exit(void)
  351. {
  352. bcma_driver_unregister(&bcma_hcd_driver);
  353. }
  354. module_exit(bcma_hcd_exit);