pci-layerscape.c 4.0 KB

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  1. /*
  2. * PCIe host controller driver for Freescale Layerscape SoCs
  3. *
  4. * Copyright (C) 2014 Freescale Semiconductor.
  5. *
  6. * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/delay.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/module.h>
  16. #include <linux/of_pci.h>
  17. #include <linux/of_platform.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/of_address.h>
  20. #include <linux/pci.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/resource.h>
  23. #include <linux/mfd/syscon.h>
  24. #include <linux/regmap.h>
  25. #include "pcie-designware.h"
  26. /* PEX1/2 Misc Ports Status Register */
  27. #define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
  28. #define LTSSM_STATE_SHIFT 20
  29. #define LTSSM_STATE_MASK 0x3f
  30. #define LTSSM_PCIE_L0 0x11 /* L0 state */
  31. /* Symbol Timer Register and Filter Mask Register 1 */
  32. #define PCIE_STRFMR1 0x71c
  33. struct ls_pcie {
  34. struct list_head node;
  35. struct device *dev;
  36. struct pci_bus *bus;
  37. void __iomem *dbi;
  38. struct regmap *scfg;
  39. struct pcie_port pp;
  40. int index;
  41. int msi_irq;
  42. };
  43. #define to_ls_pcie(x) container_of(x, struct ls_pcie, pp)
  44. static int ls_pcie_link_up(struct pcie_port *pp)
  45. {
  46. u32 state;
  47. struct ls_pcie *pcie = to_ls_pcie(pp);
  48. regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
  49. state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  50. if (state < LTSSM_PCIE_L0)
  51. return 0;
  52. return 1;
  53. }
  54. static int ls_pcie_establish_link(struct pcie_port *pp)
  55. {
  56. unsigned int retries;
  57. for (retries = 0; retries < 200; retries++) {
  58. if (dw_pcie_link_up(pp))
  59. return 0;
  60. usleep_range(100, 1000);
  61. }
  62. dev_err(pp->dev, "phy link never came up\n");
  63. return -EINVAL;
  64. }
  65. static void ls_pcie_host_init(struct pcie_port *pp)
  66. {
  67. struct ls_pcie *pcie = to_ls_pcie(pp);
  68. u32 val;
  69. dw_pcie_setup_rc(pp);
  70. ls_pcie_establish_link(pp);
  71. /*
  72. * LS1021A Workaround for internal TKT228622
  73. * to fix the INTx hang issue
  74. */
  75. val = ioread32(pcie->dbi + PCIE_STRFMR1);
  76. val &= 0xffff;
  77. iowrite32(val, pcie->dbi + PCIE_STRFMR1);
  78. }
  79. static struct pcie_host_ops ls_pcie_host_ops = {
  80. .link_up = ls_pcie_link_up,
  81. .host_init = ls_pcie_host_init,
  82. };
  83. static int ls_add_pcie_port(struct ls_pcie *pcie)
  84. {
  85. struct pcie_port *pp;
  86. int ret;
  87. pp = &pcie->pp;
  88. pp->dev = pcie->dev;
  89. pp->dbi_base = pcie->dbi;
  90. pp->root_bus_nr = -1;
  91. pp->ops = &ls_pcie_host_ops;
  92. ret = dw_pcie_host_init(pp);
  93. if (ret) {
  94. dev_err(pp->dev, "failed to initialize host\n");
  95. return ret;
  96. }
  97. return 0;
  98. }
  99. static int __init ls_pcie_probe(struct platform_device *pdev)
  100. {
  101. struct ls_pcie *pcie;
  102. struct resource *dbi_base;
  103. u32 index[2];
  104. int ret;
  105. pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
  106. if (!pcie)
  107. return -ENOMEM;
  108. pcie->dev = &pdev->dev;
  109. dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
  110. pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base);
  111. if (IS_ERR(pcie->dbi)) {
  112. dev_err(&pdev->dev, "missing *regs* space\n");
  113. return PTR_ERR(pcie->dbi);
  114. }
  115. pcie->scfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
  116. "fsl,pcie-scfg");
  117. if (IS_ERR(pcie->scfg)) {
  118. dev_err(&pdev->dev, "No syscfg phandle specified\n");
  119. return PTR_ERR(pcie->scfg);
  120. }
  121. ret = of_property_read_u32_array(pdev->dev.of_node,
  122. "fsl,pcie-scfg", index, 2);
  123. if (ret)
  124. return ret;
  125. pcie->index = index[1];
  126. ret = ls_add_pcie_port(pcie);
  127. if (ret < 0)
  128. return ret;
  129. platform_set_drvdata(pdev, pcie);
  130. return 0;
  131. }
  132. static const struct of_device_id ls_pcie_of_match[] = {
  133. { .compatible = "fsl,ls1021a-pcie" },
  134. { },
  135. };
  136. MODULE_DEVICE_TABLE(of, ls_pcie_of_match);
  137. static struct platform_driver ls_pcie_driver = {
  138. .driver = {
  139. .name = "layerscape-pcie",
  140. .of_match_table = ls_pcie_of_match,
  141. },
  142. };
  143. module_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);
  144. MODULE_AUTHOR("Minghuan Lian <Minghuan.Lian@freescale.com>");
  145. MODULE_DESCRIPTION("Freescale Layerscape PCIe host controller driver");
  146. MODULE_LICENSE("GPL v2");