mac.c 23 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. ****************************************************************************/
  29. #include "../wifi.h"
  30. #include "../pci.h"
  31. #include "../usb.h"
  32. #include "../ps.h"
  33. #include "../cam.h"
  34. #include "../stats.h"
  35. #include "reg.h"
  36. #include "def.h"
  37. #include "phy.h"
  38. #include "rf.h"
  39. #include "dm.h"
  40. #include "mac.h"
  41. #include "trx.h"
  42. #include "../rtl8192c/fw_common.h"
  43. #include <linux/module.h>
  44. /* macro to shorten lines */
  45. #define LINK_Q ui_link_quality
  46. #define RX_EVM rx_evm_percentage
  47. #define RX_SIGQ rx_mimo_sig_qual
  48. void rtl92c_read_chip_version(struct ieee80211_hw *hw)
  49. {
  50. struct rtl_priv *rtlpriv = rtl_priv(hw);
  51. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  52. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  53. enum version_8192c chip_version = VERSION_UNKNOWN;
  54. const char *versionid;
  55. u32 value32;
  56. value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
  57. if (value32 & TRP_VAUX_EN) {
  58. chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
  59. VERSION_TEST_CHIP_88C;
  60. } else {
  61. /* Normal mass production chip. */
  62. chip_version = NORMAL_CHIP;
  63. chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
  64. chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
  65. if (IS_VENDOR_UMC(chip_version))
  66. chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
  67. CHIP_VENDOR_UMC_B_CUT : 0);
  68. if (IS_92C_SERIAL(chip_version)) {
  69. value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
  70. chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
  71. CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
  72. }
  73. }
  74. rtlhal->version = (enum version_8192c)chip_version;
  75. pr_info("Chip version 0x%x\n", chip_version);
  76. switch (rtlhal->version) {
  77. case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
  78. versionid = "NORMAL_B_CHIP_92C";
  79. break;
  80. case VERSION_NORMAL_TSMC_CHIP_92C:
  81. versionid = "NORMAL_TSMC_CHIP_92C";
  82. break;
  83. case VERSION_NORMAL_TSMC_CHIP_88C:
  84. versionid = "NORMAL_TSMC_CHIP_88C";
  85. break;
  86. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
  87. versionid = "NORMAL_UMC_CHIP_i92C_1T2R_A_CUT";
  88. break;
  89. case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
  90. versionid = "NORMAL_UMC_CHIP_92C_A_CUT";
  91. break;
  92. case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
  93. versionid = "NORMAL_UMC_CHIP_88C_A_CUT";
  94. break;
  95. case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
  96. versionid = "NORMAL_UMC_CHIP_92C_1T2R_B_CUT";
  97. break;
  98. case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
  99. versionid = "NORMAL_UMC_CHIP_92C_B_CUT";
  100. break;
  101. case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
  102. versionid = "NORMAL_UMC_CHIP_88C_B_CUT";
  103. break;
  104. case VERSION_TEST_CHIP_92C:
  105. versionid = "TEST_CHIP_92C";
  106. break;
  107. case VERSION_TEST_CHIP_88C:
  108. versionid = "TEST_CHIP_88C";
  109. break;
  110. default:
  111. versionid = "UNKNOWN";
  112. break;
  113. }
  114. RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
  115. "Chip Version ID: %s\n", versionid);
  116. if (IS_92C_SERIAL(rtlhal->version))
  117. rtlphy->rf_type =
  118. (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
  119. else
  120. rtlphy->rf_type = RF_1T1R;
  121. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
  122. "Chip RF Type: %s\n",
  123. rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
  124. if (get_rf_type(rtlphy) == RF_1T1R)
  125. rtlpriv->dm.rfpath_rxenable[0] = true;
  126. else
  127. rtlpriv->dm.rfpath_rxenable[0] =
  128. rtlpriv->dm.rfpath_rxenable[1] = true;
  129. RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
  130. rtlhal->version);
  131. }
  132. /**
  133. * writeLLT - LLT table write access
  134. * @io: io callback
  135. * @address: LLT logical address.
  136. * @data: LLT data content
  137. *
  138. * Realtek hardware access function.
  139. *
  140. */
  141. bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
  142. {
  143. struct rtl_priv *rtlpriv = rtl_priv(hw);
  144. bool status = true;
  145. long count = 0;
  146. u32 value = _LLT_INIT_ADDR(address) |
  147. _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
  148. rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
  149. do {
  150. value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
  151. if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
  152. break;
  153. if (count > POLLING_LLT_THRESHOLD) {
  154. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  155. "Failed to polling write LLT done at address %d! _LLT_OP_VALUE(%x)\n",
  156. address, _LLT_OP_VALUE(value));
  157. status = false;
  158. break;
  159. }
  160. } while (++count);
  161. return status;
  162. }
  163. /**
  164. * rtl92c_init_LLT_table - Init LLT table
  165. * @io: io callback
  166. * @boundary:
  167. *
  168. * Realtek hardware access function.
  169. *
  170. */
  171. bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
  172. {
  173. bool rst = true;
  174. u32 i;
  175. for (i = 0; i < (boundary - 1); i++) {
  176. rst = rtl92c_llt_write(hw, i , i + 1);
  177. if (true != rst) {
  178. pr_err("===> %s #1 fail\n", __func__);
  179. return rst;
  180. }
  181. }
  182. /* end of list */
  183. rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
  184. if (true != rst) {
  185. pr_err("===> %s #2 fail\n", __func__);
  186. return rst;
  187. }
  188. /* Make the other pages as ring buffer
  189. * This ring buffer is used as beacon buffer if we config this MAC
  190. * as two MAC transfer.
  191. * Otherwise used as local loopback buffer.
  192. */
  193. for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
  194. rst = rtl92c_llt_write(hw, i, (i + 1));
  195. if (true != rst) {
  196. pr_err("===> %s #3 fail\n", __func__);
  197. return rst;
  198. }
  199. }
  200. /* Let last entry point to the start entry of ring buffer */
  201. rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
  202. if (true != rst) {
  203. pr_err("===> %s #4 fail\n", __func__);
  204. return rst;
  205. }
  206. return rst;
  207. }
  208. void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
  209. u8 *p_macaddr, bool is_group, u8 enc_algo,
  210. bool is_wepkey, bool clear_all)
  211. {
  212. struct rtl_priv *rtlpriv = rtl_priv(hw);
  213. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  214. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  215. u8 *macaddr = p_macaddr;
  216. u32 entry_id = 0;
  217. bool is_pairwise = false;
  218. static u8 cam_const_addr[4][6] = {
  219. {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
  220. {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
  221. {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
  222. {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
  223. };
  224. static u8 cam_const_broad[] = {
  225. 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
  226. };
  227. if (clear_all) {
  228. u8 idx = 0;
  229. u8 cam_offset = 0;
  230. u8 clear_number = 5;
  231. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
  232. for (idx = 0; idx < clear_number; idx++) {
  233. rtl_cam_mark_invalid(hw, cam_offset + idx);
  234. rtl_cam_empty_entry(hw, cam_offset + idx);
  235. if (idx < 5) {
  236. memset(rtlpriv->sec.key_buf[idx], 0,
  237. MAX_KEY_LEN);
  238. rtlpriv->sec.key_len[idx] = 0;
  239. }
  240. }
  241. } else {
  242. switch (enc_algo) {
  243. case WEP40_ENCRYPTION:
  244. enc_algo = CAM_WEP40;
  245. break;
  246. case WEP104_ENCRYPTION:
  247. enc_algo = CAM_WEP104;
  248. break;
  249. case TKIP_ENCRYPTION:
  250. enc_algo = CAM_TKIP;
  251. break;
  252. case AESCCMP_ENCRYPTION:
  253. enc_algo = CAM_AES;
  254. break;
  255. default:
  256. RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  257. "illegal switch case\n");
  258. enc_algo = CAM_TKIP;
  259. break;
  260. }
  261. if (is_wepkey || rtlpriv->sec.use_defaultkey) {
  262. macaddr = cam_const_addr[key_index];
  263. entry_id = key_index;
  264. } else {
  265. if (is_group) {
  266. macaddr = cam_const_broad;
  267. entry_id = key_index;
  268. } else {
  269. if (mac->opmode == NL80211_IFTYPE_AP ||
  270. mac->opmode == NL80211_IFTYPE_MESH_POINT) {
  271. entry_id = rtl_cam_get_free_entry(hw,
  272. p_macaddr);
  273. if (entry_id >= TOTAL_CAM_ENTRY) {
  274. RT_TRACE(rtlpriv, COMP_SEC,
  275. DBG_EMERG,
  276. "Can not find free hw security cam entry\n");
  277. return;
  278. }
  279. } else {
  280. entry_id = CAM_PAIRWISE_KEY_POSITION;
  281. }
  282. key_index = PAIRWISE_KEYIDX;
  283. is_pairwise = true;
  284. }
  285. }
  286. if (rtlpriv->sec.key_len[key_index] == 0) {
  287. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  288. "delete one entry\n");
  289. if (mac->opmode == NL80211_IFTYPE_AP ||
  290. mac->opmode == NL80211_IFTYPE_MESH_POINT)
  291. rtl_cam_del_entry(hw, p_macaddr);
  292. rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
  293. } else {
  294. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  295. "The insert KEY length is %d\n",
  296. rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
  297. RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
  298. "The insert KEY is %x %x\n",
  299. rtlpriv->sec.key_buf[0][0],
  300. rtlpriv->sec.key_buf[0][1]);
  301. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  302. "add one entry\n");
  303. if (is_pairwise) {
  304. RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
  305. "Pairwise Key content",
  306. rtlpriv->sec.pairwise_key,
  307. rtlpriv->sec.
  308. key_len[PAIRWISE_KEYIDX]);
  309. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  310. "set Pairwise key\n");
  311. rtl_cam_add_one_entry(hw, macaddr, key_index,
  312. entry_id, enc_algo,
  313. CAM_CONFIG_NO_USEDK,
  314. rtlpriv->sec.
  315. key_buf[key_index]);
  316. } else {
  317. RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
  318. "set group key\n");
  319. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  320. rtl_cam_add_one_entry(hw,
  321. rtlefuse->dev_addr,
  322. PAIRWISE_KEYIDX,
  323. CAM_PAIRWISE_KEY_POSITION,
  324. enc_algo,
  325. CAM_CONFIG_NO_USEDK,
  326. rtlpriv->sec.key_buf
  327. [entry_id]);
  328. }
  329. rtl_cam_add_one_entry(hw, macaddr, key_index,
  330. entry_id, enc_algo,
  331. CAM_CONFIG_NO_USEDK,
  332. rtlpriv->sec.key_buf[entry_id]);
  333. }
  334. }
  335. }
  336. }
  337. u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
  338. {
  339. struct rtl_priv *rtlpriv = rtl_priv(hw);
  340. return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
  341. }
  342. void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
  343. {
  344. struct rtl_priv *rtlpriv = rtl_priv(hw);
  345. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  346. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  347. struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
  348. if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
  349. rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
  350. 0xFFFFFFFF);
  351. rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
  352. 0xFFFFFFFF);
  353. } else {
  354. rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
  355. 0xFFFFFFFF);
  356. rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
  357. 0xFFFFFFFF);
  358. }
  359. }
  360. void rtl92c_init_interrupt(struct ieee80211_hw *hw)
  361. {
  362. rtl92c_enable_interrupt(hw);
  363. }
  364. void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
  365. {
  366. struct rtl_priv *rtlpriv = rtl_priv(hw);
  367. rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
  368. rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
  369. }
  370. void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
  371. {
  372. struct rtl_priv *rtlpriv = rtl_priv(hw);
  373. rtl92c_dm_init_edca_turbo(hw);
  374. rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM, (u8 *)&aci);
  375. }
  376. void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
  377. {
  378. struct rtl_priv *rtlpriv = rtl_priv(hw);
  379. rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
  380. }
  381. int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
  382. {
  383. u8 value;
  384. struct rtl_priv *rtlpriv = rtl_priv(hw);
  385. switch (type) {
  386. case NL80211_IFTYPE_UNSPECIFIED:
  387. value = NT_NO_LINK;
  388. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  389. "Set Network type to NO LINK!\n");
  390. break;
  391. case NL80211_IFTYPE_ADHOC:
  392. value = NT_LINK_AD_HOC;
  393. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  394. "Set Network type to Ad Hoc!\n");
  395. break;
  396. case NL80211_IFTYPE_STATION:
  397. value = NT_LINK_AP;
  398. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  399. "Set Network type to STA!\n");
  400. break;
  401. case NL80211_IFTYPE_AP:
  402. value = NT_AS_AP;
  403. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  404. "Set Network type to AP!\n");
  405. break;
  406. default:
  407. RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
  408. "Network type %d not supported!\n", type);
  409. return -EOPNOTSUPP;
  410. }
  411. rtl_write_byte(rtlpriv, MSR, value);
  412. return 0;
  413. }
  414. void rtl92c_init_network_type(struct ieee80211_hw *hw)
  415. {
  416. rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
  417. }
  418. void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
  419. {
  420. u16 value16;
  421. u32 value32;
  422. struct rtl_priv *rtlpriv = rtl_priv(hw);
  423. /* Response Rate Set */
  424. value32 = rtl_read_dword(rtlpriv, REG_RRSR);
  425. value32 &= ~RATE_BITMAP_ALL;
  426. value32 |= RATE_RRSR_CCK_ONLY_1M;
  427. rtl_write_dword(rtlpriv, REG_RRSR, value32);
  428. /* SIFS (used in NAV) */
  429. value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
  430. rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
  431. /* Retry Limit */
  432. value16 = _LRL(0x30) | _SRL(0x30);
  433. rtl_write_dword(rtlpriv, REG_RL, value16);
  434. }
  435. void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
  436. {
  437. struct rtl_priv *rtlpriv = rtl_priv(hw);
  438. /* Set Data Auto Rate Fallback Retry Count register. */
  439. rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
  440. rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
  441. rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
  442. rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
  443. }
  444. static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  445. u8 ctx_sifs)
  446. {
  447. struct rtl_priv *rtlpriv = rtl_priv(hw);
  448. rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
  449. rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
  450. }
  451. static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
  452. u8 ctx_sifs)
  453. {
  454. struct rtl_priv *rtlpriv = rtl_priv(hw);
  455. rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
  456. rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
  457. }
  458. void rtl92c_init_edca_param(struct ieee80211_hw *hw,
  459. u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
  460. {
  461. /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
  462. * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
  463. */
  464. u32 value;
  465. struct rtl_priv *rtlpriv = rtl_priv(hw);
  466. value = (u32)aifs;
  467. value |= ((u32)cw_min & 0xF) << 8;
  468. value |= ((u32)cw_max & 0xF) << 12;
  469. value |= (u32)txop << 16;
  470. /* 92C hardware register sequence is the same as queue number. */
  471. rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
  472. }
  473. void rtl92c_init_edca(struct ieee80211_hw *hw)
  474. {
  475. u16 value16;
  476. struct rtl_priv *rtlpriv = rtl_priv(hw);
  477. /* disable EDCCA count down, to reduce collison and retry */
  478. value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
  479. value16 |= DIS_EDCA_CNT_DWN;
  480. rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
  481. /* Update SIFS timing. ??????????
  482. * pHalData->SifsTime = 0x0e0e0a0a; */
  483. rtl92c_set_cck_sifs(hw, 0xa, 0xa);
  484. rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
  485. /* Set CCK/OFDM SIFS to be 10us. */
  486. rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
  487. rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
  488. rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
  489. rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
  490. /* TXOP */
  491. rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
  492. rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
  493. rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
  494. rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
  495. /* PIFS */
  496. rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
  497. /* AGGR BREAK TIME Register */
  498. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  499. rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
  500. rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
  501. rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
  502. }
  503. void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
  504. {
  505. struct rtl_priv *rtlpriv = rtl_priv(hw);
  506. rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
  507. rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
  508. /* init AMPDU aggregation number, tuning for Tx's TP, */
  509. rtl_write_word(rtlpriv, 0x4CA, 0x0708);
  510. }
  511. void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw)
  512. {
  513. struct rtl_priv *rtlpriv = rtl_priv(hw);
  514. rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
  515. }
  516. void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
  517. {
  518. struct rtl_priv *rtlpriv = rtl_priv(hw);
  519. rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
  520. rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
  521. rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
  522. }
  523. void rtl92c_init_retry_function(struct ieee80211_hw *hw)
  524. {
  525. u8 value8;
  526. struct rtl_priv *rtlpriv = rtl_priv(hw);
  527. value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
  528. value8 |= EN_AMPDU_RTY_NEW;
  529. rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
  530. /* Set ACK timeout */
  531. rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
  532. }
  533. void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
  534. {
  535. struct rtl_priv *rtlpriv = rtl_priv(hw);
  536. rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
  537. }
  538. void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
  539. {
  540. struct rtl_priv *rtlpriv = rtl_priv(hw);
  541. u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
  542. rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
  543. }
  544. /*==============================================================*/
  545. static u8 _rtl92c_query_rxpwrpercentage(char antpower)
  546. {
  547. if ((antpower <= -100) || (antpower >= 20))
  548. return 0;
  549. else if (antpower >= 0)
  550. return 100;
  551. else
  552. return 100 + antpower;
  553. }
  554. static u8 _rtl92c_evm_db_to_percentage(char value)
  555. {
  556. char ret_val;
  557. ret_val = value;
  558. if (ret_val >= 0)
  559. ret_val = 0;
  560. if (ret_val <= -33)
  561. ret_val = -33;
  562. ret_val = 0 - ret_val;
  563. ret_val *= 3;
  564. if (ret_val == 99)
  565. ret_val = 100;
  566. return ret_val;
  567. }
  568. static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
  569. long currsig)
  570. {
  571. long retsig;
  572. if (currsig >= 61 && currsig <= 100)
  573. retsig = 90 + ((currsig - 60) / 4);
  574. else if (currsig >= 41 && currsig <= 60)
  575. retsig = 78 + ((currsig - 40) / 2);
  576. else if (currsig >= 31 && currsig <= 40)
  577. retsig = 66 + (currsig - 30);
  578. else if (currsig >= 21 && currsig <= 30)
  579. retsig = 54 + (currsig - 20);
  580. else if (currsig >= 5 && currsig <= 20)
  581. retsig = 42 + (((currsig - 5) * 2) / 3);
  582. else if (currsig == 4)
  583. retsig = 36;
  584. else if (currsig == 3)
  585. retsig = 27;
  586. else if (currsig == 2)
  587. retsig = 18;
  588. else if (currsig == 1)
  589. retsig = 9;
  590. else
  591. retsig = currsig;
  592. return retsig;
  593. }
  594. static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
  595. struct rtl_stats *pstats,
  596. struct rx_desc_92c *p_desc,
  597. struct rx_fwinfo_92c *p_drvinfo,
  598. bool packet_match_bssid,
  599. bool packet_toself,
  600. bool packet_beacon)
  601. {
  602. struct rtl_priv *rtlpriv = rtl_priv(hw);
  603. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  604. struct phy_sts_cck_8192s_t *cck_buf;
  605. s8 rx_pwr_all = 0, rx_pwr[4];
  606. u8 rf_rx_num = 0, evm, pwdb_all;
  607. u8 i, max_spatial_stream;
  608. u32 rssi, total_rssi = 0;
  609. bool in_powersavemode = false;
  610. bool is_cck_rate;
  611. u8 *pdesc = (u8 *)p_desc;
  612. is_cck_rate = RX_HAL_IS_CCK_RATE(p_desc->rxmcs);
  613. pstats->packet_matchbssid = packet_match_bssid;
  614. pstats->packet_toself = packet_toself;
  615. pstats->packet_beacon = packet_beacon;
  616. pstats->is_cck = is_cck_rate;
  617. pstats->RX_SIGQ[0] = -1;
  618. pstats->RX_SIGQ[1] = -1;
  619. if (is_cck_rate) {
  620. u8 report, cck_highpwr;
  621. cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
  622. if (!in_powersavemode)
  623. cck_highpwr = rtlphy->cck_high_power;
  624. else
  625. cck_highpwr = false;
  626. if (!cck_highpwr) {
  627. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  628. report = cck_buf->cck_agc_rpt & 0xc0;
  629. report = report >> 6;
  630. switch (report) {
  631. case 0x3:
  632. rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
  633. break;
  634. case 0x2:
  635. rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
  636. break;
  637. case 0x1:
  638. rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
  639. break;
  640. case 0x0:
  641. rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
  642. break;
  643. }
  644. } else {
  645. u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
  646. report = p_drvinfo->cfosho[0] & 0x60;
  647. report = report >> 5;
  648. switch (report) {
  649. case 0x3:
  650. rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
  651. break;
  652. case 0x2:
  653. rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
  654. break;
  655. case 0x1:
  656. rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
  657. break;
  658. case 0x0:
  659. rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
  660. break;
  661. }
  662. }
  663. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  664. pstats->rx_pwdb_all = pwdb_all;
  665. pstats->recvsignalpower = rx_pwr_all;
  666. if (packet_match_bssid) {
  667. u8 sq;
  668. if (pstats->rx_pwdb_all > 40)
  669. sq = 100;
  670. else {
  671. sq = cck_buf->sq_rpt;
  672. if (sq > 64)
  673. sq = 0;
  674. else if (sq < 20)
  675. sq = 100;
  676. else
  677. sq = ((64 - sq) * 100) / 44;
  678. }
  679. pstats->signalquality = sq;
  680. pstats->RX_SIGQ[0] = sq;
  681. pstats->RX_SIGQ[1] = -1;
  682. }
  683. } else {
  684. rtlpriv->dm.rfpath_rxenable[0] =
  685. rtlpriv->dm.rfpath_rxenable[1] = true;
  686. for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
  687. if (rtlpriv->dm.rfpath_rxenable[i])
  688. rf_rx_num++;
  689. rx_pwr[i] =
  690. ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
  691. rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
  692. total_rssi += rssi;
  693. rtlpriv->stats.rx_snr_db[i] =
  694. (long)(p_drvinfo->rxsnr[i] / 2);
  695. if (packet_match_bssid)
  696. pstats->rx_mimo_signalstrength[i] = (u8) rssi;
  697. }
  698. rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
  699. pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
  700. pstats->rx_pwdb_all = pwdb_all;
  701. pstats->rxpower = rx_pwr_all;
  702. pstats->recvsignalpower = rx_pwr_all;
  703. if (GET_RX_DESC_RX_MCS(pdesc) &&
  704. GET_RX_DESC_RX_MCS(pdesc) >= DESC_RATEMCS8 &&
  705. GET_RX_DESC_RX_MCS(pdesc) <= DESC_RATEMCS15)
  706. max_spatial_stream = 2;
  707. else
  708. max_spatial_stream = 1;
  709. for (i = 0; i < max_spatial_stream; i++) {
  710. evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
  711. if (packet_match_bssid) {
  712. if (i == 0)
  713. pstats->signalquality =
  714. (u8) (evm & 0xff);
  715. pstats->RX_SIGQ[i] =
  716. (u8) (evm & 0xff);
  717. }
  718. }
  719. }
  720. if (is_cck_rate)
  721. pstats->signalstrength =
  722. (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
  723. else if (rf_rx_num != 0)
  724. pstats->signalstrength =
  725. (u8) (_rtl92c_signal_scale_mapping
  726. (hw, total_rssi /= rf_rx_num));
  727. }
  728. void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
  729. struct sk_buff *skb,
  730. struct rtl_stats *pstats,
  731. struct rx_desc_92c *pdesc,
  732. struct rx_fwinfo_92c *p_drvinfo)
  733. {
  734. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  735. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  736. struct ieee80211_hdr *hdr;
  737. u8 *tmp_buf;
  738. u8 *praddr;
  739. __le16 fc;
  740. u16 type, cpu_fc;
  741. bool packet_matchbssid, packet_toself, packet_beacon = false;
  742. tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
  743. hdr = (struct ieee80211_hdr *)tmp_buf;
  744. fc = hdr->frame_control;
  745. cpu_fc = le16_to_cpu(fc);
  746. type = WLAN_FC_GET_TYPE(fc);
  747. praddr = hdr->addr1;
  748. packet_matchbssid =
  749. ((IEEE80211_FTYPE_CTL != type) &&
  750. ether_addr_equal(mac->bssid,
  751. (cpu_fc & IEEE80211_FCTL_TODS) ? hdr->addr1 :
  752. (cpu_fc & IEEE80211_FCTL_FROMDS) ? hdr->addr2 :
  753. hdr->addr3) &&
  754. (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
  755. packet_toself = packet_matchbssid &&
  756. ether_addr_equal(praddr, rtlefuse->dev_addr);
  757. if (ieee80211_is_beacon(fc))
  758. packet_beacon = true;
  759. _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
  760. packet_matchbssid, packet_toself,
  761. packet_beacon);
  762. rtl_process_phyinfo(hw, tmp_buf, pstats);
  763. }