rt2800lib.c 246 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658165916601661166216631664166516661667166816691670167116721673167416751676167716781679168016811682168316841685168616871688168916901691169216931694169516961697169816991700170117021703170417051706170717081709171017111712171317141715171617171718171917201721172217231724172517261727172817291730173117321733173417351736173717381739174017411742174317441745174617471748174917501751175217531754175517561757175817591760176117621763176417651766176717681769177017711772177317741775177617771778177917801781178217831784178517861787178817891790179117921793179417951796179717981799180018011802180318041805180618071808180918101811181218131814181518161817181818191820182118221823182418251826182718281829183018311832183318341835183618371838183918401841184218431844184518461847184818491850185118521853185418551856185718581859186018611862186318641865186618671868186918701871187218731874187518761877187818791880188118821883188418851886188718881889189018911892189318941895189618971898189919001901190219031904190519061907190819091910191119121913191419151916191719181919192019211922192319241925192619271928192919301931193219331934193519361937193819391940194119421943194419451946194719481949195019511952195319541955195619571958195919601961196219631964196519661967196819691970197119721973197419751976197719781979198019811982198319841985198619871988198919901991199219931994199519961997199819992000200120022003200420052006200720082009201020112012201320142015201620172018201920202021202220232024202520262027202820292030203120322033203420352036203720382039204020412042204320442045204620472048204920502051205220532054205520562057205820592060206120622063206420652066206720682069207020712072207320742075207620772078207920802081208220832084208520862087208820892090209120922093209420952096209720982099210021012102210321042105210621072108210921102111211221132114211521162117211821192120212121222123212421252126212721282129213021312132213321342135213621372138213921402141214221432144214521462147214821492150215121522153215421552156215721582159216021612162216321642165216621672168216921702171217221732174217521762177217821792180218121822183218421852186218721882189219021912192219321942195219621972198219922002201220222032204220522062207220822092210221122122213221422152216221722182219222022212222222322242225222622272228222922302231223222332234223522362237223822392240224122422243224422452246224722482249225022512252225322542255225622572258225922602261226222632264226522662267226822692270227122722273227422752276227722782279228022812282228322842285228622872288228922902291229222932294229522962297229822992300230123022303230423052306230723082309231023112312231323142315231623172318231923202321232223232324232523262327232823292330233123322333233423352336233723382339234023412342234323442345234623472348234923502351235223532354235523562357235823592360236123622363236423652366236723682369237023712372237323742375237623772378237923802381238223832384238523862387238823892390239123922393239423952396239723982399240024012402240324042405240624072408240924102411241224132414241524162417241824192420242124222423242424252426242724282429243024312432243324342435243624372438243924402441244224432444244524462447244824492450245124522453245424552456245724582459246024612462246324642465246624672468246924702471247224732474247524762477247824792480248124822483248424852486248724882489249024912492249324942495249624972498249925002501250225032504250525062507250825092510251125122513251425152516251725182519252025212522252325242525252625272528252925302531253225332534253525362537253825392540254125422543254425452546254725482549255025512552255325542555255625572558255925602561256225632564256525662567256825692570257125722573257425752576257725782579258025812582258325842585258625872588258925902591259225932594259525962597259825992600260126022603260426052606260726082609261026112612261326142615261626172618261926202621262226232624262526262627262826292630263126322633263426352636263726382639264026412642264326442645264626472648264926502651265226532654265526562657265826592660266126622663266426652666266726682669267026712672267326742675267626772678267926802681268226832684268526862687268826892690269126922693269426952696269726982699270027012702270327042705270627072708270927102711271227132714271527162717271827192720272127222723272427252726272727282729273027312732273327342735273627372738273927402741274227432744274527462747274827492750275127522753275427552756275727582759276027612762276327642765276627672768276927702771277227732774277527762777277827792780278127822783278427852786278727882789279027912792279327942795279627972798279928002801280228032804280528062807280828092810281128122813281428152816281728182819282028212822282328242825282628272828282928302831283228332834283528362837283828392840284128422843284428452846284728482849285028512852285328542855285628572858285928602861286228632864286528662867286828692870287128722873287428752876287728782879288028812882288328842885288628872888288928902891289228932894289528962897289828992900290129022903290429052906290729082909291029112912291329142915291629172918291929202921292229232924292529262927292829292930293129322933293429352936293729382939294029412942294329442945294629472948294929502951295229532954295529562957295829592960296129622963296429652966296729682969297029712972297329742975297629772978297929802981298229832984298529862987298829892990299129922993299429952996299729982999300030013002300330043005300630073008300930103011301230133014301530163017301830193020302130223023302430253026302730283029303030313032303330343035303630373038303930403041304230433044304530463047304830493050305130523053305430553056305730583059306030613062306330643065306630673068306930703071307230733074307530763077307830793080308130823083308430853086308730883089309030913092309330943095309630973098309931003101310231033104310531063107310831093110311131123113311431153116311731183119312031213122312331243125312631273128312931303131313231333134313531363137313831393140314131423143314431453146314731483149315031513152315331543155315631573158315931603161316231633164316531663167316831693170317131723173317431753176317731783179318031813182318331843185318631873188318931903191319231933194319531963197319831993200320132023203320432053206320732083209321032113212321332143215321632173218321932203221322232233224322532263227322832293230323132323233323432353236323732383239324032413242324332443245324632473248324932503251325232533254325532563257325832593260326132623263326432653266326732683269327032713272327332743275327632773278327932803281328232833284328532863287328832893290329132923293329432953296329732983299330033013302330333043305330633073308330933103311331233133314331533163317331833193320332133223323332433253326332733283329333033313332333333343335333633373338333933403341334233433344334533463347334833493350335133523353335433553356335733583359336033613362336333643365336633673368336933703371337233733374337533763377337833793380338133823383338433853386338733883389339033913392339333943395339633973398339934003401340234033404340534063407340834093410341134123413341434153416341734183419342034213422342334243425342634273428342934303431343234333434343534363437343834393440344134423443344434453446344734483449345034513452345334543455345634573458345934603461346234633464346534663467346834693470347134723473347434753476347734783479348034813482348334843485348634873488348934903491349234933494349534963497349834993500350135023503350435053506350735083509351035113512351335143515351635173518351935203521352235233524352535263527352835293530353135323533353435353536353735383539354035413542354335443545354635473548354935503551355235533554355535563557355835593560356135623563356435653566356735683569357035713572357335743575357635773578357935803581358235833584358535863587358835893590359135923593359435953596359735983599360036013602360336043605360636073608360936103611361236133614361536163617361836193620362136223623362436253626362736283629363036313632363336343635363636373638363936403641364236433644364536463647364836493650365136523653365436553656365736583659366036613662366336643665366636673668366936703671367236733674367536763677367836793680368136823683368436853686368736883689369036913692369336943695369636973698369937003701370237033704370537063707370837093710371137123713371437153716371737183719372037213722372337243725372637273728372937303731373237333734373537363737373837393740374137423743374437453746374737483749375037513752375337543755375637573758375937603761376237633764376537663767376837693770377137723773377437753776377737783779378037813782378337843785378637873788378937903791379237933794379537963797379837993800380138023803380438053806380738083809381038113812381338143815381638173818381938203821382238233824382538263827382838293830383138323833383438353836383738383839384038413842384338443845384638473848384938503851385238533854385538563857385838593860386138623863386438653866386738683869387038713872387338743875387638773878387938803881388238833884388538863887388838893890389138923893389438953896389738983899390039013902390339043905390639073908390939103911391239133914391539163917391839193920392139223923392439253926392739283929393039313932393339343935393639373938393939403941394239433944394539463947394839493950395139523953395439553956395739583959396039613962396339643965396639673968396939703971397239733974397539763977397839793980398139823983398439853986398739883989399039913992399339943995399639973998399940004001400240034004400540064007400840094010401140124013401440154016401740184019402040214022402340244025402640274028402940304031403240334034403540364037403840394040404140424043404440454046404740484049405040514052405340544055405640574058405940604061406240634064406540664067406840694070407140724073407440754076407740784079408040814082408340844085408640874088408940904091409240934094409540964097409840994100410141024103410441054106410741084109411041114112411341144115411641174118411941204121412241234124412541264127412841294130413141324133413441354136413741384139414041414142414341444145414641474148414941504151415241534154415541564157415841594160416141624163416441654166416741684169417041714172417341744175417641774178417941804181418241834184418541864187418841894190419141924193419441954196419741984199420042014202420342044205420642074208420942104211421242134214421542164217421842194220422142224223422442254226422742284229423042314232423342344235423642374238423942404241424242434244424542464247424842494250425142524253425442554256425742584259426042614262426342644265426642674268426942704271427242734274427542764277427842794280428142824283428442854286428742884289429042914292429342944295429642974298429943004301430243034304430543064307430843094310431143124313431443154316431743184319432043214322432343244325432643274328432943304331433243334334433543364337433843394340434143424343434443454346434743484349435043514352435343544355435643574358435943604361436243634364436543664367436843694370437143724373437443754376437743784379438043814382438343844385438643874388438943904391439243934394439543964397439843994400440144024403440444054406440744084409441044114412441344144415441644174418441944204421442244234424442544264427442844294430443144324433443444354436443744384439444044414442444344444445444644474448444944504451445244534454445544564457445844594460446144624463446444654466446744684469447044714472447344744475447644774478447944804481448244834484448544864487448844894490449144924493449444954496449744984499450045014502450345044505450645074508450945104511451245134514451545164517451845194520452145224523452445254526452745284529453045314532453345344535453645374538453945404541454245434544454545464547454845494550455145524553455445554556455745584559456045614562456345644565456645674568456945704571457245734574457545764577457845794580458145824583458445854586458745884589459045914592459345944595459645974598459946004601460246034604460546064607460846094610461146124613461446154616461746184619462046214622462346244625462646274628462946304631463246334634463546364637463846394640464146424643464446454646464746484649465046514652465346544655465646574658465946604661466246634664466546664667466846694670467146724673467446754676467746784679468046814682468346844685468646874688468946904691469246934694469546964697469846994700470147024703470447054706470747084709471047114712471347144715471647174718471947204721472247234724472547264727472847294730473147324733473447354736473747384739474047414742474347444745474647474748474947504751475247534754475547564757475847594760476147624763476447654766476747684769477047714772477347744775477647774778477947804781478247834784478547864787478847894790479147924793479447954796479747984799480048014802480348044805480648074808480948104811481248134814481548164817481848194820482148224823482448254826482748284829483048314832483348344835483648374838483948404841484248434844484548464847484848494850485148524853485448554856485748584859486048614862486348644865486648674868486948704871487248734874487548764877487848794880488148824883488448854886488748884889489048914892489348944895489648974898489949004901490249034904490549064907490849094910491149124913491449154916491749184919492049214922492349244925492649274928492949304931493249334934493549364937493849394940494149424943494449454946494749484949495049514952495349544955495649574958495949604961496249634964496549664967496849694970497149724973497449754976497749784979498049814982498349844985498649874988498949904991499249934994499549964997499849995000500150025003500450055006500750085009501050115012501350145015501650175018501950205021502250235024502550265027502850295030503150325033503450355036503750385039504050415042504350445045504650475048504950505051505250535054505550565057505850595060506150625063506450655066506750685069507050715072507350745075507650775078507950805081508250835084508550865087508850895090509150925093509450955096509750985099510051015102510351045105510651075108510951105111511251135114511551165117511851195120512151225123512451255126512751285129513051315132513351345135513651375138513951405141514251435144514551465147514851495150515151525153515451555156515751585159516051615162516351645165516651675168516951705171517251735174517551765177517851795180518151825183518451855186518751885189519051915192519351945195519651975198519952005201520252035204520552065207520852095210521152125213521452155216521752185219522052215222522352245225522652275228522952305231523252335234523552365237523852395240524152425243524452455246524752485249525052515252525352545255525652575258525952605261526252635264526552665267526852695270527152725273527452755276527752785279528052815282528352845285528652875288528952905291529252935294529552965297529852995300530153025303530453055306530753085309531053115312531353145315531653175318531953205321532253235324532553265327532853295330533153325333533453355336533753385339534053415342534353445345534653475348534953505351535253535354535553565357535853595360536153625363536453655366536753685369537053715372537353745375537653775378537953805381538253835384538553865387538853895390539153925393539453955396539753985399540054015402540354045405540654075408540954105411541254135414541554165417541854195420542154225423542454255426542754285429543054315432543354345435543654375438543954405441544254435444544554465447544854495450545154525453545454555456545754585459546054615462546354645465546654675468546954705471547254735474547554765477547854795480548154825483548454855486548754885489549054915492549354945495549654975498549955005501550255035504550555065507550855095510551155125513551455155516551755185519552055215522552355245525552655275528552955305531553255335534553555365537553855395540554155425543554455455546554755485549555055515552555355545555555655575558555955605561556255635564556555665567556855695570557155725573557455755576557755785579558055815582558355845585558655875588558955905591559255935594559555965597559855995600560156025603560456055606560756085609561056115612561356145615561656175618561956205621562256235624562556265627562856295630563156325633563456355636563756385639564056415642564356445645564656475648564956505651565256535654565556565657565856595660566156625663566456655666566756685669567056715672567356745675567656775678567956805681568256835684568556865687568856895690569156925693569456955696569756985699570057015702570357045705570657075708570957105711571257135714571557165717571857195720572157225723572457255726572757285729573057315732573357345735573657375738573957405741574257435744574557465747574857495750575157525753575457555756575757585759576057615762576357645765576657675768576957705771577257735774577557765777577857795780578157825783578457855786578757885789579057915792579357945795579657975798579958005801580258035804580558065807580858095810581158125813581458155816581758185819582058215822582358245825582658275828582958305831583258335834583558365837583858395840584158425843584458455846584758485849585058515852585358545855585658575858585958605861586258635864586558665867586858695870587158725873587458755876587758785879588058815882588358845885588658875888588958905891589258935894589558965897589858995900590159025903590459055906590759085909591059115912591359145915591659175918591959205921592259235924592559265927592859295930593159325933593459355936593759385939594059415942594359445945594659475948594959505951595259535954595559565957595859595960596159625963596459655966596759685969597059715972597359745975597659775978597959805981598259835984598559865987598859895990599159925993599459955996599759985999600060016002600360046005600660076008600960106011601260136014601560166017601860196020602160226023602460256026602760286029603060316032603360346035603660376038603960406041604260436044604560466047604860496050605160526053605460556056605760586059606060616062606360646065606660676068606960706071607260736074607560766077607860796080608160826083608460856086608760886089609060916092609360946095609660976098609961006101610261036104610561066107610861096110611161126113611461156116611761186119612061216122612361246125612661276128612961306131613261336134613561366137613861396140614161426143614461456146614761486149615061516152615361546155615661576158615961606161616261636164616561666167616861696170617161726173617461756176617761786179618061816182618361846185618661876188618961906191619261936194619561966197619861996200620162026203620462056206620762086209621062116212621362146215621662176218621962206221622262236224622562266227622862296230623162326233623462356236623762386239624062416242624362446245624662476248624962506251625262536254625562566257625862596260626162626263626462656266626762686269627062716272627362746275627662776278627962806281628262836284628562866287628862896290629162926293629462956296629762986299630063016302630363046305630663076308630963106311631263136314631563166317631863196320632163226323632463256326632763286329633063316332633363346335633663376338633963406341634263436344634563466347634863496350635163526353635463556356635763586359636063616362636363646365636663676368636963706371637263736374637563766377637863796380638163826383638463856386638763886389639063916392639363946395639663976398639964006401640264036404640564066407640864096410641164126413641464156416641764186419642064216422642364246425642664276428642964306431643264336434643564366437643864396440644164426443644464456446644764486449645064516452645364546455645664576458645964606461646264636464646564666467646864696470647164726473647464756476647764786479648064816482648364846485648664876488648964906491649264936494649564966497649864996500650165026503650465056506650765086509651065116512651365146515651665176518651965206521652265236524652565266527652865296530653165326533653465356536653765386539654065416542654365446545654665476548654965506551655265536554655565566557655865596560656165626563656465656566656765686569657065716572657365746575657665776578657965806581658265836584658565866587658865896590659165926593659465956596659765986599660066016602660366046605660666076608660966106611661266136614661566166617661866196620662166226623662466256626662766286629663066316632663366346635663666376638663966406641664266436644664566466647664866496650665166526653665466556656665766586659666066616662666366646665666666676668666966706671667266736674667566766677667866796680668166826683668466856686668766886689669066916692669366946695669666976698669967006701670267036704670567066707670867096710671167126713671467156716671767186719672067216722672367246725672667276728672967306731673267336734673567366737673867396740674167426743674467456746674767486749675067516752675367546755675667576758675967606761676267636764676567666767676867696770677167726773677467756776677767786779678067816782678367846785678667876788678967906791679267936794679567966797679867996800680168026803680468056806680768086809681068116812681368146815681668176818681968206821682268236824682568266827682868296830683168326833683468356836683768386839684068416842684368446845684668476848684968506851685268536854685568566857685868596860686168626863686468656866686768686869687068716872687368746875687668776878687968806881688268836884688568866887688868896890689168926893689468956896689768986899690069016902690369046905690669076908690969106911691269136914691569166917691869196920692169226923692469256926692769286929693069316932693369346935693669376938693969406941694269436944694569466947694869496950695169526953695469556956695769586959696069616962696369646965696669676968696969706971697269736974697569766977697869796980698169826983698469856986698769886989699069916992699369946995699669976998699970007001700270037004700570067007700870097010701170127013701470157016701770187019702070217022702370247025702670277028702970307031703270337034703570367037703870397040704170427043704470457046704770487049705070517052705370547055705670577058705970607061706270637064706570667067706870697070707170727073707470757076707770787079708070817082708370847085708670877088708970907091709270937094709570967097709870997100710171027103710471057106710771087109711071117112711371147115711671177118711971207121712271237124712571267127712871297130713171327133713471357136713771387139714071417142714371447145714671477148714971507151715271537154715571567157715871597160716171627163716471657166716771687169717071717172717371747175717671777178717971807181718271837184718571867187718871897190719171927193719471957196719771987199720072017202720372047205720672077208720972107211721272137214721572167217721872197220722172227223722472257226722772287229723072317232723372347235723672377238723972407241724272437244724572467247724872497250725172527253725472557256725772587259726072617262726372647265726672677268726972707271727272737274727572767277727872797280728172827283728472857286728772887289729072917292729372947295729672977298729973007301730273037304730573067307730873097310731173127313731473157316731773187319732073217322732373247325732673277328732973307331733273337334733573367337733873397340734173427343734473457346734773487349735073517352735373547355735673577358735973607361736273637364736573667367736873697370737173727373737473757376737773787379738073817382738373847385738673877388738973907391739273937394739573967397739873997400740174027403740474057406740774087409741074117412741374147415741674177418741974207421742274237424742574267427742874297430743174327433743474357436743774387439744074417442744374447445744674477448744974507451745274537454745574567457745874597460746174627463746474657466746774687469747074717472747374747475747674777478747974807481748274837484748574867487748874897490749174927493749474957496749774987499750075017502750375047505750675077508750975107511751275137514751575167517751875197520752175227523752475257526752775287529753075317532753375347535753675377538753975407541754275437544754575467547754875497550755175527553755475557556755775587559756075617562756375647565756675677568756975707571757275737574757575767577757875797580758175827583758475857586758775887589759075917592759375947595759675977598759976007601760276037604760576067607760876097610761176127613761476157616761776187619762076217622762376247625762676277628762976307631763276337634763576367637763876397640764176427643764476457646764776487649765076517652765376547655765676577658765976607661766276637664766576667667766876697670767176727673767476757676767776787679768076817682768376847685768676877688768976907691769276937694769576967697769876997700770177027703770477057706770777087709771077117712771377147715771677177718771977207721772277237724772577267727772877297730773177327733773477357736773777387739774077417742774377447745774677477748774977507751775277537754775577567757775877597760776177627763776477657766776777687769777077717772777377747775777677777778777977807781778277837784778577867787778877897790779177927793779477957796779777987799780078017802780378047805780678077808780978107811781278137814781578167817781878197820782178227823782478257826782778287829783078317832783378347835783678377838783978407841784278437844784578467847784878497850785178527853785478557856785778587859786078617862786378647865786678677868786978707871787278737874787578767877787878797880788178827883788478857886788778887889789078917892789378947895789678977898789979007901790279037904790579067907790879097910791179127913791479157916791779187919792079217922792379247925792679277928792979307931793279337934793579367937793879397940794179427943794479457946794779487949795079517952795379547955795679577958795979607961796279637964796579667967796879697970797179727973797479757976797779787979798079817982798379847985798679877988798979907991799279937994799579967997799879998000800180028003800480058006800780088009801080118012801380148015801680178018801980208021
  1. /*
  2. Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
  3. Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
  4. Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
  5. Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
  6. Based on the original rt2800pci.c and rt2800usb.c.
  7. Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
  8. Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  9. Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  10. Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  11. Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  12. Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  13. <http://rt2x00.serialmonkey.com>
  14. This program is free software; you can redistribute it and/or modify
  15. it under the terms of the GNU General Public License as published by
  16. the Free Software Foundation; either version 2 of the License, or
  17. (at your option) any later version.
  18. This program is distributed in the hope that it will be useful,
  19. but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. GNU General Public License for more details.
  22. You should have received a copy of the GNU General Public License
  23. along with this program; if not, see <http://www.gnu.org/licenses/>.
  24. */
  25. /*
  26. Module: rt2800lib
  27. Abstract: rt2800 generic device routines.
  28. */
  29. #include <linux/crc-ccitt.h>
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/slab.h>
  33. #include "rt2x00.h"
  34. #include "rt2800lib.h"
  35. #include "rt2800.h"
  36. /*
  37. * Register access.
  38. * All access to the CSR registers will go through the methods
  39. * rt2800_register_read and rt2800_register_write.
  40. * BBP and RF register require indirect register access,
  41. * and use the CSR registers BBPCSR and RFCSR to achieve this.
  42. * These indirect registers work with busy bits,
  43. * and we will try maximal REGISTER_BUSY_COUNT times to access
  44. * the register while taking a REGISTER_BUSY_DELAY us delay
  45. * between each attampt. When the busy bit is still set at that time,
  46. * the access attempt is considered to have failed,
  47. * and we will print an error.
  48. * The _lock versions must be used if you already hold the csr_mutex
  49. */
  50. #define WAIT_FOR_BBP(__dev, __reg) \
  51. rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  52. #define WAIT_FOR_RFCSR(__dev, __reg) \
  53. rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  54. #define WAIT_FOR_RF(__dev, __reg) \
  55. rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  56. #define WAIT_FOR_MCU(__dev, __reg) \
  57. rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  58. H2M_MAILBOX_CSR_OWNER, (__reg))
  59. static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  60. {
  61. /* check for rt2872 on SoC */
  62. if (!rt2x00_is_soc(rt2x00dev) ||
  63. !rt2x00_rt(rt2x00dev, RT2872))
  64. return false;
  65. /* we know for sure that these rf chipsets are used on rt305x boards */
  66. if (rt2x00_rf(rt2x00dev, RF3020) ||
  67. rt2x00_rf(rt2x00dev, RF3021) ||
  68. rt2x00_rf(rt2x00dev, RF3022))
  69. return true;
  70. rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  71. return false;
  72. }
  73. static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  74. const unsigned int word, const u8 value)
  75. {
  76. u32 reg;
  77. mutex_lock(&rt2x00dev->csr_mutex);
  78. /*
  79. * Wait until the BBP becomes available, afterwards we
  80. * can safely write the new data into the register.
  81. */
  82. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  83. reg = 0;
  84. rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  85. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  86. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  87. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  88. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  89. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  90. }
  91. mutex_unlock(&rt2x00dev->csr_mutex);
  92. }
  93. static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
  94. const unsigned int word, u8 *value)
  95. {
  96. u32 reg;
  97. mutex_lock(&rt2x00dev->csr_mutex);
  98. /*
  99. * Wait until the BBP becomes available, afterwards we
  100. * can safely write the read request into the register.
  101. * After the data has been written, we wait until hardware
  102. * returns the correct value, if at any time the register
  103. * doesn't become available in time, reg will be 0xffffffff
  104. * which means we return 0xff to the caller.
  105. */
  106. if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  107. reg = 0;
  108. rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  109. rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  110. rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
  111. rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  112. rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
  113. WAIT_FOR_BBP(rt2x00dev, &reg);
  114. }
  115. *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
  116. mutex_unlock(&rt2x00dev->csr_mutex);
  117. }
  118. static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
  119. const unsigned int word, const u8 value)
  120. {
  121. u32 reg;
  122. mutex_lock(&rt2x00dev->csr_mutex);
  123. /*
  124. * Wait until the RFCSR becomes available, afterwards we
  125. * can safely write the new data into the register.
  126. */
  127. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  128. reg = 0;
  129. rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
  130. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  131. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
  132. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  133. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  134. }
  135. mutex_unlock(&rt2x00dev->csr_mutex);
  136. }
  137. static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
  138. const unsigned int word, u8 *value)
  139. {
  140. u32 reg;
  141. mutex_lock(&rt2x00dev->csr_mutex);
  142. /*
  143. * Wait until the RFCSR becomes available, afterwards we
  144. * can safely write the read request into the register.
  145. * After the data has been written, we wait until hardware
  146. * returns the correct value, if at any time the register
  147. * doesn't become available in time, reg will be 0xffffffff
  148. * which means we return 0xff to the caller.
  149. */
  150. if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
  151. reg = 0;
  152. rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
  153. rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
  154. rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
  155. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
  156. WAIT_FOR_RFCSR(rt2x00dev, &reg);
  157. }
  158. *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
  159. mutex_unlock(&rt2x00dev->csr_mutex);
  160. }
  161. static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
  162. const unsigned int word, const u32 value)
  163. {
  164. u32 reg;
  165. mutex_lock(&rt2x00dev->csr_mutex);
  166. /*
  167. * Wait until the RF becomes available, afterwards we
  168. * can safely write the new data into the register.
  169. */
  170. if (WAIT_FOR_RF(rt2x00dev, &reg)) {
  171. reg = 0;
  172. rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
  173. rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
  174. rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
  175. rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
  176. rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
  177. rt2x00_rf_write(rt2x00dev, word, value);
  178. }
  179. mutex_unlock(&rt2x00dev->csr_mutex);
  180. }
  181. static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
  182. [EEPROM_CHIP_ID] = 0x0000,
  183. [EEPROM_VERSION] = 0x0001,
  184. [EEPROM_MAC_ADDR_0] = 0x0002,
  185. [EEPROM_MAC_ADDR_1] = 0x0003,
  186. [EEPROM_MAC_ADDR_2] = 0x0004,
  187. [EEPROM_NIC_CONF0] = 0x001a,
  188. [EEPROM_NIC_CONF1] = 0x001b,
  189. [EEPROM_FREQ] = 0x001d,
  190. [EEPROM_LED_AG_CONF] = 0x001e,
  191. [EEPROM_LED_ACT_CONF] = 0x001f,
  192. [EEPROM_LED_POLARITY] = 0x0020,
  193. [EEPROM_NIC_CONF2] = 0x0021,
  194. [EEPROM_LNA] = 0x0022,
  195. [EEPROM_RSSI_BG] = 0x0023,
  196. [EEPROM_RSSI_BG2] = 0x0024,
  197. [EEPROM_TXMIXER_GAIN_BG] = 0x0024, /* overlaps with RSSI_BG2 */
  198. [EEPROM_RSSI_A] = 0x0025,
  199. [EEPROM_RSSI_A2] = 0x0026,
  200. [EEPROM_TXMIXER_GAIN_A] = 0x0026, /* overlaps with RSSI_A2 */
  201. [EEPROM_EIRP_MAX_TX_POWER] = 0x0027,
  202. [EEPROM_TXPOWER_DELTA] = 0x0028,
  203. [EEPROM_TXPOWER_BG1] = 0x0029,
  204. [EEPROM_TXPOWER_BG2] = 0x0030,
  205. [EEPROM_TSSI_BOUND_BG1] = 0x0037,
  206. [EEPROM_TSSI_BOUND_BG2] = 0x0038,
  207. [EEPROM_TSSI_BOUND_BG3] = 0x0039,
  208. [EEPROM_TSSI_BOUND_BG4] = 0x003a,
  209. [EEPROM_TSSI_BOUND_BG5] = 0x003b,
  210. [EEPROM_TXPOWER_A1] = 0x003c,
  211. [EEPROM_TXPOWER_A2] = 0x0053,
  212. [EEPROM_TSSI_BOUND_A1] = 0x006a,
  213. [EEPROM_TSSI_BOUND_A2] = 0x006b,
  214. [EEPROM_TSSI_BOUND_A3] = 0x006c,
  215. [EEPROM_TSSI_BOUND_A4] = 0x006d,
  216. [EEPROM_TSSI_BOUND_A5] = 0x006e,
  217. [EEPROM_TXPOWER_BYRATE] = 0x006f,
  218. [EEPROM_BBP_START] = 0x0078,
  219. };
  220. static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
  221. [EEPROM_CHIP_ID] = 0x0000,
  222. [EEPROM_VERSION] = 0x0001,
  223. [EEPROM_MAC_ADDR_0] = 0x0002,
  224. [EEPROM_MAC_ADDR_1] = 0x0003,
  225. [EEPROM_MAC_ADDR_2] = 0x0004,
  226. [EEPROM_NIC_CONF0] = 0x001a,
  227. [EEPROM_NIC_CONF1] = 0x001b,
  228. [EEPROM_NIC_CONF2] = 0x001c,
  229. [EEPROM_EIRP_MAX_TX_POWER] = 0x0020,
  230. [EEPROM_FREQ] = 0x0022,
  231. [EEPROM_LED_AG_CONF] = 0x0023,
  232. [EEPROM_LED_ACT_CONF] = 0x0024,
  233. [EEPROM_LED_POLARITY] = 0x0025,
  234. [EEPROM_LNA] = 0x0026,
  235. [EEPROM_EXT_LNA2] = 0x0027,
  236. [EEPROM_RSSI_BG] = 0x0028,
  237. [EEPROM_RSSI_BG2] = 0x0029,
  238. [EEPROM_RSSI_A] = 0x002a,
  239. [EEPROM_RSSI_A2] = 0x002b,
  240. [EEPROM_TXPOWER_BG1] = 0x0030,
  241. [EEPROM_TXPOWER_BG2] = 0x0037,
  242. [EEPROM_EXT_TXPOWER_BG3] = 0x003e,
  243. [EEPROM_TSSI_BOUND_BG1] = 0x0045,
  244. [EEPROM_TSSI_BOUND_BG2] = 0x0046,
  245. [EEPROM_TSSI_BOUND_BG3] = 0x0047,
  246. [EEPROM_TSSI_BOUND_BG4] = 0x0048,
  247. [EEPROM_TSSI_BOUND_BG5] = 0x0049,
  248. [EEPROM_TXPOWER_A1] = 0x004b,
  249. [EEPROM_TXPOWER_A2] = 0x0065,
  250. [EEPROM_EXT_TXPOWER_A3] = 0x007f,
  251. [EEPROM_TSSI_BOUND_A1] = 0x009a,
  252. [EEPROM_TSSI_BOUND_A2] = 0x009b,
  253. [EEPROM_TSSI_BOUND_A3] = 0x009c,
  254. [EEPROM_TSSI_BOUND_A4] = 0x009d,
  255. [EEPROM_TSSI_BOUND_A5] = 0x009e,
  256. [EEPROM_TXPOWER_BYRATE] = 0x00a0,
  257. };
  258. static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
  259. const enum rt2800_eeprom_word word)
  260. {
  261. const unsigned int *map;
  262. unsigned int index;
  263. if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
  264. "%s: invalid EEPROM word %d\n",
  265. wiphy_name(rt2x00dev->hw->wiphy), word))
  266. return 0;
  267. if (rt2x00_rt(rt2x00dev, RT3593))
  268. map = rt2800_eeprom_map_ext;
  269. else
  270. map = rt2800_eeprom_map;
  271. index = map[word];
  272. /* Index 0 is valid only for EEPROM_CHIP_ID.
  273. * Otherwise it means that the offset of the
  274. * given word is not initialized in the map,
  275. * or that the field is not usable on the
  276. * actual chipset.
  277. */
  278. WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
  279. "%s: invalid access of EEPROM word %d\n",
  280. wiphy_name(rt2x00dev->hw->wiphy), word);
  281. return index;
  282. }
  283. static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
  284. const enum rt2800_eeprom_word word)
  285. {
  286. unsigned int index;
  287. index = rt2800_eeprom_word_index(rt2x00dev, word);
  288. return rt2x00_eeprom_addr(rt2x00dev, index);
  289. }
  290. static void rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
  291. const enum rt2800_eeprom_word word, u16 *data)
  292. {
  293. unsigned int index;
  294. index = rt2800_eeprom_word_index(rt2x00dev, word);
  295. rt2x00_eeprom_read(rt2x00dev, index, data);
  296. }
  297. static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
  298. const enum rt2800_eeprom_word word, u16 data)
  299. {
  300. unsigned int index;
  301. index = rt2800_eeprom_word_index(rt2x00dev, word);
  302. rt2x00_eeprom_write(rt2x00dev, index, data);
  303. }
  304. static void rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
  305. const enum rt2800_eeprom_word array,
  306. unsigned int offset,
  307. u16 *data)
  308. {
  309. unsigned int index;
  310. index = rt2800_eeprom_word_index(rt2x00dev, array);
  311. rt2x00_eeprom_read(rt2x00dev, index + offset, data);
  312. }
  313. static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
  314. {
  315. u32 reg;
  316. int i, count;
  317. rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
  318. if (rt2x00_get_field32(reg, WLAN_EN))
  319. return 0;
  320. rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
  321. rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
  322. rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
  323. rt2x00_set_field32(&reg, WLAN_EN, 1);
  324. rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  325. udelay(REGISTER_BUSY_DELAY);
  326. count = 0;
  327. do {
  328. /*
  329. * Check PLL_LD & XTAL_RDY.
  330. */
  331. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  332. rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
  333. if (rt2x00_get_field32(reg, PLL_LD) &&
  334. rt2x00_get_field32(reg, XTAL_RDY))
  335. break;
  336. udelay(REGISTER_BUSY_DELAY);
  337. }
  338. if (i >= REGISTER_BUSY_COUNT) {
  339. if (count >= 10)
  340. return -EIO;
  341. rt2800_register_write(rt2x00dev, 0x58, 0x018);
  342. udelay(REGISTER_BUSY_DELAY);
  343. rt2800_register_write(rt2x00dev, 0x58, 0x418);
  344. udelay(REGISTER_BUSY_DELAY);
  345. rt2800_register_write(rt2x00dev, 0x58, 0x618);
  346. udelay(REGISTER_BUSY_DELAY);
  347. count++;
  348. } else {
  349. count = 0;
  350. }
  351. rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
  352. rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
  353. rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
  354. rt2x00_set_field32(&reg, WLAN_RESET, 1);
  355. rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  356. udelay(10);
  357. rt2x00_set_field32(&reg, WLAN_RESET, 0);
  358. rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  359. udelay(10);
  360. rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
  361. } while (count != 0);
  362. return 0;
  363. }
  364. void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
  365. const u8 command, const u8 token,
  366. const u8 arg0, const u8 arg1)
  367. {
  368. u32 reg;
  369. /*
  370. * SOC devices don't support MCU requests.
  371. */
  372. if (rt2x00_is_soc(rt2x00dev))
  373. return;
  374. mutex_lock(&rt2x00dev->csr_mutex);
  375. /*
  376. * Wait until the MCU becomes available, afterwards we
  377. * can safely write the new data into the register.
  378. */
  379. if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
  380. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
  381. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
  382. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
  383. rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
  384. rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
  385. reg = 0;
  386. rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
  387. rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
  388. }
  389. mutex_unlock(&rt2x00dev->csr_mutex);
  390. }
  391. EXPORT_SYMBOL_GPL(rt2800_mcu_request);
  392. int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
  393. {
  394. unsigned int i = 0;
  395. u32 reg;
  396. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  397. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  398. if (reg && reg != ~0)
  399. return 0;
  400. msleep(1);
  401. }
  402. rt2x00_err(rt2x00dev, "Unstable hardware\n");
  403. return -EBUSY;
  404. }
  405. EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
  406. int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
  407. {
  408. unsigned int i;
  409. u32 reg;
  410. /*
  411. * Some devices are really slow to respond here. Wait a whole second
  412. * before timing out.
  413. */
  414. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  415. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  416. if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
  417. !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
  418. return 0;
  419. msleep(10);
  420. }
  421. rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
  422. return -EACCES;
  423. }
  424. EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
  425. void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
  426. {
  427. u32 reg;
  428. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  429. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  430. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  431. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  432. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  433. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
  434. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  435. }
  436. EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
  437. void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
  438. unsigned short *txwi_size,
  439. unsigned short *rxwi_size)
  440. {
  441. switch (rt2x00dev->chip.rt) {
  442. case RT3593:
  443. *txwi_size = TXWI_DESC_SIZE_4WORDS;
  444. *rxwi_size = RXWI_DESC_SIZE_5WORDS;
  445. break;
  446. case RT5592:
  447. *txwi_size = TXWI_DESC_SIZE_5WORDS;
  448. *rxwi_size = RXWI_DESC_SIZE_6WORDS;
  449. break;
  450. default:
  451. *txwi_size = TXWI_DESC_SIZE_4WORDS;
  452. *rxwi_size = RXWI_DESC_SIZE_4WORDS;
  453. break;
  454. }
  455. }
  456. EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
  457. static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
  458. {
  459. u16 fw_crc;
  460. u16 crc;
  461. /*
  462. * The last 2 bytes in the firmware array are the crc checksum itself,
  463. * this means that we should never pass those 2 bytes to the crc
  464. * algorithm.
  465. */
  466. fw_crc = (data[len - 2] << 8 | data[len - 1]);
  467. /*
  468. * Use the crc ccitt algorithm.
  469. * This will return the same value as the legacy driver which
  470. * used bit ordering reversion on the both the firmware bytes
  471. * before input input as well as on the final output.
  472. * Obviously using crc ccitt directly is much more efficient.
  473. */
  474. crc = crc_ccitt(~0, data, len - 2);
  475. /*
  476. * There is a small difference between the crc-itu-t + bitrev and
  477. * the crc-ccitt crc calculation. In the latter method the 2 bytes
  478. * will be swapped, use swab16 to convert the crc to the correct
  479. * value.
  480. */
  481. crc = swab16(crc);
  482. return fw_crc == crc;
  483. }
  484. int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
  485. const u8 *data, const size_t len)
  486. {
  487. size_t offset = 0;
  488. size_t fw_len;
  489. bool multiple;
  490. /*
  491. * PCI(e) & SOC devices require firmware with a length
  492. * of 8kb. USB devices require firmware files with a length
  493. * of 4kb. Certain USB chipsets however require different firmware,
  494. * which Ralink only provides attached to the original firmware
  495. * file. Thus for USB devices, firmware files have a length
  496. * which is a multiple of 4kb. The firmware for rt3290 chip also
  497. * have a length which is a multiple of 4kb.
  498. */
  499. if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
  500. fw_len = 4096;
  501. else
  502. fw_len = 8192;
  503. multiple = true;
  504. /*
  505. * Validate the firmware length
  506. */
  507. if (len != fw_len && (!multiple || (len % fw_len) != 0))
  508. return FW_BAD_LENGTH;
  509. /*
  510. * Check if the chipset requires one of the upper parts
  511. * of the firmware.
  512. */
  513. if (rt2x00_is_usb(rt2x00dev) &&
  514. !rt2x00_rt(rt2x00dev, RT2860) &&
  515. !rt2x00_rt(rt2x00dev, RT2872) &&
  516. !rt2x00_rt(rt2x00dev, RT3070) &&
  517. ((len / fw_len) == 1))
  518. return FW_BAD_VERSION;
  519. /*
  520. * 8kb firmware files must be checked as if it were
  521. * 2 separate firmware files.
  522. */
  523. while (offset < len) {
  524. if (!rt2800_check_firmware_crc(data + offset, fw_len))
  525. return FW_BAD_CRC;
  526. offset += fw_len;
  527. }
  528. return FW_OK;
  529. }
  530. EXPORT_SYMBOL_GPL(rt2800_check_firmware);
  531. int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
  532. const u8 *data, const size_t len)
  533. {
  534. unsigned int i;
  535. u32 reg;
  536. int retval;
  537. if (rt2x00_rt(rt2x00dev, RT3290)) {
  538. retval = rt2800_enable_wlan_rt3290(rt2x00dev);
  539. if (retval)
  540. return -EBUSY;
  541. }
  542. /*
  543. * If driver doesn't wake up firmware here,
  544. * rt2800_load_firmware will hang forever when interface is up again.
  545. */
  546. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
  547. /*
  548. * Wait for stable hardware.
  549. */
  550. if (rt2800_wait_csr_ready(rt2x00dev))
  551. return -EBUSY;
  552. if (rt2x00_is_pci(rt2x00dev)) {
  553. if (rt2x00_rt(rt2x00dev, RT3290) ||
  554. rt2x00_rt(rt2x00dev, RT3572) ||
  555. rt2x00_rt(rt2x00dev, RT5390) ||
  556. rt2x00_rt(rt2x00dev, RT5392)) {
  557. rt2800_register_read(rt2x00dev, AUX_CTRL, &reg);
  558. rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
  559. rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
  560. rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
  561. }
  562. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
  563. }
  564. rt2800_disable_wpdma(rt2x00dev);
  565. /*
  566. * Write firmware to the device.
  567. */
  568. rt2800_drv_write_firmware(rt2x00dev, data, len);
  569. /*
  570. * Wait for device to stabilize.
  571. */
  572. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  573. rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
  574. if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
  575. break;
  576. msleep(1);
  577. }
  578. if (i == REGISTER_BUSY_COUNT) {
  579. rt2x00_err(rt2x00dev, "PBF system register not ready\n");
  580. return -EBUSY;
  581. }
  582. /*
  583. * Disable DMA, will be reenabled later when enabling
  584. * the radio.
  585. */
  586. rt2800_disable_wpdma(rt2x00dev);
  587. /*
  588. * Initialize firmware.
  589. */
  590. rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  591. rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  592. if (rt2x00_is_usb(rt2x00dev)) {
  593. rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
  594. rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
  595. }
  596. msleep(1);
  597. return 0;
  598. }
  599. EXPORT_SYMBOL_GPL(rt2800_load_firmware);
  600. void rt2800_write_tx_data(struct queue_entry *entry,
  601. struct txentry_desc *txdesc)
  602. {
  603. __le32 *txwi = rt2800_drv_get_txwi(entry);
  604. u32 word;
  605. int i;
  606. /*
  607. * Initialize TX Info descriptor
  608. */
  609. rt2x00_desc_read(txwi, 0, &word);
  610. rt2x00_set_field32(&word, TXWI_W0_FRAG,
  611. test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
  612. rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
  613. test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
  614. rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
  615. rt2x00_set_field32(&word, TXWI_W0_TS,
  616. test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
  617. rt2x00_set_field32(&word, TXWI_W0_AMPDU,
  618. test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
  619. rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
  620. txdesc->u.ht.mpdu_density);
  621. rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
  622. rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
  623. rt2x00_set_field32(&word, TXWI_W0_BW,
  624. test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
  625. rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
  626. test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
  627. rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
  628. rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
  629. rt2x00_desc_write(txwi, 0, word);
  630. rt2x00_desc_read(txwi, 1, &word);
  631. rt2x00_set_field32(&word, TXWI_W1_ACK,
  632. test_bit(ENTRY_TXD_ACK, &txdesc->flags));
  633. rt2x00_set_field32(&word, TXWI_W1_NSEQ,
  634. test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
  635. rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
  636. rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
  637. test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
  638. txdesc->key_idx : txdesc->u.ht.wcid);
  639. rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
  640. txdesc->length);
  641. rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
  642. rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
  643. rt2x00_desc_write(txwi, 1, word);
  644. /*
  645. * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
  646. * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
  647. * When TXD_W3_WIV is set to 1 it will use the IV data
  648. * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
  649. * crypto entry in the registers should be used to encrypt the frame.
  650. *
  651. * Nulify all remaining words as well, we don't know how to program them.
  652. */
  653. for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
  654. _rt2x00_desc_write(txwi, i, 0);
  655. }
  656. EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
  657. static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
  658. {
  659. s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
  660. s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
  661. s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
  662. u16 eeprom;
  663. u8 offset0;
  664. u8 offset1;
  665. u8 offset2;
  666. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
  667. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
  668. offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
  669. offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
  670. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
  671. offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
  672. } else {
  673. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
  674. offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
  675. offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
  676. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
  677. offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
  678. }
  679. /*
  680. * Convert the value from the descriptor into the RSSI value
  681. * If the value in the descriptor is 0, it is considered invalid
  682. * and the default (extremely low) rssi value is assumed
  683. */
  684. rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
  685. rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
  686. rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
  687. /*
  688. * mac80211 only accepts a single RSSI value. Calculating the
  689. * average doesn't deliver a fair answer either since -60:-60 would
  690. * be considered equally good as -50:-70 while the second is the one
  691. * which gives less energy...
  692. */
  693. rssi0 = max(rssi0, rssi1);
  694. return (int)max(rssi0, rssi2);
  695. }
  696. void rt2800_process_rxwi(struct queue_entry *entry,
  697. struct rxdone_entry_desc *rxdesc)
  698. {
  699. __le32 *rxwi = (__le32 *) entry->skb->data;
  700. u32 word;
  701. rt2x00_desc_read(rxwi, 0, &word);
  702. rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
  703. rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
  704. rt2x00_desc_read(rxwi, 1, &word);
  705. if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
  706. rxdesc->flags |= RX_FLAG_SHORT_GI;
  707. if (rt2x00_get_field32(word, RXWI_W1_BW))
  708. rxdesc->flags |= RX_FLAG_40MHZ;
  709. /*
  710. * Detect RX rate, always use MCS as signal type.
  711. */
  712. rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
  713. rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
  714. rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
  715. /*
  716. * Mask of 0x8 bit to remove the short preamble flag.
  717. */
  718. if (rxdesc->rate_mode == RATE_MODE_CCK)
  719. rxdesc->signal &= ~0x8;
  720. rt2x00_desc_read(rxwi, 2, &word);
  721. /*
  722. * Convert descriptor AGC value to RSSI value.
  723. */
  724. rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
  725. /*
  726. * Remove RXWI descriptor from start of the buffer.
  727. */
  728. skb_pull(entry->skb, entry->queue->winfo_size);
  729. }
  730. EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
  731. void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
  732. {
  733. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  734. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  735. struct txdone_entry_desc txdesc;
  736. u32 word;
  737. u16 mcs, real_mcs;
  738. int aggr, ampdu;
  739. /*
  740. * Obtain the status about this packet.
  741. */
  742. txdesc.flags = 0;
  743. rt2x00_desc_read(txwi, 0, &word);
  744. mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
  745. ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
  746. real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
  747. aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
  748. /*
  749. * If a frame was meant to be sent as a single non-aggregated MPDU
  750. * but ended up in an aggregate the used tx rate doesn't correlate
  751. * with the one specified in the TXWI as the whole aggregate is sent
  752. * with the same rate.
  753. *
  754. * For example: two frames are sent to rt2x00, the first one sets
  755. * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
  756. * and requests MCS15. If the hw aggregates both frames into one
  757. * AMDPU the tx status for both frames will contain MCS7 although
  758. * the frame was sent successfully.
  759. *
  760. * Hence, replace the requested rate with the real tx rate to not
  761. * confuse the rate control algortihm by providing clearly wrong
  762. * data.
  763. */
  764. if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
  765. skbdesc->tx_rate_idx = real_mcs;
  766. mcs = real_mcs;
  767. }
  768. if (aggr == 1 || ampdu == 1)
  769. __set_bit(TXDONE_AMPDU, &txdesc.flags);
  770. /*
  771. * Ralink has a retry mechanism using a global fallback
  772. * table. We setup this fallback table to try the immediate
  773. * lower rate for all rates. In the TX_STA_FIFO, the MCS field
  774. * always contains the MCS used for the last transmission, be
  775. * it successful or not.
  776. */
  777. if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
  778. /*
  779. * Transmission succeeded. The number of retries is
  780. * mcs - real_mcs
  781. */
  782. __set_bit(TXDONE_SUCCESS, &txdesc.flags);
  783. txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
  784. } else {
  785. /*
  786. * Transmission failed. The number of retries is
  787. * always 7 in this case (for a total number of 8
  788. * frames sent).
  789. */
  790. __set_bit(TXDONE_FAILURE, &txdesc.flags);
  791. txdesc.retry = rt2x00dev->long_retry;
  792. }
  793. /*
  794. * the frame was retried at least once
  795. * -> hw used fallback rates
  796. */
  797. if (txdesc.retry)
  798. __set_bit(TXDONE_FALLBACK, &txdesc.flags);
  799. rt2x00lib_txdone(entry, &txdesc);
  800. }
  801. EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
  802. static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
  803. unsigned int index)
  804. {
  805. return HW_BEACON_BASE(index);
  806. }
  807. static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
  808. unsigned int index)
  809. {
  810. return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
  811. }
  812. static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
  813. {
  814. struct data_queue *queue = rt2x00dev->bcn;
  815. struct queue_entry *entry;
  816. int i, bcn_num = 0;
  817. u64 off, reg = 0;
  818. u32 bssid_dw1;
  819. /*
  820. * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
  821. */
  822. for (i = 0; i < queue->limit; i++) {
  823. entry = &queue->entries[i];
  824. if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
  825. continue;
  826. off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
  827. reg |= off << (8 * bcn_num);
  828. bcn_num++;
  829. }
  830. WARN_ON_ONCE(bcn_num != rt2x00dev->intf_beaconing);
  831. rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
  832. rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
  833. /*
  834. * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
  835. */
  836. rt2800_register_read(rt2x00dev, MAC_BSSID_DW1, &bssid_dw1);
  837. rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
  838. bcn_num > 0 ? bcn_num - 1 : 0);
  839. rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
  840. }
  841. void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
  842. {
  843. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  844. struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
  845. unsigned int beacon_base;
  846. unsigned int padding_len;
  847. u32 orig_reg, reg;
  848. const int txwi_desc_size = entry->queue->winfo_size;
  849. /*
  850. * Disable beaconing while we are reloading the beacon data,
  851. * otherwise we might be sending out invalid data.
  852. */
  853. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  854. orig_reg = reg;
  855. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  856. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  857. /*
  858. * Add space for the TXWI in front of the skb.
  859. */
  860. memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
  861. /*
  862. * Register descriptor details in skb frame descriptor.
  863. */
  864. skbdesc->flags |= SKBDESC_DESC_IN_SKB;
  865. skbdesc->desc = entry->skb->data;
  866. skbdesc->desc_len = txwi_desc_size;
  867. /*
  868. * Add the TXWI for the beacon to the skb.
  869. */
  870. rt2800_write_tx_data(entry, txdesc);
  871. /*
  872. * Dump beacon to userspace through debugfs.
  873. */
  874. rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
  875. /*
  876. * Write entire beacon with TXWI and padding to register.
  877. */
  878. padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
  879. if (padding_len && skb_pad(entry->skb, padding_len)) {
  880. rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
  881. /* skb freed by skb_pad() on failure */
  882. entry->skb = NULL;
  883. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
  884. return;
  885. }
  886. beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
  887. rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
  888. entry->skb->len + padding_len);
  889. __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
  890. /*
  891. * Change global beacons settings.
  892. */
  893. rt2800_update_beacons_setup(rt2x00dev);
  894. /*
  895. * Restore beaconing state.
  896. */
  897. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
  898. /*
  899. * Clean up beacon skb.
  900. */
  901. dev_kfree_skb_any(entry->skb);
  902. entry->skb = NULL;
  903. }
  904. EXPORT_SYMBOL_GPL(rt2800_write_beacon);
  905. static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
  906. unsigned int index)
  907. {
  908. int i;
  909. const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
  910. unsigned int beacon_base;
  911. beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
  912. /*
  913. * For the Beacon base registers we only need to clear
  914. * the whole TXWI which (when set to 0) will invalidate
  915. * the entire beacon.
  916. */
  917. for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
  918. rt2800_register_write(rt2x00dev, beacon_base + i, 0);
  919. }
  920. void rt2800_clear_beacon(struct queue_entry *entry)
  921. {
  922. struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
  923. u32 orig_reg, reg;
  924. /*
  925. * Disable beaconing while we are reloading the beacon data,
  926. * otherwise we might be sending out invalid data.
  927. */
  928. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &orig_reg);
  929. reg = orig_reg;
  930. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  931. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  932. /*
  933. * Clear beacon.
  934. */
  935. rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
  936. __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
  937. /*
  938. * Change global beacons settings.
  939. */
  940. rt2800_update_beacons_setup(rt2x00dev);
  941. /*
  942. * Restore beaconing state.
  943. */
  944. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
  945. }
  946. EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
  947. #ifdef CONFIG_RT2X00_LIB_DEBUGFS
  948. const struct rt2x00debug rt2800_rt2x00debug = {
  949. .owner = THIS_MODULE,
  950. .csr = {
  951. .read = rt2800_register_read,
  952. .write = rt2800_register_write,
  953. .flags = RT2X00DEBUGFS_OFFSET,
  954. .word_base = CSR_REG_BASE,
  955. .word_size = sizeof(u32),
  956. .word_count = CSR_REG_SIZE / sizeof(u32),
  957. },
  958. .eeprom = {
  959. /* NOTE: The local EEPROM access functions can't
  960. * be used here, use the generic versions instead.
  961. */
  962. .read = rt2x00_eeprom_read,
  963. .write = rt2x00_eeprom_write,
  964. .word_base = EEPROM_BASE,
  965. .word_size = sizeof(u16),
  966. .word_count = EEPROM_SIZE / sizeof(u16),
  967. },
  968. .bbp = {
  969. .read = rt2800_bbp_read,
  970. .write = rt2800_bbp_write,
  971. .word_base = BBP_BASE,
  972. .word_size = sizeof(u8),
  973. .word_count = BBP_SIZE / sizeof(u8),
  974. },
  975. .rf = {
  976. .read = rt2x00_rf_read,
  977. .write = rt2800_rf_write,
  978. .word_base = RF_BASE,
  979. .word_size = sizeof(u32),
  980. .word_count = RF_SIZE / sizeof(u32),
  981. },
  982. .rfcsr = {
  983. .read = rt2800_rfcsr_read,
  984. .write = rt2800_rfcsr_write,
  985. .word_base = RFCSR_BASE,
  986. .word_size = sizeof(u8),
  987. .word_count = RFCSR_SIZE / sizeof(u8),
  988. },
  989. };
  990. EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
  991. #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
  992. int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
  993. {
  994. u32 reg;
  995. if (rt2x00_rt(rt2x00dev, RT3290)) {
  996. rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
  997. return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
  998. } else {
  999. rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
  1000. return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
  1001. }
  1002. }
  1003. EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
  1004. #ifdef CONFIG_RT2X00_LIB_LEDS
  1005. static void rt2800_brightness_set(struct led_classdev *led_cdev,
  1006. enum led_brightness brightness)
  1007. {
  1008. struct rt2x00_led *led =
  1009. container_of(led_cdev, struct rt2x00_led, led_dev);
  1010. unsigned int enabled = brightness != LED_OFF;
  1011. unsigned int bg_mode =
  1012. (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
  1013. unsigned int polarity =
  1014. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  1015. EEPROM_FREQ_LED_POLARITY);
  1016. unsigned int ledmode =
  1017. rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
  1018. EEPROM_FREQ_LED_MODE);
  1019. u32 reg;
  1020. /* Check for SoC (SOC devices don't support MCU requests) */
  1021. if (rt2x00_is_soc(led->rt2x00dev)) {
  1022. rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
  1023. /* Set LED Polarity */
  1024. rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
  1025. /* Set LED Mode */
  1026. if (led->type == LED_TYPE_RADIO) {
  1027. rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
  1028. enabled ? 3 : 0);
  1029. } else if (led->type == LED_TYPE_ASSOC) {
  1030. rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
  1031. enabled ? 3 : 0);
  1032. } else if (led->type == LED_TYPE_QUALITY) {
  1033. rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
  1034. enabled ? 3 : 0);
  1035. }
  1036. rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
  1037. } else {
  1038. if (led->type == LED_TYPE_RADIO) {
  1039. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  1040. enabled ? 0x20 : 0);
  1041. } else if (led->type == LED_TYPE_ASSOC) {
  1042. rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
  1043. enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
  1044. } else if (led->type == LED_TYPE_QUALITY) {
  1045. /*
  1046. * The brightness is divided into 6 levels (0 - 5),
  1047. * The specs tell us the following levels:
  1048. * 0, 1 ,3, 7, 15, 31
  1049. * to determine the level in a simple way we can simply
  1050. * work with bitshifting:
  1051. * (1 << level) - 1
  1052. */
  1053. rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
  1054. (1 << brightness / (LED_FULL / 6)) - 1,
  1055. polarity);
  1056. }
  1057. }
  1058. }
  1059. static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
  1060. struct rt2x00_led *led, enum led_type type)
  1061. {
  1062. led->rt2x00dev = rt2x00dev;
  1063. led->type = type;
  1064. led->led_dev.brightness_set = rt2800_brightness_set;
  1065. led->flags = LED_INITIALIZED;
  1066. }
  1067. #endif /* CONFIG_RT2X00_LIB_LEDS */
  1068. /*
  1069. * Configuration handlers.
  1070. */
  1071. static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
  1072. const u8 *address,
  1073. int wcid)
  1074. {
  1075. struct mac_wcid_entry wcid_entry;
  1076. u32 offset;
  1077. offset = MAC_WCID_ENTRY(wcid);
  1078. memset(&wcid_entry, 0xff, sizeof(wcid_entry));
  1079. if (address)
  1080. memcpy(wcid_entry.mac, address, ETH_ALEN);
  1081. rt2800_register_multiwrite(rt2x00dev, offset,
  1082. &wcid_entry, sizeof(wcid_entry));
  1083. }
  1084. static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
  1085. {
  1086. u32 offset;
  1087. offset = MAC_WCID_ATTR_ENTRY(wcid);
  1088. rt2800_register_write(rt2x00dev, offset, 0);
  1089. }
  1090. static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
  1091. int wcid, u32 bssidx)
  1092. {
  1093. u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
  1094. u32 reg;
  1095. /*
  1096. * The BSS Idx numbers is split in a main value of 3 bits,
  1097. * and a extended field for adding one additional bit to the value.
  1098. */
  1099. rt2800_register_read(rt2x00dev, offset, &reg);
  1100. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
  1101. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
  1102. (bssidx & 0x8) >> 3);
  1103. rt2800_register_write(rt2x00dev, offset, reg);
  1104. }
  1105. static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
  1106. struct rt2x00lib_crypto *crypto,
  1107. struct ieee80211_key_conf *key)
  1108. {
  1109. struct mac_iveiv_entry iveiv_entry;
  1110. u32 offset;
  1111. u32 reg;
  1112. offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
  1113. if (crypto->cmd == SET_KEY) {
  1114. rt2800_register_read(rt2x00dev, offset, &reg);
  1115. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
  1116. !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
  1117. /*
  1118. * Both the cipher as the BSS Idx numbers are split in a main
  1119. * value of 3 bits, and a extended field for adding one additional
  1120. * bit to the value.
  1121. */
  1122. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
  1123. (crypto->cipher & 0x7));
  1124. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
  1125. (crypto->cipher & 0x8) >> 3);
  1126. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
  1127. rt2800_register_write(rt2x00dev, offset, reg);
  1128. } else {
  1129. /* Delete the cipher without touching the bssidx */
  1130. rt2800_register_read(rt2x00dev, offset, &reg);
  1131. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
  1132. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
  1133. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
  1134. rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
  1135. rt2800_register_write(rt2x00dev, offset, reg);
  1136. }
  1137. offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
  1138. memset(&iveiv_entry, 0, sizeof(iveiv_entry));
  1139. if ((crypto->cipher == CIPHER_TKIP) ||
  1140. (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
  1141. (crypto->cipher == CIPHER_AES))
  1142. iveiv_entry.iv[3] |= 0x20;
  1143. iveiv_entry.iv[3] |= key->keyidx << 6;
  1144. rt2800_register_multiwrite(rt2x00dev, offset,
  1145. &iveiv_entry, sizeof(iveiv_entry));
  1146. }
  1147. int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
  1148. struct rt2x00lib_crypto *crypto,
  1149. struct ieee80211_key_conf *key)
  1150. {
  1151. struct hw_key_entry key_entry;
  1152. struct rt2x00_field32 field;
  1153. u32 offset;
  1154. u32 reg;
  1155. if (crypto->cmd == SET_KEY) {
  1156. key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
  1157. memcpy(key_entry.key, crypto->key,
  1158. sizeof(key_entry.key));
  1159. memcpy(key_entry.tx_mic, crypto->tx_mic,
  1160. sizeof(key_entry.tx_mic));
  1161. memcpy(key_entry.rx_mic, crypto->rx_mic,
  1162. sizeof(key_entry.rx_mic));
  1163. offset = SHARED_KEY_ENTRY(key->hw_key_idx);
  1164. rt2800_register_multiwrite(rt2x00dev, offset,
  1165. &key_entry, sizeof(key_entry));
  1166. }
  1167. /*
  1168. * The cipher types are stored over multiple registers
  1169. * starting with SHARED_KEY_MODE_BASE each word will have
  1170. * 32 bits and contains the cipher types for 2 bssidx each.
  1171. * Using the correct defines correctly will cause overhead,
  1172. * so just calculate the correct offset.
  1173. */
  1174. field.bit_offset = 4 * (key->hw_key_idx % 8);
  1175. field.bit_mask = 0x7 << field.bit_offset;
  1176. offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
  1177. rt2800_register_read(rt2x00dev, offset, &reg);
  1178. rt2x00_set_field32(&reg, field,
  1179. (crypto->cmd == SET_KEY) * crypto->cipher);
  1180. rt2800_register_write(rt2x00dev, offset, reg);
  1181. /*
  1182. * Update WCID information
  1183. */
  1184. rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
  1185. rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
  1186. crypto->bssidx);
  1187. rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
  1188. return 0;
  1189. }
  1190. EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
  1191. int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
  1192. struct rt2x00lib_crypto *crypto,
  1193. struct ieee80211_key_conf *key)
  1194. {
  1195. struct hw_key_entry key_entry;
  1196. u32 offset;
  1197. if (crypto->cmd == SET_KEY) {
  1198. /*
  1199. * Allow key configuration only for STAs that are
  1200. * known by the hw.
  1201. */
  1202. if (crypto->wcid > WCID_END)
  1203. return -ENOSPC;
  1204. key->hw_key_idx = crypto->wcid;
  1205. memcpy(key_entry.key, crypto->key,
  1206. sizeof(key_entry.key));
  1207. memcpy(key_entry.tx_mic, crypto->tx_mic,
  1208. sizeof(key_entry.tx_mic));
  1209. memcpy(key_entry.rx_mic, crypto->rx_mic,
  1210. sizeof(key_entry.rx_mic));
  1211. offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
  1212. rt2800_register_multiwrite(rt2x00dev, offset,
  1213. &key_entry, sizeof(key_entry));
  1214. }
  1215. /*
  1216. * Update WCID information
  1217. */
  1218. rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
  1219. return 0;
  1220. }
  1221. EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
  1222. int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
  1223. struct ieee80211_sta *sta)
  1224. {
  1225. int wcid;
  1226. struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
  1227. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  1228. /*
  1229. * Search for the first free WCID entry and return the corresponding
  1230. * index.
  1231. */
  1232. wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
  1233. /*
  1234. * Store selected wcid even if it is invalid so that we can
  1235. * later decide if the STA is uploaded into the hw.
  1236. */
  1237. sta_priv->wcid = wcid;
  1238. /*
  1239. * No space left in the device, however, we can still communicate
  1240. * with the STA -> No error.
  1241. */
  1242. if (wcid > WCID_END)
  1243. return 0;
  1244. __set_bit(wcid - WCID_START, drv_data->sta_ids);
  1245. /*
  1246. * Clean up WCID attributes and write STA address to the device.
  1247. */
  1248. rt2800_delete_wcid_attr(rt2x00dev, wcid);
  1249. rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
  1250. rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
  1251. rt2x00lib_get_bssidx(rt2x00dev, vif));
  1252. return 0;
  1253. }
  1254. EXPORT_SYMBOL_GPL(rt2800_sta_add);
  1255. int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
  1256. {
  1257. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  1258. if (wcid > WCID_END)
  1259. return 0;
  1260. /*
  1261. * Remove WCID entry, no need to clean the attributes as they will
  1262. * get renewed when the WCID is reused.
  1263. */
  1264. rt2800_config_wcid(rt2x00dev, NULL, wcid);
  1265. __clear_bit(wcid - WCID_START, drv_data->sta_ids);
  1266. return 0;
  1267. }
  1268. EXPORT_SYMBOL_GPL(rt2800_sta_remove);
  1269. void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
  1270. const unsigned int filter_flags)
  1271. {
  1272. u32 reg;
  1273. /*
  1274. * Start configuration steps.
  1275. * Note that the version error will always be dropped
  1276. * and broadcast frames will always be accepted since
  1277. * there is no filter for it at this time.
  1278. */
  1279. rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
  1280. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
  1281. !(filter_flags & FIF_FCSFAIL));
  1282. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
  1283. !(filter_flags & FIF_PLCPFAIL));
  1284. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME, 1);
  1285. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
  1286. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
  1287. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
  1288. !(filter_flags & FIF_ALLMULTI));
  1289. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
  1290. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
  1291. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
  1292. !(filter_flags & FIF_CONTROL));
  1293. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
  1294. !(filter_flags & FIF_CONTROL));
  1295. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
  1296. !(filter_flags & FIF_CONTROL));
  1297. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
  1298. !(filter_flags & FIF_CONTROL));
  1299. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
  1300. !(filter_flags & FIF_CONTROL));
  1301. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
  1302. !(filter_flags & FIF_PSPOLL));
  1303. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
  1304. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
  1305. !(filter_flags & FIF_CONTROL));
  1306. rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
  1307. !(filter_flags & FIF_CONTROL));
  1308. rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
  1309. }
  1310. EXPORT_SYMBOL_GPL(rt2800_config_filter);
  1311. void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
  1312. struct rt2x00intf_conf *conf, const unsigned int flags)
  1313. {
  1314. u32 reg;
  1315. bool update_bssid = false;
  1316. if (flags & CONFIG_UPDATE_TYPE) {
  1317. /*
  1318. * Enable synchronisation.
  1319. */
  1320. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  1321. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
  1322. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  1323. if (conf->sync == TSF_SYNC_AP_NONE) {
  1324. /*
  1325. * Tune beacon queue transmit parameters for AP mode
  1326. */
  1327. rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
  1328. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
  1329. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
  1330. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
  1331. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
  1332. rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
  1333. } else {
  1334. rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, &reg);
  1335. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
  1336. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
  1337. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
  1338. rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
  1339. rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
  1340. }
  1341. }
  1342. if (flags & CONFIG_UPDATE_MAC) {
  1343. if (flags & CONFIG_UPDATE_TYPE &&
  1344. conf->sync == TSF_SYNC_AP_NONE) {
  1345. /*
  1346. * The BSSID register has to be set to our own mac
  1347. * address in AP mode.
  1348. */
  1349. memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
  1350. update_bssid = true;
  1351. }
  1352. if (!is_zero_ether_addr((const u8 *)conf->mac)) {
  1353. reg = le32_to_cpu(conf->mac[1]);
  1354. rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
  1355. conf->mac[1] = cpu_to_le32(reg);
  1356. }
  1357. rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
  1358. conf->mac, sizeof(conf->mac));
  1359. }
  1360. if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
  1361. if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
  1362. reg = le32_to_cpu(conf->bssid[1]);
  1363. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
  1364. rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
  1365. conf->bssid[1] = cpu_to_le32(reg);
  1366. }
  1367. rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
  1368. conf->bssid, sizeof(conf->bssid));
  1369. }
  1370. }
  1371. EXPORT_SYMBOL_GPL(rt2800_config_intf);
  1372. static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
  1373. struct rt2x00lib_erp *erp)
  1374. {
  1375. bool any_sta_nongf = !!(erp->ht_opmode &
  1376. IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
  1377. u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
  1378. u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
  1379. u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
  1380. u32 reg;
  1381. /* default protection rate for HT20: OFDM 24M */
  1382. mm20_rate = gf20_rate = 0x4004;
  1383. /* default protection rate for HT40: duplicate OFDM 24M */
  1384. mm40_rate = gf40_rate = 0x4084;
  1385. switch (protection) {
  1386. case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
  1387. /*
  1388. * All STAs in this BSS are HT20/40 but there might be
  1389. * STAs not supporting greenfield mode.
  1390. * => Disable protection for HT transmissions.
  1391. */
  1392. mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
  1393. break;
  1394. case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
  1395. /*
  1396. * All STAs in this BSS are HT20 or HT20/40 but there
  1397. * might be STAs not supporting greenfield mode.
  1398. * => Protect all HT40 transmissions.
  1399. */
  1400. mm20_mode = gf20_mode = 0;
  1401. mm40_mode = gf40_mode = 2;
  1402. break;
  1403. case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
  1404. /*
  1405. * Nonmember protection:
  1406. * According to 802.11n we _should_ protect all
  1407. * HT transmissions (but we don't have to).
  1408. *
  1409. * But if cts_protection is enabled we _shall_ protect
  1410. * all HT transmissions using a CCK rate.
  1411. *
  1412. * And if any station is non GF we _shall_ protect
  1413. * GF transmissions.
  1414. *
  1415. * We decide to protect everything
  1416. * -> fall through to mixed mode.
  1417. */
  1418. case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
  1419. /*
  1420. * Legacy STAs are present
  1421. * => Protect all HT transmissions.
  1422. */
  1423. mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
  1424. /*
  1425. * If erp protection is needed we have to protect HT
  1426. * transmissions with CCK 11M long preamble.
  1427. */
  1428. if (erp->cts_protection) {
  1429. /* don't duplicate RTS/CTS in CCK mode */
  1430. mm20_rate = mm40_rate = 0x0003;
  1431. gf20_rate = gf40_rate = 0x0003;
  1432. }
  1433. break;
  1434. }
  1435. /* check for STAs not supporting greenfield mode */
  1436. if (any_sta_nongf)
  1437. gf20_mode = gf40_mode = 2;
  1438. /* Update HT protection config */
  1439. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  1440. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
  1441. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
  1442. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  1443. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  1444. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
  1445. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
  1446. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  1447. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  1448. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
  1449. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
  1450. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  1451. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  1452. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
  1453. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
  1454. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  1455. }
  1456. void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
  1457. u32 changed)
  1458. {
  1459. u32 reg;
  1460. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1461. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  1462. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
  1463. !!erp->short_preamble);
  1464. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
  1465. !!erp->short_preamble);
  1466. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  1467. }
  1468. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1469. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  1470. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
  1471. erp->cts_protection ? 2 : 0);
  1472. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  1473. }
  1474. if (changed & BSS_CHANGED_BASIC_RATES) {
  1475. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
  1476. erp->basic_rates);
  1477. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  1478. }
  1479. if (changed & BSS_CHANGED_ERP_SLOT) {
  1480. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  1481. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
  1482. erp->slot_time);
  1483. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  1484. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  1485. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
  1486. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  1487. }
  1488. if (changed & BSS_CHANGED_BEACON_INT) {
  1489. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  1490. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
  1491. erp->beacon_int * 16);
  1492. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  1493. }
  1494. if (changed & BSS_CHANGED_HT)
  1495. rt2800_config_ht_opmode(rt2x00dev, erp);
  1496. }
  1497. EXPORT_SYMBOL_GPL(rt2800_config_erp);
  1498. static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
  1499. {
  1500. u32 reg;
  1501. u16 eeprom;
  1502. u8 led_ctrl, led_g_mode, led_r_mode;
  1503. rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
  1504. if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
  1505. rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
  1506. rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
  1507. } else {
  1508. rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
  1509. rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
  1510. }
  1511. rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
  1512. rt2800_register_read(rt2x00dev, LED_CFG, &reg);
  1513. led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
  1514. led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
  1515. if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
  1516. led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
  1517. rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  1518. led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
  1519. if (led_ctrl == 0 || led_ctrl > 0x40) {
  1520. rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
  1521. rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
  1522. rt2800_register_write(rt2x00dev, LED_CFG, reg);
  1523. } else {
  1524. rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
  1525. (led_g_mode << 2) | led_r_mode, 1);
  1526. }
  1527. }
  1528. }
  1529. static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
  1530. enum antenna ant)
  1531. {
  1532. u32 reg;
  1533. u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
  1534. u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
  1535. if (rt2x00_is_pci(rt2x00dev)) {
  1536. rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
  1537. rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
  1538. rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
  1539. } else if (rt2x00_is_usb(rt2x00dev))
  1540. rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
  1541. eesk_pin, 0);
  1542. rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
  1543. rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
  1544. rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
  1545. rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
  1546. }
  1547. void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
  1548. {
  1549. u8 r1;
  1550. u8 r3;
  1551. u16 eeprom;
  1552. rt2800_bbp_read(rt2x00dev, 1, &r1);
  1553. rt2800_bbp_read(rt2x00dev, 3, &r3);
  1554. if (rt2x00_rt(rt2x00dev, RT3572) &&
  1555. rt2x00_has_cap_bt_coexist(rt2x00dev))
  1556. rt2800_config_3572bt_ant(rt2x00dev);
  1557. /*
  1558. * Configure the TX antenna.
  1559. */
  1560. switch (ant->tx_chain_num) {
  1561. case 1:
  1562. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
  1563. break;
  1564. case 2:
  1565. if (rt2x00_rt(rt2x00dev, RT3572) &&
  1566. rt2x00_has_cap_bt_coexist(rt2x00dev))
  1567. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
  1568. else
  1569. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
  1570. break;
  1571. case 3:
  1572. rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
  1573. break;
  1574. }
  1575. /*
  1576. * Configure the RX antenna.
  1577. */
  1578. switch (ant->rx_chain_num) {
  1579. case 1:
  1580. if (rt2x00_rt(rt2x00dev, RT3070) ||
  1581. rt2x00_rt(rt2x00dev, RT3090) ||
  1582. rt2x00_rt(rt2x00dev, RT3352) ||
  1583. rt2x00_rt(rt2x00dev, RT3390)) {
  1584. rt2800_eeprom_read(rt2x00dev,
  1585. EEPROM_NIC_CONF1, &eeprom);
  1586. if (rt2x00_get_field16(eeprom,
  1587. EEPROM_NIC_CONF1_ANT_DIVERSITY))
  1588. rt2800_set_ant_diversity(rt2x00dev,
  1589. rt2x00dev->default_ant.rx);
  1590. }
  1591. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
  1592. break;
  1593. case 2:
  1594. if (rt2x00_rt(rt2x00dev, RT3572) &&
  1595. rt2x00_has_cap_bt_coexist(rt2x00dev)) {
  1596. rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
  1597. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
  1598. rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
  1599. rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
  1600. } else {
  1601. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
  1602. }
  1603. break;
  1604. case 3:
  1605. rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
  1606. break;
  1607. }
  1608. rt2800_bbp_write(rt2x00dev, 3, r3);
  1609. rt2800_bbp_write(rt2x00dev, 1, r1);
  1610. if (rt2x00_rt(rt2x00dev, RT3593)) {
  1611. if (ant->rx_chain_num == 1)
  1612. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  1613. else
  1614. rt2800_bbp_write(rt2x00dev, 86, 0x46);
  1615. }
  1616. }
  1617. EXPORT_SYMBOL_GPL(rt2800_config_ant);
  1618. static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
  1619. struct rt2x00lib_conf *libconf)
  1620. {
  1621. u16 eeprom;
  1622. short lna_gain;
  1623. if (libconf->rf.channel <= 14) {
  1624. rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  1625. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
  1626. } else if (libconf->rf.channel <= 64) {
  1627. rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
  1628. lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
  1629. } else if (libconf->rf.channel <= 128) {
  1630. if (rt2x00_rt(rt2x00dev, RT3593)) {
  1631. rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
  1632. lna_gain = rt2x00_get_field16(eeprom,
  1633. EEPROM_EXT_LNA2_A1);
  1634. } else {
  1635. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
  1636. lna_gain = rt2x00_get_field16(eeprom,
  1637. EEPROM_RSSI_BG2_LNA_A1);
  1638. }
  1639. } else {
  1640. if (rt2x00_rt(rt2x00dev, RT3593)) {
  1641. rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &eeprom);
  1642. lna_gain = rt2x00_get_field16(eeprom,
  1643. EEPROM_EXT_LNA2_A2);
  1644. } else {
  1645. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
  1646. lna_gain = rt2x00_get_field16(eeprom,
  1647. EEPROM_RSSI_A2_LNA_A2);
  1648. }
  1649. }
  1650. rt2x00dev->lna_gain = lna_gain;
  1651. }
  1652. #define FREQ_OFFSET_BOUND 0x5f
  1653. static void rt2800_adjust_freq_offset(struct rt2x00_dev *rt2x00dev)
  1654. {
  1655. u8 freq_offset, prev_freq_offset;
  1656. u8 rfcsr, prev_rfcsr;
  1657. freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
  1658. freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
  1659. rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
  1660. prev_rfcsr = rfcsr;
  1661. rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
  1662. if (rfcsr == prev_rfcsr)
  1663. return;
  1664. if (rt2x00_is_usb(rt2x00dev)) {
  1665. rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
  1666. freq_offset, prev_rfcsr);
  1667. return;
  1668. }
  1669. prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
  1670. while (prev_freq_offset != freq_offset) {
  1671. if (prev_freq_offset < freq_offset)
  1672. prev_freq_offset++;
  1673. else
  1674. prev_freq_offset--;
  1675. rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
  1676. rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
  1677. usleep_range(1000, 1500);
  1678. }
  1679. }
  1680. static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
  1681. struct ieee80211_conf *conf,
  1682. struct rf_channel *rf,
  1683. struct channel_info *info)
  1684. {
  1685. rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
  1686. if (rt2x00dev->default_ant.tx_chain_num == 1)
  1687. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
  1688. if (rt2x00dev->default_ant.rx_chain_num == 1) {
  1689. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
  1690. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  1691. } else if (rt2x00dev->default_ant.rx_chain_num == 2)
  1692. rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
  1693. if (rf->channel > 14) {
  1694. /*
  1695. * When TX power is below 0, we should increase it by 7 to
  1696. * make it a positive value (Minimum value is -7).
  1697. * However this means that values between 0 and 7 have
  1698. * double meaning, and we should set a 7DBm boost flag.
  1699. */
  1700. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
  1701. (info->default_power1 >= 0));
  1702. if (info->default_power1 < 0)
  1703. info->default_power1 += 7;
  1704. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
  1705. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
  1706. (info->default_power2 >= 0));
  1707. if (info->default_power2 < 0)
  1708. info->default_power2 += 7;
  1709. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
  1710. } else {
  1711. rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
  1712. rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
  1713. }
  1714. rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
  1715. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  1716. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  1717. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  1718. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  1719. udelay(200);
  1720. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  1721. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  1722. rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
  1723. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  1724. udelay(200);
  1725. rt2800_rf_write(rt2x00dev, 1, rf->rf1);
  1726. rt2800_rf_write(rt2x00dev, 2, rf->rf2);
  1727. rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
  1728. rt2800_rf_write(rt2x00dev, 4, rf->rf4);
  1729. }
  1730. static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
  1731. struct ieee80211_conf *conf,
  1732. struct rf_channel *rf,
  1733. struct channel_info *info)
  1734. {
  1735. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  1736. u8 rfcsr, calib_tx, calib_rx;
  1737. rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
  1738. rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  1739. rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
  1740. rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  1741. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  1742. rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
  1743. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  1744. rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
  1745. rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
  1746. rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
  1747. rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
  1748. rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
  1749. rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
  1750. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  1751. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  1752. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
  1753. rt2x00dev->default_ant.rx_chain_num <= 1);
  1754. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
  1755. rt2x00dev->default_ant.rx_chain_num <= 2);
  1756. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  1757. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
  1758. rt2x00dev->default_ant.tx_chain_num <= 1);
  1759. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
  1760. rt2x00dev->default_ant.tx_chain_num <= 2);
  1761. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  1762. rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
  1763. rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
  1764. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  1765. if (rt2x00_rt(rt2x00dev, RT3390)) {
  1766. calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
  1767. calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
  1768. } else {
  1769. if (conf_is_ht40(conf)) {
  1770. calib_tx = drv_data->calibration_bw40;
  1771. calib_rx = drv_data->calibration_bw40;
  1772. } else {
  1773. calib_tx = drv_data->calibration_bw20;
  1774. calib_rx = drv_data->calibration_bw20;
  1775. }
  1776. }
  1777. rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
  1778. rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
  1779. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
  1780. rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
  1781. rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
  1782. rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
  1783. rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
  1784. rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
  1785. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  1786. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  1787. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
  1788. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1789. msleep(1);
  1790. rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
  1791. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  1792. }
  1793. static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
  1794. struct ieee80211_conf *conf,
  1795. struct rf_channel *rf,
  1796. struct channel_info *info)
  1797. {
  1798. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  1799. u8 rfcsr;
  1800. u32 reg;
  1801. if (rf->channel <= 14) {
  1802. rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
  1803. rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
  1804. } else {
  1805. rt2800_bbp_write(rt2x00dev, 25, 0x09);
  1806. rt2800_bbp_write(rt2x00dev, 26, 0xff);
  1807. }
  1808. rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
  1809. rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
  1810. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  1811. rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
  1812. if (rf->channel <= 14)
  1813. rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
  1814. else
  1815. rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
  1816. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  1817. rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
  1818. if (rf->channel <= 14)
  1819. rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
  1820. else
  1821. rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
  1822. rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
  1823. rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
  1824. if (rf->channel <= 14) {
  1825. rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
  1826. rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
  1827. info->default_power1);
  1828. } else {
  1829. rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
  1830. rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
  1831. (info->default_power1 & 0x3) |
  1832. ((info->default_power1 & 0xC) << 1));
  1833. }
  1834. rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
  1835. rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
  1836. if (rf->channel <= 14) {
  1837. rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
  1838. rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
  1839. info->default_power2);
  1840. } else {
  1841. rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
  1842. rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
  1843. (info->default_power2 & 0x3) |
  1844. ((info->default_power2 & 0xC) << 1));
  1845. }
  1846. rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
  1847. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  1848. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  1849. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  1850. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
  1851. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
  1852. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  1853. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  1854. if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
  1855. if (rf->channel <= 14) {
  1856. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  1857. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  1858. }
  1859. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
  1860. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
  1861. } else {
  1862. switch (rt2x00dev->default_ant.tx_chain_num) {
  1863. case 1:
  1864. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  1865. case 2:
  1866. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
  1867. break;
  1868. }
  1869. switch (rt2x00dev->default_ant.rx_chain_num) {
  1870. case 1:
  1871. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  1872. case 2:
  1873. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
  1874. break;
  1875. }
  1876. }
  1877. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  1878. rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
  1879. rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
  1880. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  1881. if (conf_is_ht40(conf)) {
  1882. rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
  1883. rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
  1884. } else {
  1885. rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
  1886. rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
  1887. }
  1888. if (rf->channel <= 14) {
  1889. rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
  1890. rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
  1891. rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
  1892. rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
  1893. rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
  1894. rfcsr = 0x4c;
  1895. rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
  1896. drv_data->txmixer_gain_24g);
  1897. rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  1898. rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
  1899. rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
  1900. rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
  1901. rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
  1902. rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
  1903. rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  1904. rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
  1905. } else {
  1906. rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
  1907. rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
  1908. rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
  1909. rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
  1910. rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
  1911. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  1912. rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
  1913. rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
  1914. rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
  1915. rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
  1916. rfcsr = 0x7a;
  1917. rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
  1918. drv_data->txmixer_gain_5g);
  1919. rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
  1920. rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
  1921. if (rf->channel <= 64) {
  1922. rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
  1923. rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
  1924. rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
  1925. } else if (rf->channel <= 128) {
  1926. rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
  1927. rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
  1928. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1929. } else {
  1930. rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
  1931. rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
  1932. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  1933. }
  1934. rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
  1935. rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
  1936. rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
  1937. }
  1938. rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
  1939. rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
  1940. if (rf->channel <= 14)
  1941. rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
  1942. else
  1943. rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
  1944. rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
  1945. rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
  1946. rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
  1947. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  1948. }
  1949. static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
  1950. struct ieee80211_conf *conf,
  1951. struct rf_channel *rf,
  1952. struct channel_info *info)
  1953. {
  1954. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  1955. u8 txrx_agc_fc;
  1956. u8 txrx_h20m;
  1957. u8 rfcsr;
  1958. u8 bbp;
  1959. const bool txbf_enabled = false; /* TODO */
  1960. /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
  1961. rt2800_bbp_read(rt2x00dev, 109, &bbp);
  1962. rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
  1963. rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
  1964. rt2800_bbp_write(rt2x00dev, 109, bbp);
  1965. rt2800_bbp_read(rt2x00dev, 110, &bbp);
  1966. rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
  1967. rt2800_bbp_write(rt2x00dev, 110, bbp);
  1968. if (rf->channel <= 14) {
  1969. /* Restore BBP 25 & 26 for 2.4 GHz */
  1970. rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
  1971. rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
  1972. } else {
  1973. /* Hard code BBP 25 & 26 for 5GHz */
  1974. /* Enable IQ Phase correction */
  1975. rt2800_bbp_write(rt2x00dev, 25, 0x09);
  1976. /* Setup IQ Phase correction value */
  1977. rt2800_bbp_write(rt2x00dev, 26, 0xff);
  1978. }
  1979. rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  1980. rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
  1981. rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
  1982. rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
  1983. rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
  1984. rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
  1985. rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
  1986. if (rf->channel <= 14)
  1987. rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
  1988. else
  1989. rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
  1990. rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
  1991. rt2800_rfcsr_read(rt2x00dev, 53, &rfcsr);
  1992. if (rf->channel <= 14) {
  1993. rfcsr = 0;
  1994. rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
  1995. info->default_power1 & 0x1f);
  1996. } else {
  1997. if (rt2x00_is_usb(rt2x00dev))
  1998. rfcsr = 0x40;
  1999. rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
  2000. ((info->default_power1 & 0x18) << 1) |
  2001. (info->default_power1 & 7));
  2002. }
  2003. rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
  2004. rt2800_rfcsr_read(rt2x00dev, 55, &rfcsr);
  2005. if (rf->channel <= 14) {
  2006. rfcsr = 0;
  2007. rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
  2008. info->default_power2 & 0x1f);
  2009. } else {
  2010. if (rt2x00_is_usb(rt2x00dev))
  2011. rfcsr = 0x40;
  2012. rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
  2013. ((info->default_power2 & 0x18) << 1) |
  2014. (info->default_power2 & 7));
  2015. }
  2016. rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
  2017. rt2800_rfcsr_read(rt2x00dev, 54, &rfcsr);
  2018. if (rf->channel <= 14) {
  2019. rfcsr = 0;
  2020. rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
  2021. info->default_power3 & 0x1f);
  2022. } else {
  2023. if (rt2x00_is_usb(rt2x00dev))
  2024. rfcsr = 0x40;
  2025. rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
  2026. ((info->default_power3 & 0x18) << 1) |
  2027. (info->default_power3 & 7));
  2028. }
  2029. rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
  2030. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  2031. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  2032. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  2033. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
  2034. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
  2035. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  2036. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  2037. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  2038. rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
  2039. switch (rt2x00dev->default_ant.tx_chain_num) {
  2040. case 3:
  2041. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
  2042. /* fallthrough */
  2043. case 2:
  2044. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  2045. /* fallthrough */
  2046. case 1:
  2047. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  2048. break;
  2049. }
  2050. switch (rt2x00dev->default_ant.rx_chain_num) {
  2051. case 3:
  2052. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
  2053. /* fallthrough */
  2054. case 2:
  2055. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  2056. /* fallthrough */
  2057. case 1:
  2058. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  2059. break;
  2060. }
  2061. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  2062. rt2800_adjust_freq_offset(rt2x00dev);
  2063. if (conf_is_ht40(conf)) {
  2064. txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
  2065. RFCSR24_TX_AGC_FC);
  2066. txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
  2067. RFCSR24_TX_H20M);
  2068. } else {
  2069. txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
  2070. RFCSR24_TX_AGC_FC);
  2071. txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
  2072. RFCSR24_TX_H20M);
  2073. }
  2074. /* NOTE: the reference driver does not writes the new value
  2075. * back to RFCSR 32
  2076. */
  2077. rt2800_rfcsr_read(rt2x00dev, 32, &rfcsr);
  2078. rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
  2079. if (rf->channel <= 14)
  2080. rfcsr = 0xa0;
  2081. else
  2082. rfcsr = 0x80;
  2083. rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
  2084. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  2085. rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
  2086. rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
  2087. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  2088. /* Band selection */
  2089. rt2800_rfcsr_read(rt2x00dev, 36, &rfcsr);
  2090. if (rf->channel <= 14)
  2091. rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
  2092. else
  2093. rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
  2094. rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
  2095. rt2800_rfcsr_read(rt2x00dev, 34, &rfcsr);
  2096. if (rf->channel <= 14)
  2097. rfcsr = 0x3c;
  2098. else
  2099. rfcsr = 0x20;
  2100. rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
  2101. rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
  2102. if (rf->channel <= 14)
  2103. rfcsr = 0x1a;
  2104. else
  2105. rfcsr = 0x12;
  2106. rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
  2107. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  2108. if (rf->channel >= 1 && rf->channel <= 14)
  2109. rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
  2110. else if (rf->channel >= 36 && rf->channel <= 64)
  2111. rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
  2112. else if (rf->channel >= 100 && rf->channel <= 128)
  2113. rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
  2114. else
  2115. rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
  2116. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  2117. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  2118. rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
  2119. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  2120. rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
  2121. if (rf->channel <= 14) {
  2122. rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
  2123. rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
  2124. } else {
  2125. rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
  2126. rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
  2127. }
  2128. rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
  2129. rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
  2130. rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
  2131. rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
  2132. if (rf->channel <= 14) {
  2133. rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
  2134. rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
  2135. } else {
  2136. rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
  2137. rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
  2138. }
  2139. rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
  2140. rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
  2141. if (rf->channel <= 14)
  2142. rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
  2143. else
  2144. rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
  2145. if (txbf_enabled)
  2146. rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
  2147. rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
  2148. rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
  2149. rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
  2150. rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
  2151. rt2800_rfcsr_read(rt2x00dev, 57, &rfcsr);
  2152. if (rf->channel <= 14)
  2153. rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
  2154. else
  2155. rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
  2156. rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
  2157. if (rf->channel <= 14) {
  2158. rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
  2159. rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
  2160. } else {
  2161. rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
  2162. rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
  2163. }
  2164. /* Initiate VCO calibration */
  2165. rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  2166. if (rf->channel <= 14) {
  2167. rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  2168. } else {
  2169. rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
  2170. rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
  2171. rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
  2172. rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
  2173. rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
  2174. rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  2175. }
  2176. rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  2177. if (rf->channel >= 1 && rf->channel <= 14) {
  2178. rfcsr = 0x23;
  2179. if (txbf_enabled)
  2180. rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
  2181. rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
  2182. rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
  2183. } else if (rf->channel >= 36 && rf->channel <= 64) {
  2184. rfcsr = 0x36;
  2185. if (txbf_enabled)
  2186. rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
  2187. rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
  2188. rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
  2189. } else if (rf->channel >= 100 && rf->channel <= 128) {
  2190. rfcsr = 0x32;
  2191. if (txbf_enabled)
  2192. rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
  2193. rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
  2194. rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
  2195. } else {
  2196. rfcsr = 0x30;
  2197. if (txbf_enabled)
  2198. rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
  2199. rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
  2200. rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
  2201. }
  2202. }
  2203. #define POWER_BOUND 0x27
  2204. #define POWER_BOUND_5G 0x2b
  2205. static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
  2206. struct ieee80211_conf *conf,
  2207. struct rf_channel *rf,
  2208. struct channel_info *info)
  2209. {
  2210. u8 rfcsr;
  2211. rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  2212. rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
  2213. rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
  2214. rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
  2215. rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
  2216. rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
  2217. if (info->default_power1 > POWER_BOUND)
  2218. rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
  2219. else
  2220. rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
  2221. rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
  2222. rt2800_adjust_freq_offset(rt2x00dev);
  2223. if (rf->channel <= 14) {
  2224. if (rf->channel == 6)
  2225. rt2800_bbp_write(rt2x00dev, 68, 0x0c);
  2226. else
  2227. rt2800_bbp_write(rt2x00dev, 68, 0x0b);
  2228. if (rf->channel >= 1 && rf->channel <= 6)
  2229. rt2800_bbp_write(rt2x00dev, 59, 0x0f);
  2230. else if (rf->channel >= 7 && rf->channel <= 11)
  2231. rt2800_bbp_write(rt2x00dev, 59, 0x0e);
  2232. else if (rf->channel >= 12 && rf->channel <= 14)
  2233. rt2800_bbp_write(rt2x00dev, 59, 0x0d);
  2234. }
  2235. }
  2236. static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
  2237. struct ieee80211_conf *conf,
  2238. struct rf_channel *rf,
  2239. struct channel_info *info)
  2240. {
  2241. u8 rfcsr;
  2242. rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  2243. rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
  2244. rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
  2245. rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
  2246. rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  2247. if (info->default_power1 > POWER_BOUND)
  2248. rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
  2249. else
  2250. rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
  2251. if (info->default_power2 > POWER_BOUND)
  2252. rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
  2253. else
  2254. rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
  2255. rt2800_adjust_freq_offset(rt2x00dev);
  2256. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  2257. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  2258. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  2259. if ( rt2x00dev->default_ant.tx_chain_num == 2 )
  2260. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  2261. else
  2262. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
  2263. if ( rt2x00dev->default_ant.rx_chain_num == 2 )
  2264. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  2265. else
  2266. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
  2267. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  2268. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  2269. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  2270. rt2800_rfcsr_write(rt2x00dev, 31, 80);
  2271. }
  2272. static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
  2273. struct ieee80211_conf *conf,
  2274. struct rf_channel *rf,
  2275. struct channel_info *info)
  2276. {
  2277. u8 rfcsr;
  2278. rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
  2279. rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
  2280. rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
  2281. rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
  2282. rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
  2283. rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
  2284. if (info->default_power1 > POWER_BOUND)
  2285. rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
  2286. else
  2287. rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
  2288. rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
  2289. if (rt2x00_rt(rt2x00dev, RT5392)) {
  2290. rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
  2291. if (info->default_power2 > POWER_BOUND)
  2292. rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
  2293. else
  2294. rt2x00_set_field8(&rfcsr, RFCSR50_TX,
  2295. info->default_power2);
  2296. rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
  2297. }
  2298. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  2299. if (rt2x00_rt(rt2x00dev, RT5392)) {
  2300. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  2301. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  2302. }
  2303. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  2304. rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
  2305. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
  2306. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
  2307. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  2308. rt2800_adjust_freq_offset(rt2x00dev);
  2309. if (rf->channel <= 14) {
  2310. int idx = rf->channel-1;
  2311. if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
  2312. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
  2313. /* r55/r59 value array of channel 1~14 */
  2314. static const char r55_bt_rev[] = {0x83, 0x83,
  2315. 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
  2316. 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
  2317. static const char r59_bt_rev[] = {0x0e, 0x0e,
  2318. 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
  2319. 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
  2320. rt2800_rfcsr_write(rt2x00dev, 55,
  2321. r55_bt_rev[idx]);
  2322. rt2800_rfcsr_write(rt2x00dev, 59,
  2323. r59_bt_rev[idx]);
  2324. } else {
  2325. static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
  2326. 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
  2327. 0x88, 0x88, 0x86, 0x85, 0x84};
  2328. rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
  2329. }
  2330. } else {
  2331. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
  2332. static const char r55_nonbt_rev[] = {0x23, 0x23,
  2333. 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
  2334. 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
  2335. static const char r59_nonbt_rev[] = {0x07, 0x07,
  2336. 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
  2337. 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
  2338. rt2800_rfcsr_write(rt2x00dev, 55,
  2339. r55_nonbt_rev[idx]);
  2340. rt2800_rfcsr_write(rt2x00dev, 59,
  2341. r59_nonbt_rev[idx]);
  2342. } else if (rt2x00_rt(rt2x00dev, RT5390) ||
  2343. rt2x00_rt(rt2x00dev, RT5392)) {
  2344. static const char r59_non_bt[] = {0x8f, 0x8f,
  2345. 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
  2346. 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
  2347. rt2800_rfcsr_write(rt2x00dev, 59,
  2348. r59_non_bt[idx]);
  2349. }
  2350. }
  2351. }
  2352. }
  2353. static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
  2354. struct ieee80211_conf *conf,
  2355. struct rf_channel *rf,
  2356. struct channel_info *info)
  2357. {
  2358. u8 rfcsr, ep_reg;
  2359. u32 reg;
  2360. int power_bound;
  2361. /* TODO */
  2362. const bool is_11b = false;
  2363. const bool is_type_ep = false;
  2364. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  2365. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
  2366. (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
  2367. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  2368. /* Order of values on rf_channel entry: N, K, mod, R */
  2369. rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
  2370. rt2800_rfcsr_read(rt2x00dev, 9, &rfcsr);
  2371. rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
  2372. rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
  2373. rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
  2374. rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
  2375. rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
  2376. rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
  2377. rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
  2378. rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
  2379. if (rf->channel <= 14) {
  2380. rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
  2381. /* FIXME: RF11 owerwrite ? */
  2382. rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
  2383. rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
  2384. rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
  2385. rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
  2386. rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
  2387. rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
  2388. rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
  2389. rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
  2390. rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
  2391. rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
  2392. rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
  2393. rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
  2394. rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
  2395. rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
  2396. rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
  2397. rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
  2398. rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
  2399. rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
  2400. rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
  2401. rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
  2402. rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
  2403. rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
  2404. rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
  2405. rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
  2406. rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
  2407. rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
  2408. rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
  2409. rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
  2410. /* TODO RF27 <- tssi */
  2411. rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
  2412. rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
  2413. rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
  2414. if (is_11b) {
  2415. /* CCK */
  2416. rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
  2417. rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
  2418. if (is_type_ep)
  2419. rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
  2420. else
  2421. rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
  2422. } else {
  2423. /* OFDM */
  2424. if (is_type_ep)
  2425. rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
  2426. else
  2427. rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
  2428. }
  2429. power_bound = POWER_BOUND;
  2430. ep_reg = 0x2;
  2431. } else {
  2432. rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
  2433. /* FIMXE: RF11 overwrite */
  2434. rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
  2435. rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
  2436. rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
  2437. rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  2438. rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
  2439. rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
  2440. rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
  2441. rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
  2442. rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
  2443. rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
  2444. rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
  2445. rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
  2446. rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
  2447. rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
  2448. /* TODO RF27 <- tssi */
  2449. if (rf->channel >= 36 && rf->channel <= 64) {
  2450. rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
  2451. rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
  2452. rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
  2453. rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
  2454. if (rf->channel <= 50)
  2455. rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
  2456. else if (rf->channel >= 52)
  2457. rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
  2458. rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
  2459. rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
  2460. rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
  2461. rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
  2462. rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
  2463. rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
  2464. rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
  2465. if (rf->channel <= 50) {
  2466. rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
  2467. rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
  2468. } else if (rf->channel >= 52) {
  2469. rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
  2470. rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
  2471. }
  2472. rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
  2473. rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
  2474. rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
  2475. } else if (rf->channel >= 100 && rf->channel <= 165) {
  2476. rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
  2477. rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
  2478. rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
  2479. if (rf->channel <= 153) {
  2480. rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
  2481. rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
  2482. } else if (rf->channel >= 155) {
  2483. rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
  2484. rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
  2485. }
  2486. if (rf->channel <= 138) {
  2487. rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
  2488. rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
  2489. rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
  2490. rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
  2491. } else if (rf->channel >= 140) {
  2492. rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
  2493. rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
  2494. rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
  2495. rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
  2496. }
  2497. if (rf->channel <= 124)
  2498. rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
  2499. else if (rf->channel >= 126)
  2500. rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
  2501. if (rf->channel <= 138)
  2502. rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
  2503. else if (rf->channel >= 140)
  2504. rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
  2505. rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
  2506. if (rf->channel <= 138)
  2507. rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
  2508. else if (rf->channel >= 140)
  2509. rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
  2510. if (rf->channel <= 128)
  2511. rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
  2512. else if (rf->channel >= 130)
  2513. rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
  2514. if (rf->channel <= 116)
  2515. rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
  2516. else if (rf->channel >= 118)
  2517. rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
  2518. if (rf->channel <= 138)
  2519. rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
  2520. else if (rf->channel >= 140)
  2521. rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
  2522. if (rf->channel <= 116)
  2523. rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
  2524. else if (rf->channel >= 118)
  2525. rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
  2526. }
  2527. power_bound = POWER_BOUND_5G;
  2528. ep_reg = 0x3;
  2529. }
  2530. rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
  2531. if (info->default_power1 > power_bound)
  2532. rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
  2533. else
  2534. rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
  2535. if (is_type_ep)
  2536. rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
  2537. rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
  2538. rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
  2539. if (info->default_power2 > power_bound)
  2540. rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
  2541. else
  2542. rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
  2543. if (is_type_ep)
  2544. rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
  2545. rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
  2546. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  2547. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  2548. rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
  2549. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
  2550. rt2x00dev->default_ant.tx_chain_num >= 1);
  2551. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
  2552. rt2x00dev->default_ant.tx_chain_num == 2);
  2553. rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
  2554. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
  2555. rt2x00dev->default_ant.rx_chain_num >= 1);
  2556. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
  2557. rt2x00dev->default_ant.rx_chain_num == 2);
  2558. rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
  2559. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  2560. rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
  2561. if (conf_is_ht40(conf))
  2562. rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
  2563. else
  2564. rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  2565. if (!is_11b) {
  2566. rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  2567. rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  2568. }
  2569. /* TODO proper frequency adjustment */
  2570. rt2800_adjust_freq_offset(rt2x00dev);
  2571. /* TODO merge with others */
  2572. rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  2573. rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  2574. rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  2575. /* BBP settings */
  2576. rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
  2577. rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
  2578. rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
  2579. rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
  2580. rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
  2581. rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
  2582. rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
  2583. /* GLRT band configuration */
  2584. rt2800_bbp_write(rt2x00dev, 195, 128);
  2585. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
  2586. rt2800_bbp_write(rt2x00dev, 195, 129);
  2587. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
  2588. rt2800_bbp_write(rt2x00dev, 195, 130);
  2589. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
  2590. rt2800_bbp_write(rt2x00dev, 195, 131);
  2591. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
  2592. rt2800_bbp_write(rt2x00dev, 195, 133);
  2593. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
  2594. rt2800_bbp_write(rt2x00dev, 195, 124);
  2595. rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
  2596. }
  2597. static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
  2598. const unsigned int word,
  2599. const u8 value)
  2600. {
  2601. u8 chain, reg;
  2602. for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
  2603. rt2800_bbp_read(rt2x00dev, 27, &reg);
  2604. rt2x00_set_field8(&reg, BBP27_RX_CHAIN_SEL, chain);
  2605. rt2800_bbp_write(rt2x00dev, 27, reg);
  2606. rt2800_bbp_write(rt2x00dev, word, value);
  2607. }
  2608. }
  2609. static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
  2610. {
  2611. u8 cal;
  2612. /* TX0 IQ Gain */
  2613. rt2800_bbp_write(rt2x00dev, 158, 0x2c);
  2614. if (channel <= 14)
  2615. cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
  2616. else if (channel >= 36 && channel <= 64)
  2617. cal = rt2x00_eeprom_byte(rt2x00dev,
  2618. EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
  2619. else if (channel >= 100 && channel <= 138)
  2620. cal = rt2x00_eeprom_byte(rt2x00dev,
  2621. EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
  2622. else if (channel >= 140 && channel <= 165)
  2623. cal = rt2x00_eeprom_byte(rt2x00dev,
  2624. EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
  2625. else
  2626. cal = 0;
  2627. rt2800_bbp_write(rt2x00dev, 159, cal);
  2628. /* TX0 IQ Phase */
  2629. rt2800_bbp_write(rt2x00dev, 158, 0x2d);
  2630. if (channel <= 14)
  2631. cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
  2632. else if (channel >= 36 && channel <= 64)
  2633. cal = rt2x00_eeprom_byte(rt2x00dev,
  2634. EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
  2635. else if (channel >= 100 && channel <= 138)
  2636. cal = rt2x00_eeprom_byte(rt2x00dev,
  2637. EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
  2638. else if (channel >= 140 && channel <= 165)
  2639. cal = rt2x00_eeprom_byte(rt2x00dev,
  2640. EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
  2641. else
  2642. cal = 0;
  2643. rt2800_bbp_write(rt2x00dev, 159, cal);
  2644. /* TX1 IQ Gain */
  2645. rt2800_bbp_write(rt2x00dev, 158, 0x4a);
  2646. if (channel <= 14)
  2647. cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
  2648. else if (channel >= 36 && channel <= 64)
  2649. cal = rt2x00_eeprom_byte(rt2x00dev,
  2650. EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
  2651. else if (channel >= 100 && channel <= 138)
  2652. cal = rt2x00_eeprom_byte(rt2x00dev,
  2653. EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
  2654. else if (channel >= 140 && channel <= 165)
  2655. cal = rt2x00_eeprom_byte(rt2x00dev,
  2656. EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
  2657. else
  2658. cal = 0;
  2659. rt2800_bbp_write(rt2x00dev, 159, cal);
  2660. /* TX1 IQ Phase */
  2661. rt2800_bbp_write(rt2x00dev, 158, 0x4b);
  2662. if (channel <= 14)
  2663. cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
  2664. else if (channel >= 36 && channel <= 64)
  2665. cal = rt2x00_eeprom_byte(rt2x00dev,
  2666. EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
  2667. else if (channel >= 100 && channel <= 138)
  2668. cal = rt2x00_eeprom_byte(rt2x00dev,
  2669. EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
  2670. else if (channel >= 140 && channel <= 165)
  2671. cal = rt2x00_eeprom_byte(rt2x00dev,
  2672. EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
  2673. else
  2674. cal = 0;
  2675. rt2800_bbp_write(rt2x00dev, 159, cal);
  2676. /* FIXME: possible RX0, RX1 callibration ? */
  2677. /* RF IQ compensation control */
  2678. rt2800_bbp_write(rt2x00dev, 158, 0x04);
  2679. cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
  2680. rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
  2681. /* RF IQ imbalance compensation control */
  2682. rt2800_bbp_write(rt2x00dev, 158, 0x03);
  2683. cal = rt2x00_eeprom_byte(rt2x00dev,
  2684. EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
  2685. rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
  2686. }
  2687. static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
  2688. unsigned int channel,
  2689. char txpower)
  2690. {
  2691. if (rt2x00_rt(rt2x00dev, RT3593))
  2692. txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
  2693. if (channel <= 14)
  2694. return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
  2695. if (rt2x00_rt(rt2x00dev, RT3593))
  2696. return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
  2697. MAX_A_TXPOWER_3593);
  2698. else
  2699. return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
  2700. }
  2701. static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
  2702. struct ieee80211_conf *conf,
  2703. struct rf_channel *rf,
  2704. struct channel_info *info)
  2705. {
  2706. u32 reg;
  2707. unsigned int tx_pin;
  2708. u8 bbp, rfcsr;
  2709. info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
  2710. info->default_power1);
  2711. info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
  2712. info->default_power2);
  2713. if (rt2x00dev->default_ant.tx_chain_num > 2)
  2714. info->default_power3 =
  2715. rt2800_txpower_to_dev(rt2x00dev, rf->channel,
  2716. info->default_power3);
  2717. switch (rt2x00dev->chip.rf) {
  2718. case RF2020:
  2719. case RF3020:
  2720. case RF3021:
  2721. case RF3022:
  2722. case RF3320:
  2723. rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
  2724. break;
  2725. case RF3052:
  2726. rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
  2727. break;
  2728. case RF3053:
  2729. rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
  2730. break;
  2731. case RF3290:
  2732. rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
  2733. break;
  2734. case RF3322:
  2735. rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
  2736. break;
  2737. case RF3070:
  2738. case RF5360:
  2739. case RF5362:
  2740. case RF5370:
  2741. case RF5372:
  2742. case RF5390:
  2743. case RF5392:
  2744. rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
  2745. break;
  2746. case RF5592:
  2747. rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
  2748. break;
  2749. default:
  2750. rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
  2751. }
  2752. if (rt2x00_rf(rt2x00dev, RF3070) ||
  2753. rt2x00_rf(rt2x00dev, RF3290) ||
  2754. rt2x00_rf(rt2x00dev, RF3322) ||
  2755. rt2x00_rf(rt2x00dev, RF5360) ||
  2756. rt2x00_rf(rt2x00dev, RF5362) ||
  2757. rt2x00_rf(rt2x00dev, RF5370) ||
  2758. rt2x00_rf(rt2x00dev, RF5372) ||
  2759. rt2x00_rf(rt2x00dev, RF5390) ||
  2760. rt2x00_rf(rt2x00dev, RF5392)) {
  2761. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  2762. rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
  2763. rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
  2764. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  2765. rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  2766. rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  2767. rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  2768. }
  2769. /*
  2770. * Change BBP settings
  2771. */
  2772. if (rt2x00_rt(rt2x00dev, RT3352)) {
  2773. rt2800_bbp_write(rt2x00dev, 27, 0x0);
  2774. rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
  2775. rt2800_bbp_write(rt2x00dev, 27, 0x20);
  2776. rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
  2777. } else if (rt2x00_rt(rt2x00dev, RT3593)) {
  2778. if (rf->channel > 14) {
  2779. /* Disable CCK Packet detection on 5GHz */
  2780. rt2800_bbp_write(rt2x00dev, 70, 0x00);
  2781. } else {
  2782. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  2783. }
  2784. if (conf_is_ht40(conf))
  2785. rt2800_bbp_write(rt2x00dev, 105, 0x04);
  2786. else
  2787. rt2800_bbp_write(rt2x00dev, 105, 0x34);
  2788. rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
  2789. rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
  2790. rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
  2791. rt2800_bbp_write(rt2x00dev, 77, 0x98);
  2792. } else {
  2793. rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
  2794. rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
  2795. rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
  2796. rt2800_bbp_write(rt2x00dev, 86, 0);
  2797. }
  2798. if (rf->channel <= 14) {
  2799. if (!rt2x00_rt(rt2x00dev, RT5390) &&
  2800. !rt2x00_rt(rt2x00dev, RT5392)) {
  2801. if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
  2802. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  2803. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  2804. } else {
  2805. if (rt2x00_rt(rt2x00dev, RT3593))
  2806. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  2807. else
  2808. rt2800_bbp_write(rt2x00dev, 82, 0x84);
  2809. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  2810. }
  2811. if (rt2x00_rt(rt2x00dev, RT3593))
  2812. rt2800_bbp_write(rt2x00dev, 83, 0x8a);
  2813. }
  2814. } else {
  2815. if (rt2x00_rt(rt2x00dev, RT3572))
  2816. rt2800_bbp_write(rt2x00dev, 82, 0x94);
  2817. else if (rt2x00_rt(rt2x00dev, RT3593))
  2818. rt2800_bbp_write(rt2x00dev, 82, 0x82);
  2819. else
  2820. rt2800_bbp_write(rt2x00dev, 82, 0xf2);
  2821. if (rt2x00_rt(rt2x00dev, RT3593))
  2822. rt2800_bbp_write(rt2x00dev, 83, 0x9a);
  2823. if (rt2x00_has_cap_external_lna_a(rt2x00dev))
  2824. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  2825. else
  2826. rt2800_bbp_write(rt2x00dev, 75, 0x50);
  2827. }
  2828. rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
  2829. rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
  2830. rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
  2831. rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
  2832. rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
  2833. if (rt2x00_rt(rt2x00dev, RT3572))
  2834. rt2800_rfcsr_write(rt2x00dev, 8, 0);
  2835. tx_pin = 0;
  2836. switch (rt2x00dev->default_ant.tx_chain_num) {
  2837. case 3:
  2838. /* Turn on tertiary PAs */
  2839. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
  2840. rf->channel > 14);
  2841. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
  2842. rf->channel <= 14);
  2843. /* fall-through */
  2844. case 2:
  2845. /* Turn on secondary PAs */
  2846. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
  2847. rf->channel > 14);
  2848. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
  2849. rf->channel <= 14);
  2850. /* fall-through */
  2851. case 1:
  2852. /* Turn on primary PAs */
  2853. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
  2854. rf->channel > 14);
  2855. if (rt2x00_has_cap_bt_coexist(rt2x00dev))
  2856. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
  2857. else
  2858. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
  2859. rf->channel <= 14);
  2860. break;
  2861. }
  2862. switch (rt2x00dev->default_ant.rx_chain_num) {
  2863. case 3:
  2864. /* Turn on tertiary LNAs */
  2865. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
  2866. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
  2867. /* fall-through */
  2868. case 2:
  2869. /* Turn on secondary LNAs */
  2870. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
  2871. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
  2872. /* fall-through */
  2873. case 1:
  2874. /* Turn on primary LNAs */
  2875. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
  2876. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
  2877. break;
  2878. }
  2879. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
  2880. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
  2881. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  2882. if (rt2x00_rt(rt2x00dev, RT3572)) {
  2883. rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
  2884. /* AGC init */
  2885. if (rf->channel <= 14)
  2886. reg = 0x1c + (2 * rt2x00dev->lna_gain);
  2887. else
  2888. reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
  2889. rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
  2890. }
  2891. if (rt2x00_rt(rt2x00dev, RT3593)) {
  2892. rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
  2893. /* Band selection */
  2894. if (rt2x00_is_usb(rt2x00dev) ||
  2895. rt2x00_is_pcie(rt2x00dev)) {
  2896. /* GPIO #8 controls all paths */
  2897. rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
  2898. if (rf->channel <= 14)
  2899. rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
  2900. else
  2901. rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
  2902. }
  2903. /* LNA PE control. */
  2904. if (rt2x00_is_usb(rt2x00dev)) {
  2905. /* GPIO #4 controls PE0 and PE1,
  2906. * GPIO #7 controls PE2
  2907. */
  2908. rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
  2909. rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
  2910. rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
  2911. rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
  2912. } else if (rt2x00_is_pcie(rt2x00dev)) {
  2913. /* GPIO #4 controls PE0, PE1 and PE2 */
  2914. rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
  2915. rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
  2916. }
  2917. rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
  2918. /* AGC init */
  2919. if (rf->channel <= 14)
  2920. reg = 0x1c + 2 * rt2x00dev->lna_gain;
  2921. else
  2922. reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
  2923. rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
  2924. usleep_range(1000, 1500);
  2925. }
  2926. if (rt2x00_rt(rt2x00dev, RT5592)) {
  2927. rt2800_bbp_write(rt2x00dev, 195, 141);
  2928. rt2800_bbp_write(rt2x00dev, 196, conf_is_ht40(conf) ? 0x10 : 0x1a);
  2929. /* AGC init */
  2930. reg = (rf->channel <= 14 ? 0x1c : 0x24) + 2 * rt2x00dev->lna_gain;
  2931. rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
  2932. rt2800_iq_calibrate(rt2x00dev, rf->channel);
  2933. }
  2934. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  2935. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
  2936. rt2800_bbp_write(rt2x00dev, 4, bbp);
  2937. rt2800_bbp_read(rt2x00dev, 3, &bbp);
  2938. rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
  2939. rt2800_bbp_write(rt2x00dev, 3, bbp);
  2940. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
  2941. if (conf_is_ht40(conf)) {
  2942. rt2800_bbp_write(rt2x00dev, 69, 0x1a);
  2943. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  2944. rt2800_bbp_write(rt2x00dev, 73, 0x16);
  2945. } else {
  2946. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  2947. rt2800_bbp_write(rt2x00dev, 70, 0x08);
  2948. rt2800_bbp_write(rt2x00dev, 73, 0x11);
  2949. }
  2950. }
  2951. msleep(1);
  2952. /*
  2953. * Clear channel statistic counters
  2954. */
  2955. rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
  2956. rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
  2957. rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
  2958. /*
  2959. * Clear update flag
  2960. */
  2961. if (rt2x00_rt(rt2x00dev, RT3352)) {
  2962. rt2800_bbp_read(rt2x00dev, 49, &bbp);
  2963. rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
  2964. rt2800_bbp_write(rt2x00dev, 49, bbp);
  2965. }
  2966. }
  2967. static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
  2968. {
  2969. u8 tssi_bounds[9];
  2970. u8 current_tssi;
  2971. u16 eeprom;
  2972. u8 step;
  2973. int i;
  2974. /*
  2975. * First check if temperature compensation is supported.
  2976. */
  2977. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
  2978. if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
  2979. return 0;
  2980. /*
  2981. * Read TSSI boundaries for temperature compensation from
  2982. * the EEPROM.
  2983. *
  2984. * Array idx 0 1 2 3 4 5 6 7 8
  2985. * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
  2986. * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
  2987. */
  2988. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
  2989. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
  2990. tssi_bounds[0] = rt2x00_get_field16(eeprom,
  2991. EEPROM_TSSI_BOUND_BG1_MINUS4);
  2992. tssi_bounds[1] = rt2x00_get_field16(eeprom,
  2993. EEPROM_TSSI_BOUND_BG1_MINUS3);
  2994. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
  2995. tssi_bounds[2] = rt2x00_get_field16(eeprom,
  2996. EEPROM_TSSI_BOUND_BG2_MINUS2);
  2997. tssi_bounds[3] = rt2x00_get_field16(eeprom,
  2998. EEPROM_TSSI_BOUND_BG2_MINUS1);
  2999. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
  3000. tssi_bounds[4] = rt2x00_get_field16(eeprom,
  3001. EEPROM_TSSI_BOUND_BG3_REF);
  3002. tssi_bounds[5] = rt2x00_get_field16(eeprom,
  3003. EEPROM_TSSI_BOUND_BG3_PLUS1);
  3004. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
  3005. tssi_bounds[6] = rt2x00_get_field16(eeprom,
  3006. EEPROM_TSSI_BOUND_BG4_PLUS2);
  3007. tssi_bounds[7] = rt2x00_get_field16(eeprom,
  3008. EEPROM_TSSI_BOUND_BG4_PLUS3);
  3009. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
  3010. tssi_bounds[8] = rt2x00_get_field16(eeprom,
  3011. EEPROM_TSSI_BOUND_BG5_PLUS4);
  3012. step = rt2x00_get_field16(eeprom,
  3013. EEPROM_TSSI_BOUND_BG5_AGC_STEP);
  3014. } else {
  3015. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
  3016. tssi_bounds[0] = rt2x00_get_field16(eeprom,
  3017. EEPROM_TSSI_BOUND_A1_MINUS4);
  3018. tssi_bounds[1] = rt2x00_get_field16(eeprom,
  3019. EEPROM_TSSI_BOUND_A1_MINUS3);
  3020. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
  3021. tssi_bounds[2] = rt2x00_get_field16(eeprom,
  3022. EEPROM_TSSI_BOUND_A2_MINUS2);
  3023. tssi_bounds[3] = rt2x00_get_field16(eeprom,
  3024. EEPROM_TSSI_BOUND_A2_MINUS1);
  3025. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
  3026. tssi_bounds[4] = rt2x00_get_field16(eeprom,
  3027. EEPROM_TSSI_BOUND_A3_REF);
  3028. tssi_bounds[5] = rt2x00_get_field16(eeprom,
  3029. EEPROM_TSSI_BOUND_A3_PLUS1);
  3030. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
  3031. tssi_bounds[6] = rt2x00_get_field16(eeprom,
  3032. EEPROM_TSSI_BOUND_A4_PLUS2);
  3033. tssi_bounds[7] = rt2x00_get_field16(eeprom,
  3034. EEPROM_TSSI_BOUND_A4_PLUS3);
  3035. rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
  3036. tssi_bounds[8] = rt2x00_get_field16(eeprom,
  3037. EEPROM_TSSI_BOUND_A5_PLUS4);
  3038. step = rt2x00_get_field16(eeprom,
  3039. EEPROM_TSSI_BOUND_A5_AGC_STEP);
  3040. }
  3041. /*
  3042. * Check if temperature compensation is supported.
  3043. */
  3044. if (tssi_bounds[4] == 0xff || step == 0xff)
  3045. return 0;
  3046. /*
  3047. * Read current TSSI (BBP 49).
  3048. */
  3049. rt2800_bbp_read(rt2x00dev, 49, &current_tssi);
  3050. /*
  3051. * Compare TSSI value (BBP49) with the compensation boundaries
  3052. * from the EEPROM and increase or decrease tx power.
  3053. */
  3054. for (i = 0; i <= 3; i++) {
  3055. if (current_tssi > tssi_bounds[i])
  3056. break;
  3057. }
  3058. if (i == 4) {
  3059. for (i = 8; i >= 5; i--) {
  3060. if (current_tssi < tssi_bounds[i])
  3061. break;
  3062. }
  3063. }
  3064. return (i - 4) * step;
  3065. }
  3066. static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
  3067. enum ieee80211_band band)
  3068. {
  3069. u16 eeprom;
  3070. u8 comp_en;
  3071. u8 comp_type;
  3072. int comp_value = 0;
  3073. rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
  3074. /*
  3075. * HT40 compensation not required.
  3076. */
  3077. if (eeprom == 0xffff ||
  3078. !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
  3079. return 0;
  3080. if (band == IEEE80211_BAND_2GHZ) {
  3081. comp_en = rt2x00_get_field16(eeprom,
  3082. EEPROM_TXPOWER_DELTA_ENABLE_2G);
  3083. if (comp_en) {
  3084. comp_type = rt2x00_get_field16(eeprom,
  3085. EEPROM_TXPOWER_DELTA_TYPE_2G);
  3086. comp_value = rt2x00_get_field16(eeprom,
  3087. EEPROM_TXPOWER_DELTA_VALUE_2G);
  3088. if (!comp_type)
  3089. comp_value = -comp_value;
  3090. }
  3091. } else {
  3092. comp_en = rt2x00_get_field16(eeprom,
  3093. EEPROM_TXPOWER_DELTA_ENABLE_5G);
  3094. if (comp_en) {
  3095. comp_type = rt2x00_get_field16(eeprom,
  3096. EEPROM_TXPOWER_DELTA_TYPE_5G);
  3097. comp_value = rt2x00_get_field16(eeprom,
  3098. EEPROM_TXPOWER_DELTA_VALUE_5G);
  3099. if (!comp_type)
  3100. comp_value = -comp_value;
  3101. }
  3102. }
  3103. return comp_value;
  3104. }
  3105. static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
  3106. int power_level, int max_power)
  3107. {
  3108. int delta;
  3109. if (rt2x00_has_cap_power_limit(rt2x00dev))
  3110. return 0;
  3111. /*
  3112. * XXX: We don't know the maximum transmit power of our hardware since
  3113. * the EEPROM doesn't expose it. We only know that we are calibrated
  3114. * to 100% tx power.
  3115. *
  3116. * Hence, we assume the regulatory limit that cfg80211 calulated for
  3117. * the current channel is our maximum and if we are requested to lower
  3118. * the value we just reduce our tx power accordingly.
  3119. */
  3120. delta = power_level - max_power;
  3121. return min(delta, 0);
  3122. }
  3123. static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
  3124. enum ieee80211_band band, int power_level,
  3125. u8 txpower, int delta)
  3126. {
  3127. u16 eeprom;
  3128. u8 criterion;
  3129. u8 eirp_txpower;
  3130. u8 eirp_txpower_criterion;
  3131. u8 reg_limit;
  3132. if (rt2x00_rt(rt2x00dev, RT3593))
  3133. return min_t(u8, txpower, 0xc);
  3134. if (rt2x00_has_cap_power_limit(rt2x00dev)) {
  3135. /*
  3136. * Check if eirp txpower exceed txpower_limit.
  3137. * We use OFDM 6M as criterion and its eirp txpower
  3138. * is stored at EEPROM_EIRP_MAX_TX_POWER.
  3139. * .11b data rate need add additional 4dbm
  3140. * when calculating eirp txpower.
  3141. */
  3142. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3143. 1, &eeprom);
  3144. criterion = rt2x00_get_field16(eeprom,
  3145. EEPROM_TXPOWER_BYRATE_RATE0);
  3146. rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER,
  3147. &eeprom);
  3148. if (band == IEEE80211_BAND_2GHZ)
  3149. eirp_txpower_criterion = rt2x00_get_field16(eeprom,
  3150. EEPROM_EIRP_MAX_TX_POWER_2GHZ);
  3151. else
  3152. eirp_txpower_criterion = rt2x00_get_field16(eeprom,
  3153. EEPROM_EIRP_MAX_TX_POWER_5GHZ);
  3154. eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
  3155. (is_rate_b ? 4 : 0) + delta;
  3156. reg_limit = (eirp_txpower > power_level) ?
  3157. (eirp_txpower - power_level) : 0;
  3158. } else
  3159. reg_limit = 0;
  3160. txpower = max(0, txpower + delta - reg_limit);
  3161. return min_t(u8, txpower, 0xc);
  3162. }
  3163. enum {
  3164. TX_PWR_CFG_0_IDX,
  3165. TX_PWR_CFG_1_IDX,
  3166. TX_PWR_CFG_2_IDX,
  3167. TX_PWR_CFG_3_IDX,
  3168. TX_PWR_CFG_4_IDX,
  3169. TX_PWR_CFG_5_IDX,
  3170. TX_PWR_CFG_6_IDX,
  3171. TX_PWR_CFG_7_IDX,
  3172. TX_PWR_CFG_8_IDX,
  3173. TX_PWR_CFG_9_IDX,
  3174. TX_PWR_CFG_0_EXT_IDX,
  3175. TX_PWR_CFG_1_EXT_IDX,
  3176. TX_PWR_CFG_2_EXT_IDX,
  3177. TX_PWR_CFG_3_EXT_IDX,
  3178. TX_PWR_CFG_4_EXT_IDX,
  3179. TX_PWR_CFG_IDX_COUNT,
  3180. };
  3181. static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
  3182. struct ieee80211_channel *chan,
  3183. int power_level)
  3184. {
  3185. u8 txpower;
  3186. u16 eeprom;
  3187. u32 regs[TX_PWR_CFG_IDX_COUNT];
  3188. unsigned int offset;
  3189. enum ieee80211_band band = chan->band;
  3190. int delta;
  3191. int i;
  3192. memset(regs, '\0', sizeof(regs));
  3193. /* TODO: adapt TX power reduction from the rt28xx code */
  3194. /* calculate temperature compensation delta */
  3195. delta = rt2800_get_gain_calibration_delta(rt2x00dev);
  3196. if (band == IEEE80211_BAND_5GHZ)
  3197. offset = 16;
  3198. else
  3199. offset = 0;
  3200. if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
  3201. offset += 8;
  3202. /* read the next four txpower values */
  3203. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3204. offset, &eeprom);
  3205. /* CCK 1MBS,2MBS */
  3206. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3207. txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
  3208. txpower, delta);
  3209. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3210. TX_PWR_CFG_0_CCK1_CH0, txpower);
  3211. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3212. TX_PWR_CFG_0_CCK1_CH1, txpower);
  3213. rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
  3214. TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
  3215. /* CCK 5.5MBS,11MBS */
  3216. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3217. txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
  3218. txpower, delta);
  3219. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3220. TX_PWR_CFG_0_CCK5_CH0, txpower);
  3221. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3222. TX_PWR_CFG_0_CCK5_CH1, txpower);
  3223. rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
  3224. TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
  3225. /* OFDM 6MBS,9MBS */
  3226. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3227. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3228. txpower, delta);
  3229. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3230. TX_PWR_CFG_0_OFDM6_CH0, txpower);
  3231. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3232. TX_PWR_CFG_0_OFDM6_CH1, txpower);
  3233. rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
  3234. TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
  3235. /* OFDM 12MBS,18MBS */
  3236. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
  3237. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3238. txpower, delta);
  3239. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3240. TX_PWR_CFG_0_OFDM12_CH0, txpower);
  3241. rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
  3242. TX_PWR_CFG_0_OFDM12_CH1, txpower);
  3243. rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
  3244. TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
  3245. /* read the next four txpower values */
  3246. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3247. offset + 1, &eeprom);
  3248. /* OFDM 24MBS,36MBS */
  3249. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3250. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3251. txpower, delta);
  3252. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3253. TX_PWR_CFG_1_OFDM24_CH0, txpower);
  3254. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3255. TX_PWR_CFG_1_OFDM24_CH1, txpower);
  3256. rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
  3257. TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
  3258. /* OFDM 48MBS */
  3259. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3260. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3261. txpower, delta);
  3262. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3263. TX_PWR_CFG_1_OFDM48_CH0, txpower);
  3264. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3265. TX_PWR_CFG_1_OFDM48_CH1, txpower);
  3266. rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
  3267. TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
  3268. /* OFDM 54MBS */
  3269. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3270. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3271. txpower, delta);
  3272. rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
  3273. TX_PWR_CFG_7_OFDM54_CH0, txpower);
  3274. rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
  3275. TX_PWR_CFG_7_OFDM54_CH1, txpower);
  3276. rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
  3277. TX_PWR_CFG_7_OFDM54_CH2, txpower);
  3278. /* read the next four txpower values */
  3279. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3280. offset + 2, &eeprom);
  3281. /* MCS 0,1 */
  3282. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3283. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3284. txpower, delta);
  3285. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3286. TX_PWR_CFG_1_MCS0_CH0, txpower);
  3287. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3288. TX_PWR_CFG_1_MCS0_CH1, txpower);
  3289. rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
  3290. TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
  3291. /* MCS 2,3 */
  3292. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3293. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3294. txpower, delta);
  3295. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3296. TX_PWR_CFG_1_MCS2_CH0, txpower);
  3297. rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
  3298. TX_PWR_CFG_1_MCS2_CH1, txpower);
  3299. rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
  3300. TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
  3301. /* MCS 4,5 */
  3302. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3303. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3304. txpower, delta);
  3305. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3306. TX_PWR_CFG_2_MCS4_CH0, txpower);
  3307. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3308. TX_PWR_CFG_2_MCS4_CH1, txpower);
  3309. rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
  3310. TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
  3311. /* MCS 6 */
  3312. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
  3313. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3314. txpower, delta);
  3315. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3316. TX_PWR_CFG_2_MCS6_CH0, txpower);
  3317. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3318. TX_PWR_CFG_2_MCS6_CH1, txpower);
  3319. rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
  3320. TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
  3321. /* read the next four txpower values */
  3322. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3323. offset + 3, &eeprom);
  3324. /* MCS 7 */
  3325. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3326. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3327. txpower, delta);
  3328. rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
  3329. TX_PWR_CFG_7_MCS7_CH0, txpower);
  3330. rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
  3331. TX_PWR_CFG_7_MCS7_CH1, txpower);
  3332. rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
  3333. TX_PWR_CFG_7_MCS7_CH2, txpower);
  3334. /* MCS 8,9 */
  3335. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3336. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3337. txpower, delta);
  3338. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3339. TX_PWR_CFG_2_MCS8_CH0, txpower);
  3340. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3341. TX_PWR_CFG_2_MCS8_CH1, txpower);
  3342. rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
  3343. TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
  3344. /* MCS 10,11 */
  3345. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3346. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3347. txpower, delta);
  3348. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3349. TX_PWR_CFG_2_MCS10_CH0, txpower);
  3350. rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
  3351. TX_PWR_CFG_2_MCS10_CH1, txpower);
  3352. rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
  3353. TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
  3354. /* MCS 12,13 */
  3355. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
  3356. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3357. txpower, delta);
  3358. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3359. TX_PWR_CFG_3_MCS12_CH0, txpower);
  3360. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3361. TX_PWR_CFG_3_MCS12_CH1, txpower);
  3362. rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
  3363. TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
  3364. /* read the next four txpower values */
  3365. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3366. offset + 4, &eeprom);
  3367. /* MCS 14 */
  3368. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3369. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3370. txpower, delta);
  3371. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3372. TX_PWR_CFG_3_MCS14_CH0, txpower);
  3373. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3374. TX_PWR_CFG_3_MCS14_CH1, txpower);
  3375. rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
  3376. TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
  3377. /* MCS 15 */
  3378. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3379. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3380. txpower, delta);
  3381. rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
  3382. TX_PWR_CFG_8_MCS15_CH0, txpower);
  3383. rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
  3384. TX_PWR_CFG_8_MCS15_CH1, txpower);
  3385. rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
  3386. TX_PWR_CFG_8_MCS15_CH2, txpower);
  3387. /* MCS 16,17 */
  3388. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3389. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3390. txpower, delta);
  3391. rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
  3392. TX_PWR_CFG_5_MCS16_CH0, txpower);
  3393. rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
  3394. TX_PWR_CFG_5_MCS16_CH1, txpower);
  3395. rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
  3396. TX_PWR_CFG_5_MCS16_CH2, txpower);
  3397. /* MCS 18,19 */
  3398. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
  3399. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3400. txpower, delta);
  3401. rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
  3402. TX_PWR_CFG_5_MCS18_CH0, txpower);
  3403. rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
  3404. TX_PWR_CFG_5_MCS18_CH1, txpower);
  3405. rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
  3406. TX_PWR_CFG_5_MCS18_CH2, txpower);
  3407. /* read the next four txpower values */
  3408. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3409. offset + 5, &eeprom);
  3410. /* MCS 20,21 */
  3411. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3412. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3413. txpower, delta);
  3414. rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
  3415. TX_PWR_CFG_6_MCS20_CH0, txpower);
  3416. rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
  3417. TX_PWR_CFG_6_MCS20_CH1, txpower);
  3418. rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
  3419. TX_PWR_CFG_6_MCS20_CH2, txpower);
  3420. /* MCS 22 */
  3421. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3422. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3423. txpower, delta);
  3424. rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
  3425. TX_PWR_CFG_6_MCS22_CH0, txpower);
  3426. rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
  3427. TX_PWR_CFG_6_MCS22_CH1, txpower);
  3428. rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
  3429. TX_PWR_CFG_6_MCS22_CH2, txpower);
  3430. /* MCS 23 */
  3431. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3432. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3433. txpower, delta);
  3434. rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
  3435. TX_PWR_CFG_8_MCS23_CH0, txpower);
  3436. rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
  3437. TX_PWR_CFG_8_MCS23_CH1, txpower);
  3438. rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
  3439. TX_PWR_CFG_8_MCS23_CH2, txpower);
  3440. /* read the next four txpower values */
  3441. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3442. offset + 6, &eeprom);
  3443. /* STBC, MCS 0,1 */
  3444. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3445. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3446. txpower, delta);
  3447. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3448. TX_PWR_CFG_3_STBC0_CH0, txpower);
  3449. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3450. TX_PWR_CFG_3_STBC0_CH1, txpower);
  3451. rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
  3452. TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
  3453. /* STBC, MCS 2,3 */
  3454. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
  3455. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3456. txpower, delta);
  3457. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3458. TX_PWR_CFG_3_STBC2_CH0, txpower);
  3459. rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
  3460. TX_PWR_CFG_3_STBC2_CH1, txpower);
  3461. rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
  3462. TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
  3463. /* STBC, MCS 4,5 */
  3464. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
  3465. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3466. txpower, delta);
  3467. rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
  3468. rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
  3469. rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
  3470. txpower);
  3471. /* STBC, MCS 6 */
  3472. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
  3473. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3474. txpower, delta);
  3475. rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
  3476. rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
  3477. rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
  3478. txpower);
  3479. /* read the next four txpower values */
  3480. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3481. offset + 7, &eeprom);
  3482. /* STBC, MCS 7 */
  3483. txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
  3484. txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
  3485. txpower, delta);
  3486. rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
  3487. TX_PWR_CFG_9_STBC7_CH0, txpower);
  3488. rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
  3489. TX_PWR_CFG_9_STBC7_CH1, txpower);
  3490. rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
  3491. TX_PWR_CFG_9_STBC7_CH2, txpower);
  3492. rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
  3493. rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
  3494. rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
  3495. rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
  3496. rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
  3497. rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
  3498. rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
  3499. rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
  3500. rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
  3501. rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
  3502. rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
  3503. regs[TX_PWR_CFG_0_EXT_IDX]);
  3504. rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
  3505. regs[TX_PWR_CFG_1_EXT_IDX]);
  3506. rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
  3507. regs[TX_PWR_CFG_2_EXT_IDX]);
  3508. rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
  3509. regs[TX_PWR_CFG_3_EXT_IDX]);
  3510. rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
  3511. regs[TX_PWR_CFG_4_EXT_IDX]);
  3512. for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
  3513. rt2x00_dbg(rt2x00dev,
  3514. "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
  3515. (band == IEEE80211_BAND_5GHZ) ? '5' : '2',
  3516. (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
  3517. '4' : '2',
  3518. (i > TX_PWR_CFG_9_IDX) ?
  3519. (i - TX_PWR_CFG_9_IDX - 1) : i,
  3520. (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
  3521. (unsigned long) regs[i]);
  3522. }
  3523. /*
  3524. * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
  3525. * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
  3526. * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
  3527. * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
  3528. * Reference per rate transmit power values are located in the EEPROM at
  3529. * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
  3530. * current conditions (i.e. band, bandwidth, temperature, user settings).
  3531. */
  3532. static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
  3533. struct ieee80211_channel *chan,
  3534. int power_level)
  3535. {
  3536. u8 txpower, r1;
  3537. u16 eeprom;
  3538. u32 reg, offset;
  3539. int i, is_rate_b, delta, power_ctrl;
  3540. enum ieee80211_band band = chan->band;
  3541. /*
  3542. * Calculate HT40 compensation. For 40MHz we need to add or subtract
  3543. * value read from EEPROM (different for 2GHz and for 5GHz).
  3544. */
  3545. delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
  3546. /*
  3547. * Calculate temperature compensation. Depends on measurement of current
  3548. * TSSI (Transmitter Signal Strength Indication) we know TX power (due
  3549. * to temperature or maybe other factors) is smaller or bigger than
  3550. * expected. We adjust it, based on TSSI reference and boundaries values
  3551. * provided in EEPROM.
  3552. */
  3553. switch (rt2x00dev->chip.rt) {
  3554. case RT2860:
  3555. case RT2872:
  3556. case RT2883:
  3557. case RT3070:
  3558. case RT3071:
  3559. case RT3090:
  3560. case RT3572:
  3561. delta += rt2800_get_gain_calibration_delta(rt2x00dev);
  3562. break;
  3563. default:
  3564. /* TODO: temperature compensation code for other chips. */
  3565. break;
  3566. }
  3567. /*
  3568. * Decrease power according to user settings, on devices with unknown
  3569. * maximum tx power. For other devices we take user power_level into
  3570. * consideration on rt2800_compensate_txpower().
  3571. */
  3572. delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
  3573. chan->max_power);
  3574. /*
  3575. * BBP_R1 controls TX power for all rates, it allow to set the following
  3576. * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
  3577. *
  3578. * TODO: we do not use +6 dBm option to do not increase power beyond
  3579. * regulatory limit, however this could be utilized for devices with
  3580. * CAPABILITY_POWER_LIMIT.
  3581. */
  3582. if (delta <= -12) {
  3583. power_ctrl = 2;
  3584. delta += 12;
  3585. } else if (delta <= -6) {
  3586. power_ctrl = 1;
  3587. delta += 6;
  3588. } else {
  3589. power_ctrl = 0;
  3590. }
  3591. rt2800_bbp_read(rt2x00dev, 1, &r1);
  3592. rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
  3593. rt2800_bbp_write(rt2x00dev, 1, r1);
  3594. offset = TX_PWR_CFG_0;
  3595. for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
  3596. /* just to be safe */
  3597. if (offset > TX_PWR_CFG_4)
  3598. break;
  3599. rt2800_register_read(rt2x00dev, offset, &reg);
  3600. /* read the next four txpower values */
  3601. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3602. i, &eeprom);
  3603. is_rate_b = i ? 0 : 1;
  3604. /*
  3605. * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
  3606. * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
  3607. * TX_PWR_CFG_4: unknown
  3608. */
  3609. txpower = rt2x00_get_field16(eeprom,
  3610. EEPROM_TXPOWER_BYRATE_RATE0);
  3611. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3612. power_level, txpower, delta);
  3613. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
  3614. /*
  3615. * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
  3616. * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
  3617. * TX_PWR_CFG_4: unknown
  3618. */
  3619. txpower = rt2x00_get_field16(eeprom,
  3620. EEPROM_TXPOWER_BYRATE_RATE1);
  3621. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3622. power_level, txpower, delta);
  3623. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
  3624. /*
  3625. * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
  3626. * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
  3627. * TX_PWR_CFG_4: unknown
  3628. */
  3629. txpower = rt2x00_get_field16(eeprom,
  3630. EEPROM_TXPOWER_BYRATE_RATE2);
  3631. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3632. power_level, txpower, delta);
  3633. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
  3634. /*
  3635. * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
  3636. * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
  3637. * TX_PWR_CFG_4: unknown
  3638. */
  3639. txpower = rt2x00_get_field16(eeprom,
  3640. EEPROM_TXPOWER_BYRATE_RATE3);
  3641. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3642. power_level, txpower, delta);
  3643. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
  3644. /* read the next four txpower values */
  3645. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
  3646. i + 1, &eeprom);
  3647. is_rate_b = 0;
  3648. /*
  3649. * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
  3650. * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
  3651. * TX_PWR_CFG_4: unknown
  3652. */
  3653. txpower = rt2x00_get_field16(eeprom,
  3654. EEPROM_TXPOWER_BYRATE_RATE0);
  3655. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3656. power_level, txpower, delta);
  3657. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
  3658. /*
  3659. * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
  3660. * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
  3661. * TX_PWR_CFG_4: unknown
  3662. */
  3663. txpower = rt2x00_get_field16(eeprom,
  3664. EEPROM_TXPOWER_BYRATE_RATE1);
  3665. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3666. power_level, txpower, delta);
  3667. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
  3668. /*
  3669. * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
  3670. * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
  3671. * TX_PWR_CFG_4: unknown
  3672. */
  3673. txpower = rt2x00_get_field16(eeprom,
  3674. EEPROM_TXPOWER_BYRATE_RATE2);
  3675. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3676. power_level, txpower, delta);
  3677. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
  3678. /*
  3679. * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
  3680. * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
  3681. * TX_PWR_CFG_4: unknown
  3682. */
  3683. txpower = rt2x00_get_field16(eeprom,
  3684. EEPROM_TXPOWER_BYRATE_RATE3);
  3685. txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
  3686. power_level, txpower, delta);
  3687. rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
  3688. rt2800_register_write(rt2x00dev, offset, reg);
  3689. /* next TX_PWR_CFG register */
  3690. offset += 4;
  3691. }
  3692. }
  3693. static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
  3694. struct ieee80211_channel *chan,
  3695. int power_level)
  3696. {
  3697. if (rt2x00_rt(rt2x00dev, RT3593))
  3698. rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
  3699. else
  3700. rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
  3701. }
  3702. void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
  3703. {
  3704. rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
  3705. rt2x00dev->tx_power);
  3706. }
  3707. EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
  3708. void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
  3709. {
  3710. u32 tx_pin;
  3711. u8 rfcsr;
  3712. /*
  3713. * A voltage-controlled oscillator(VCO) is an electronic oscillator
  3714. * designed to be controlled in oscillation frequency by a voltage
  3715. * input. Maybe the temperature will affect the frequency of
  3716. * oscillation to be shifted. The VCO calibration will be called
  3717. * periodically to adjust the frequency to be precision.
  3718. */
  3719. rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
  3720. tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
  3721. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  3722. switch (rt2x00dev->chip.rf) {
  3723. case RF2020:
  3724. case RF3020:
  3725. case RF3021:
  3726. case RF3022:
  3727. case RF3320:
  3728. case RF3052:
  3729. rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
  3730. rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
  3731. rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
  3732. break;
  3733. case RF3053:
  3734. case RF3070:
  3735. case RF3290:
  3736. case RF5360:
  3737. case RF5362:
  3738. case RF5370:
  3739. case RF5372:
  3740. case RF5390:
  3741. case RF5392:
  3742. rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
  3743. rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
  3744. rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
  3745. break;
  3746. default:
  3747. return;
  3748. }
  3749. mdelay(1);
  3750. rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
  3751. if (rt2x00dev->rf_channel <= 14) {
  3752. switch (rt2x00dev->default_ant.tx_chain_num) {
  3753. case 3:
  3754. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
  3755. /* fall through */
  3756. case 2:
  3757. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
  3758. /* fall through */
  3759. case 1:
  3760. default:
  3761. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
  3762. break;
  3763. }
  3764. } else {
  3765. switch (rt2x00dev->default_ant.tx_chain_num) {
  3766. case 3:
  3767. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
  3768. /* fall through */
  3769. case 2:
  3770. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
  3771. /* fall through */
  3772. case 1:
  3773. default:
  3774. rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
  3775. break;
  3776. }
  3777. }
  3778. rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
  3779. }
  3780. EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
  3781. static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
  3782. struct rt2x00lib_conf *libconf)
  3783. {
  3784. u32 reg;
  3785. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  3786. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
  3787. libconf->conf->short_frame_max_tx_count);
  3788. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
  3789. libconf->conf->long_frame_max_tx_count);
  3790. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  3791. }
  3792. static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
  3793. struct rt2x00lib_conf *libconf)
  3794. {
  3795. enum dev_state state =
  3796. (libconf->conf->flags & IEEE80211_CONF_PS) ?
  3797. STATE_SLEEP : STATE_AWAKE;
  3798. u32 reg;
  3799. if (state == STATE_SLEEP) {
  3800. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
  3801. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  3802. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
  3803. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
  3804. libconf->conf->listen_interval - 1);
  3805. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
  3806. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  3807. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  3808. } else {
  3809. rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
  3810. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
  3811. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
  3812. rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
  3813. rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
  3814. rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
  3815. }
  3816. }
  3817. void rt2800_config(struct rt2x00_dev *rt2x00dev,
  3818. struct rt2x00lib_conf *libconf,
  3819. const unsigned int flags)
  3820. {
  3821. /* Always recalculate LNA gain before changing configuration */
  3822. rt2800_config_lna_gain(rt2x00dev, libconf);
  3823. if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
  3824. rt2800_config_channel(rt2x00dev, libconf->conf,
  3825. &libconf->rf, &libconf->channel);
  3826. rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
  3827. libconf->conf->power_level);
  3828. }
  3829. if (flags & IEEE80211_CONF_CHANGE_POWER)
  3830. rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
  3831. libconf->conf->power_level);
  3832. if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
  3833. rt2800_config_retry_limit(rt2x00dev, libconf);
  3834. if (flags & IEEE80211_CONF_CHANGE_PS)
  3835. rt2800_config_ps(rt2x00dev, libconf);
  3836. }
  3837. EXPORT_SYMBOL_GPL(rt2800_config);
  3838. /*
  3839. * Link tuning
  3840. */
  3841. void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  3842. {
  3843. u32 reg;
  3844. /*
  3845. * Update FCS error count from register.
  3846. */
  3847. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  3848. qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
  3849. }
  3850. EXPORT_SYMBOL_GPL(rt2800_link_stats);
  3851. static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
  3852. {
  3853. u8 vgc;
  3854. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
  3855. if (rt2x00_rt(rt2x00dev, RT3070) ||
  3856. rt2x00_rt(rt2x00dev, RT3071) ||
  3857. rt2x00_rt(rt2x00dev, RT3090) ||
  3858. rt2x00_rt(rt2x00dev, RT3290) ||
  3859. rt2x00_rt(rt2x00dev, RT3390) ||
  3860. rt2x00_rt(rt2x00dev, RT3572) ||
  3861. rt2x00_rt(rt2x00dev, RT3593) ||
  3862. rt2x00_rt(rt2x00dev, RT5390) ||
  3863. rt2x00_rt(rt2x00dev, RT5392) ||
  3864. rt2x00_rt(rt2x00dev, RT5592))
  3865. vgc = 0x1c + (2 * rt2x00dev->lna_gain);
  3866. else
  3867. vgc = 0x2e + rt2x00dev->lna_gain;
  3868. } else { /* 5GHZ band */
  3869. if (rt2x00_rt(rt2x00dev, RT3593))
  3870. vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
  3871. else if (rt2x00_rt(rt2x00dev, RT5592))
  3872. vgc = 0x24 + (2 * rt2x00dev->lna_gain);
  3873. else {
  3874. if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
  3875. vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
  3876. else
  3877. vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
  3878. }
  3879. }
  3880. return vgc;
  3881. }
  3882. static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
  3883. struct link_qual *qual, u8 vgc_level)
  3884. {
  3885. if (qual->vgc_level != vgc_level) {
  3886. if (rt2x00_rt(rt2x00dev, RT3572) ||
  3887. rt2x00_rt(rt2x00dev, RT3593)) {
  3888. rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
  3889. vgc_level);
  3890. } else if (rt2x00_rt(rt2x00dev, RT5592)) {
  3891. rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
  3892. rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
  3893. } else {
  3894. rt2800_bbp_write(rt2x00dev, 66, vgc_level);
  3895. }
  3896. qual->vgc_level = vgc_level;
  3897. qual->vgc_level_reg = vgc_level;
  3898. }
  3899. }
  3900. void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
  3901. {
  3902. rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
  3903. }
  3904. EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
  3905. void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
  3906. const u32 count)
  3907. {
  3908. u8 vgc;
  3909. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
  3910. return;
  3911. /* When RSSI is better than a certain threshold, increase VGC
  3912. * with a chip specific value in order to improve the balance
  3913. * between sensibility and noise isolation.
  3914. */
  3915. vgc = rt2800_get_default_vgc(rt2x00dev);
  3916. switch (rt2x00dev->chip.rt) {
  3917. case RT3572:
  3918. case RT3593:
  3919. if (qual->rssi > -65) {
  3920. if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
  3921. vgc += 0x20;
  3922. else
  3923. vgc += 0x10;
  3924. }
  3925. break;
  3926. case RT5592:
  3927. if (qual->rssi > -65)
  3928. vgc += 0x20;
  3929. break;
  3930. default:
  3931. if (qual->rssi > -80)
  3932. vgc += 0x10;
  3933. break;
  3934. }
  3935. rt2800_set_vgc(rt2x00dev, qual, vgc);
  3936. }
  3937. EXPORT_SYMBOL_GPL(rt2800_link_tuner);
  3938. /*
  3939. * Initialization functions.
  3940. */
  3941. static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
  3942. {
  3943. u32 reg;
  3944. u16 eeprom;
  3945. unsigned int i;
  3946. int ret;
  3947. rt2800_disable_wpdma(rt2x00dev);
  3948. ret = rt2800_drv_init_registers(rt2x00dev);
  3949. if (ret)
  3950. return ret;
  3951. rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
  3952. rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
  3953. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
  3954. rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
  3955. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
  3956. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
  3957. rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
  3958. rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
  3959. rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
  3960. rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
  3961. rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
  3962. rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
  3963. rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
  3964. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
  3965. rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
  3966. rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
  3967. if (rt2x00_rt(rt2x00dev, RT3290)) {
  3968. rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, &reg);
  3969. if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
  3970. rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
  3971. rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
  3972. }
  3973. rt2800_register_read(rt2x00dev, CMB_CTRL, &reg);
  3974. if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
  3975. rt2x00_set_field32(&reg, LDO0_EN, 1);
  3976. rt2x00_set_field32(&reg, LDO_BGSEL, 3);
  3977. rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
  3978. }
  3979. rt2800_register_read(rt2x00dev, OSC_CTRL, &reg);
  3980. rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
  3981. rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
  3982. rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
  3983. rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
  3984. rt2800_register_read(rt2x00dev, COEX_CFG0, &reg);
  3985. rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
  3986. rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
  3987. rt2800_register_read(rt2x00dev, COEX_CFG2, &reg);
  3988. rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
  3989. rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
  3990. rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
  3991. rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
  3992. rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
  3993. rt2800_register_read(rt2x00dev, PLL_CTRL, &reg);
  3994. rt2x00_set_field32(&reg, PLL_CONTROL, 1);
  3995. rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
  3996. }
  3997. if (rt2x00_rt(rt2x00dev, RT3071) ||
  3998. rt2x00_rt(rt2x00dev, RT3090) ||
  3999. rt2x00_rt(rt2x00dev, RT3290) ||
  4000. rt2x00_rt(rt2x00dev, RT3390)) {
  4001. if (rt2x00_rt(rt2x00dev, RT3290))
  4002. rt2800_register_write(rt2x00dev, TX_SW_CFG0,
  4003. 0x00000404);
  4004. else
  4005. rt2800_register_write(rt2x00dev, TX_SW_CFG0,
  4006. 0x00000400);
  4007. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  4008. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  4009. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  4010. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
  4011. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
  4012. &eeprom);
  4013. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
  4014. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  4015. 0x0000002c);
  4016. else
  4017. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  4018. 0x0000000f);
  4019. } else {
  4020. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  4021. }
  4022. } else if (rt2x00_rt(rt2x00dev, RT3070)) {
  4023. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  4024. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
  4025. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  4026. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
  4027. } else {
  4028. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  4029. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  4030. }
  4031. } else if (rt2800_is_305x_soc(rt2x00dev)) {
  4032. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  4033. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  4034. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
  4035. } else if (rt2x00_rt(rt2x00dev, RT3352)) {
  4036. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
  4037. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  4038. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  4039. } else if (rt2x00_rt(rt2x00dev, RT3572)) {
  4040. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
  4041. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  4042. } else if (rt2x00_rt(rt2x00dev, RT3593)) {
  4043. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
  4044. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
  4045. if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
  4046. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
  4047. &eeprom);
  4048. if (rt2x00_get_field16(eeprom,
  4049. EEPROM_NIC_CONF1_DAC_TEST))
  4050. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  4051. 0x0000001f);
  4052. else
  4053. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  4054. 0x0000000f);
  4055. } else {
  4056. rt2800_register_write(rt2x00dev, TX_SW_CFG2,
  4057. 0x00000000);
  4058. }
  4059. } else if (rt2x00_rt(rt2x00dev, RT5390) ||
  4060. rt2x00_rt(rt2x00dev, RT5392) ||
  4061. rt2x00_rt(rt2x00dev, RT5592)) {
  4062. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
  4063. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  4064. rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
  4065. } else {
  4066. rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
  4067. rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
  4068. }
  4069. rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
  4070. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
  4071. rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
  4072. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
  4073. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
  4074. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
  4075. rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
  4076. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
  4077. rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
  4078. rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
  4079. rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
  4080. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
  4081. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
  4082. rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
  4083. rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
  4084. rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
  4085. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
  4086. if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
  4087. rt2x00_rt(rt2x00dev, RT2883) ||
  4088. rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
  4089. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
  4090. else
  4091. rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
  4092. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
  4093. rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
  4094. rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
  4095. rt2800_register_read(rt2x00dev, LED_CFG, &reg);
  4096. rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
  4097. rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
  4098. rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
  4099. rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
  4100. rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
  4101. rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
  4102. rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
  4103. rt2800_register_write(rt2x00dev, LED_CFG, reg);
  4104. rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
  4105. rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
  4106. rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
  4107. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
  4108. rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
  4109. rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
  4110. rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
  4111. rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
  4112. rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
  4113. rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
  4114. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
  4115. rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
  4116. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
  4117. rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
  4118. rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
  4119. rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
  4120. rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
  4121. rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
  4122. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  4123. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
  4124. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
  4125. rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
  4126. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  4127. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  4128. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  4129. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  4130. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  4131. rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  4132. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
  4133. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  4134. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  4135. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
  4136. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
  4137. rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
  4138. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  4139. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  4140. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  4141. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  4142. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  4143. rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  4144. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
  4145. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  4146. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  4147. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
  4148. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
  4149. rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
  4150. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  4151. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  4152. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  4153. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  4154. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  4155. rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  4156. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
  4157. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  4158. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  4159. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
  4160. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
  4161. rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
  4162. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  4163. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  4164. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  4165. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  4166. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  4167. rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  4168. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
  4169. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  4170. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  4171. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
  4172. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
  4173. rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
  4174. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  4175. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  4176. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  4177. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
  4178. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  4179. rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
  4180. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
  4181. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  4182. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  4183. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
  4184. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
  4185. rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
  4186. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
  4187. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
  4188. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
  4189. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
  4190. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
  4191. rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
  4192. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
  4193. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  4194. if (rt2x00_is_usb(rt2x00dev)) {
  4195. rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
  4196. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  4197. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
  4198. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
  4199. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
  4200. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
  4201. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
  4202. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
  4203. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
  4204. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
  4205. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
  4206. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  4207. }
  4208. /*
  4209. * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
  4210. * although it is reserved.
  4211. */
  4212. rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, &reg);
  4213. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
  4214. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
  4215. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
  4216. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
  4217. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
  4218. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
  4219. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
  4220. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
  4221. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
  4222. rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
  4223. rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
  4224. reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
  4225. rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
  4226. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  4227. rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
  4228. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
  4229. IEEE80211_MAX_RTS_THRESHOLD);
  4230. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
  4231. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  4232. rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
  4233. /*
  4234. * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
  4235. * time should be set to 16. However, the original Ralink driver uses
  4236. * 16 for both and indeed using a value of 10 for CCK SIFS results in
  4237. * connection problems with 11g + CTS protection. Hence, use the same
  4238. * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
  4239. */
  4240. rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
  4241. rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
  4242. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
  4243. rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
  4244. rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
  4245. rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
  4246. rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
  4247. rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
  4248. /*
  4249. * ASIC will keep garbage value after boot, clear encryption keys.
  4250. */
  4251. for (i = 0; i < 4; i++)
  4252. rt2800_register_write(rt2x00dev,
  4253. SHARED_KEY_MODE_ENTRY(i), 0);
  4254. for (i = 0; i < 256; i++) {
  4255. rt2800_config_wcid(rt2x00dev, NULL, i);
  4256. rt2800_delete_wcid_attr(rt2x00dev, i);
  4257. rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
  4258. }
  4259. /*
  4260. * Clear all beacons
  4261. */
  4262. for (i = 0; i < 8; i++)
  4263. rt2800_clear_beacon_register(rt2x00dev, i);
  4264. if (rt2x00_is_usb(rt2x00dev)) {
  4265. rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
  4266. rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
  4267. rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
  4268. } else if (rt2x00_is_pcie(rt2x00dev)) {
  4269. rt2800_register_read(rt2x00dev, US_CYC_CNT, &reg);
  4270. rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
  4271. rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
  4272. }
  4273. rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
  4274. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
  4275. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
  4276. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
  4277. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
  4278. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
  4279. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
  4280. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
  4281. rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
  4282. rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
  4283. rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
  4284. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
  4285. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
  4286. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
  4287. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
  4288. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
  4289. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
  4290. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
  4291. rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
  4292. rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
  4293. rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
  4294. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
  4295. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
  4296. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
  4297. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
  4298. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
  4299. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
  4300. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
  4301. rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
  4302. rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
  4303. rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
  4304. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
  4305. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
  4306. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
  4307. rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
  4308. rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
  4309. /*
  4310. * Do not force the BA window size, we use the TXWI to set it
  4311. */
  4312. rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, &reg);
  4313. rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
  4314. rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
  4315. rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
  4316. /*
  4317. * We must clear the error counters.
  4318. * These registers are cleared on read,
  4319. * so we may pass a useless variable to store the value.
  4320. */
  4321. rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
  4322. rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
  4323. rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
  4324. rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
  4325. rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
  4326. rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
  4327. /*
  4328. * Setup leadtime for pre tbtt interrupt to 6ms
  4329. */
  4330. rt2800_register_read(rt2x00dev, INT_TIMER_CFG, &reg);
  4331. rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
  4332. rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
  4333. /*
  4334. * Set up channel statistics timer
  4335. */
  4336. rt2800_register_read(rt2x00dev, CH_TIME_CFG, &reg);
  4337. rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
  4338. rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
  4339. rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
  4340. rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
  4341. rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
  4342. rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
  4343. return 0;
  4344. }
  4345. static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
  4346. {
  4347. unsigned int i;
  4348. u32 reg;
  4349. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  4350. rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
  4351. if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
  4352. return 0;
  4353. udelay(REGISTER_BUSY_DELAY);
  4354. }
  4355. rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
  4356. return -EACCES;
  4357. }
  4358. static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
  4359. {
  4360. unsigned int i;
  4361. u8 value;
  4362. /*
  4363. * BBP was enabled after firmware was loaded,
  4364. * but we need to reactivate it now.
  4365. */
  4366. rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  4367. rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  4368. msleep(1);
  4369. for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  4370. rt2800_bbp_read(rt2x00dev, 0, &value);
  4371. if ((value != 0xff) && (value != 0x00))
  4372. return 0;
  4373. udelay(REGISTER_BUSY_DELAY);
  4374. }
  4375. rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
  4376. return -EACCES;
  4377. }
  4378. static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
  4379. {
  4380. u8 value;
  4381. rt2800_bbp_read(rt2x00dev, 4, &value);
  4382. rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
  4383. rt2800_bbp_write(rt2x00dev, 4, value);
  4384. }
  4385. static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
  4386. {
  4387. rt2800_bbp_write(rt2x00dev, 142, 1);
  4388. rt2800_bbp_write(rt2x00dev, 143, 57);
  4389. }
  4390. static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
  4391. {
  4392. const u8 glrt_table[] = {
  4393. 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
  4394. 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
  4395. 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
  4396. 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
  4397. 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
  4398. 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
  4399. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
  4400. 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
  4401. 0x2E, 0x36, 0x30, 0x6E, /* 208 ~ 211 */
  4402. };
  4403. int i;
  4404. for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
  4405. rt2800_bbp_write(rt2x00dev, 195, 128 + i);
  4406. rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
  4407. }
  4408. };
  4409. static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
  4410. {
  4411. rt2800_bbp_write(rt2x00dev, 65, 0x2C);
  4412. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4413. rt2800_bbp_write(rt2x00dev, 68, 0x0B);
  4414. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4415. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4416. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  4417. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  4418. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4419. rt2800_bbp_write(rt2x00dev, 83, 0x6A);
  4420. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4421. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  4422. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4423. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  4424. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  4425. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  4426. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4427. }
  4428. static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
  4429. {
  4430. u16 eeprom;
  4431. u8 value;
  4432. rt2800_bbp_read(rt2x00dev, 138, &value);
  4433. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
  4434. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
  4435. value |= 0x20;
  4436. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
  4437. value &= ~0x02;
  4438. rt2800_bbp_write(rt2x00dev, 138, value);
  4439. }
  4440. static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
  4441. {
  4442. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  4443. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4444. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4445. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4446. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  4447. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4448. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  4449. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  4450. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4451. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  4452. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4453. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  4454. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4455. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  4456. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4457. rt2800_bbp_write(rt2x00dev, 105, 0x01);
  4458. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4459. }
  4460. static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
  4461. {
  4462. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4463. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4464. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
  4465. rt2800_bbp_write(rt2x00dev, 69, 0x16);
  4466. rt2800_bbp_write(rt2x00dev, 73, 0x12);
  4467. } else {
  4468. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4469. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  4470. }
  4471. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4472. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  4473. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4474. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  4475. if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
  4476. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  4477. else
  4478. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4479. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  4480. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4481. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  4482. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  4483. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  4484. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4485. }
  4486. static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
  4487. {
  4488. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4489. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4490. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4491. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  4492. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4493. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  4494. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  4495. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  4496. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4497. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  4498. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4499. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  4500. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4501. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  4502. if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
  4503. rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
  4504. rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
  4505. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4506. else
  4507. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  4508. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  4509. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4510. if (rt2x00_rt(rt2x00dev, RT3071) ||
  4511. rt2x00_rt(rt2x00dev, RT3090))
  4512. rt2800_disable_unused_dac_adc(rt2x00dev);
  4513. }
  4514. static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
  4515. {
  4516. u8 value;
  4517. rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  4518. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  4519. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4520. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4521. rt2800_bbp_write(rt2x00dev, 68, 0x0b);
  4522. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4523. rt2800_bbp_write(rt2x00dev, 73, 0x13);
  4524. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  4525. rt2800_bbp_write(rt2x00dev, 76, 0x28);
  4526. rt2800_bbp_write(rt2x00dev, 77, 0x58);
  4527. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4528. rt2800_bbp_write(rt2x00dev, 74, 0x0b);
  4529. rt2800_bbp_write(rt2x00dev, 79, 0x18);
  4530. rt2800_bbp_write(rt2x00dev, 80, 0x09);
  4531. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  4532. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4533. rt2800_bbp_write(rt2x00dev, 83, 0x7a);
  4534. rt2800_bbp_write(rt2x00dev, 84, 0x9a);
  4535. rt2800_bbp_write(rt2x00dev, 86, 0x38);
  4536. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4537. rt2800_bbp_write(rt2x00dev, 92, 0x02);
  4538. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4539. rt2800_bbp_write(rt2x00dev, 104, 0x92);
  4540. rt2800_bbp_write(rt2x00dev, 105, 0x1c);
  4541. rt2800_bbp_write(rt2x00dev, 106, 0x03);
  4542. rt2800_bbp_write(rt2x00dev, 128, 0x12);
  4543. rt2800_bbp_write(rt2x00dev, 67, 0x24);
  4544. rt2800_bbp_write(rt2x00dev, 143, 0x04);
  4545. rt2800_bbp_write(rt2x00dev, 142, 0x99);
  4546. rt2800_bbp_write(rt2x00dev, 150, 0x30);
  4547. rt2800_bbp_write(rt2x00dev, 151, 0x2e);
  4548. rt2800_bbp_write(rt2x00dev, 152, 0x20);
  4549. rt2800_bbp_write(rt2x00dev, 153, 0x34);
  4550. rt2800_bbp_write(rt2x00dev, 154, 0x40);
  4551. rt2800_bbp_write(rt2x00dev, 155, 0x3b);
  4552. rt2800_bbp_write(rt2x00dev, 253, 0x04);
  4553. rt2800_bbp_read(rt2x00dev, 47, &value);
  4554. rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
  4555. rt2800_bbp_write(rt2x00dev, 47, value);
  4556. /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
  4557. rt2800_bbp_read(rt2x00dev, 3, &value);
  4558. rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
  4559. rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
  4560. rt2800_bbp_write(rt2x00dev, 3, value);
  4561. }
  4562. static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
  4563. {
  4564. rt2800_bbp_write(rt2x00dev, 3, 0x00);
  4565. rt2800_bbp_write(rt2x00dev, 4, 0x50);
  4566. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  4567. rt2800_bbp_write(rt2x00dev, 47, 0x48);
  4568. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4569. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4570. rt2800_bbp_write(rt2x00dev, 68, 0x0b);
  4571. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4572. rt2800_bbp_write(rt2x00dev, 73, 0x13);
  4573. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  4574. rt2800_bbp_write(rt2x00dev, 76, 0x28);
  4575. rt2800_bbp_write(rt2x00dev, 77, 0x59);
  4576. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4577. rt2800_bbp_write(rt2x00dev, 78, 0x0e);
  4578. rt2800_bbp_write(rt2x00dev, 80, 0x08);
  4579. rt2800_bbp_write(rt2x00dev, 81, 0x37);
  4580. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4581. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  4582. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4583. rt2800_bbp_write(rt2x00dev, 86, 0x38);
  4584. rt2800_bbp_write(rt2x00dev, 88, 0x90);
  4585. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4586. rt2800_bbp_write(rt2x00dev, 92, 0x02);
  4587. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4588. rt2800_bbp_write(rt2x00dev, 104, 0x92);
  4589. rt2800_bbp_write(rt2x00dev, 105, 0x34);
  4590. rt2800_bbp_write(rt2x00dev, 106, 0x05);
  4591. rt2800_bbp_write(rt2x00dev, 120, 0x50);
  4592. rt2800_bbp_write(rt2x00dev, 137, 0x0f);
  4593. rt2800_bbp_write(rt2x00dev, 163, 0xbd);
  4594. /* Set ITxBF timeout to 0x9c40=1000msec */
  4595. rt2800_bbp_write(rt2x00dev, 179, 0x02);
  4596. rt2800_bbp_write(rt2x00dev, 180, 0x00);
  4597. rt2800_bbp_write(rt2x00dev, 182, 0x40);
  4598. rt2800_bbp_write(rt2x00dev, 180, 0x01);
  4599. rt2800_bbp_write(rt2x00dev, 182, 0x9c);
  4600. rt2800_bbp_write(rt2x00dev, 179, 0x00);
  4601. /* Reprogram the inband interface to put right values in RXWI */
  4602. rt2800_bbp_write(rt2x00dev, 142, 0x04);
  4603. rt2800_bbp_write(rt2x00dev, 143, 0x3b);
  4604. rt2800_bbp_write(rt2x00dev, 142, 0x06);
  4605. rt2800_bbp_write(rt2x00dev, 143, 0xa0);
  4606. rt2800_bbp_write(rt2x00dev, 142, 0x07);
  4607. rt2800_bbp_write(rt2x00dev, 143, 0xa1);
  4608. rt2800_bbp_write(rt2x00dev, 142, 0x08);
  4609. rt2800_bbp_write(rt2x00dev, 143, 0xa2);
  4610. rt2800_bbp_write(rt2x00dev, 148, 0xc8);
  4611. }
  4612. static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
  4613. {
  4614. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4615. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4616. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4617. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  4618. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4619. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  4620. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  4621. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  4622. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4623. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  4624. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4625. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  4626. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4627. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  4628. if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
  4629. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4630. else
  4631. rt2800_bbp_write(rt2x00dev, 103, 0x00);
  4632. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  4633. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4634. rt2800_disable_unused_dac_adc(rt2x00dev);
  4635. }
  4636. static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
  4637. {
  4638. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  4639. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4640. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4641. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4642. rt2800_bbp_write(rt2x00dev, 73, 0x10);
  4643. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4644. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  4645. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  4646. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  4647. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4648. rt2800_bbp_write(rt2x00dev, 83, 0x6a);
  4649. rt2800_bbp_write(rt2x00dev, 84, 0x99);
  4650. rt2800_bbp_write(rt2x00dev, 86, 0x00);
  4651. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4652. rt2800_bbp_write(rt2x00dev, 92, 0x00);
  4653. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4654. rt2800_bbp_write(rt2x00dev, 105, 0x05);
  4655. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4656. rt2800_disable_unused_dac_adc(rt2x00dev);
  4657. }
  4658. static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
  4659. {
  4660. rt2800_init_bbp_early(rt2x00dev);
  4661. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  4662. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  4663. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  4664. rt2800_bbp_write(rt2x00dev, 137, 0x0f);
  4665. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  4666. /* Enable DC filter */
  4667. if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
  4668. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4669. }
  4670. static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
  4671. {
  4672. int ant, div_mode;
  4673. u16 eeprom;
  4674. u8 value;
  4675. rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  4676. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  4677. rt2800_bbp_write(rt2x00dev, 65, 0x2c);
  4678. rt2800_bbp_write(rt2x00dev, 66, 0x38);
  4679. rt2800_bbp_write(rt2x00dev, 68, 0x0b);
  4680. rt2800_bbp_write(rt2x00dev, 69, 0x12);
  4681. rt2800_bbp_write(rt2x00dev, 73, 0x13);
  4682. rt2800_bbp_write(rt2x00dev, 75, 0x46);
  4683. rt2800_bbp_write(rt2x00dev, 76, 0x28);
  4684. rt2800_bbp_write(rt2x00dev, 77, 0x59);
  4685. rt2800_bbp_write(rt2x00dev, 70, 0x0a);
  4686. rt2800_bbp_write(rt2x00dev, 79, 0x13);
  4687. rt2800_bbp_write(rt2x00dev, 80, 0x05);
  4688. rt2800_bbp_write(rt2x00dev, 81, 0x33);
  4689. rt2800_bbp_write(rt2x00dev, 82, 0x62);
  4690. rt2800_bbp_write(rt2x00dev, 83, 0x7a);
  4691. rt2800_bbp_write(rt2x00dev, 84, 0x9a);
  4692. rt2800_bbp_write(rt2x00dev, 86, 0x38);
  4693. if (rt2x00_rt(rt2x00dev, RT5392))
  4694. rt2800_bbp_write(rt2x00dev, 88, 0x90);
  4695. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4696. rt2800_bbp_write(rt2x00dev, 92, 0x02);
  4697. if (rt2x00_rt(rt2x00dev, RT5392)) {
  4698. rt2800_bbp_write(rt2x00dev, 95, 0x9a);
  4699. rt2800_bbp_write(rt2x00dev, 98, 0x12);
  4700. }
  4701. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4702. rt2800_bbp_write(rt2x00dev, 104, 0x92);
  4703. rt2800_bbp_write(rt2x00dev, 105, 0x3c);
  4704. if (rt2x00_rt(rt2x00dev, RT5390))
  4705. rt2800_bbp_write(rt2x00dev, 106, 0x03);
  4706. else if (rt2x00_rt(rt2x00dev, RT5392))
  4707. rt2800_bbp_write(rt2x00dev, 106, 0x12);
  4708. else
  4709. WARN_ON(1);
  4710. rt2800_bbp_write(rt2x00dev, 128, 0x12);
  4711. if (rt2x00_rt(rt2x00dev, RT5392)) {
  4712. rt2800_bbp_write(rt2x00dev, 134, 0xd0);
  4713. rt2800_bbp_write(rt2x00dev, 135, 0xf6);
  4714. }
  4715. rt2800_disable_unused_dac_adc(rt2x00dev);
  4716. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
  4717. div_mode = rt2x00_get_field16(eeprom,
  4718. EEPROM_NIC_CONF1_ANT_DIVERSITY);
  4719. ant = (div_mode == 3) ? 1 : 0;
  4720. /* check if this is a Bluetooth combo card */
  4721. if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
  4722. u32 reg;
  4723. rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
  4724. rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
  4725. rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
  4726. rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
  4727. rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
  4728. if (ant == 0)
  4729. rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
  4730. else if (ant == 1)
  4731. rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
  4732. rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
  4733. }
  4734. /* This chip has hardware antenna diversity*/
  4735. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
  4736. rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
  4737. rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
  4738. rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
  4739. }
  4740. rt2800_bbp_read(rt2x00dev, 152, &value);
  4741. if (ant == 0)
  4742. rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
  4743. else
  4744. rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
  4745. rt2800_bbp_write(rt2x00dev, 152, value);
  4746. rt2800_init_freq_calibration(rt2x00dev);
  4747. }
  4748. static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
  4749. {
  4750. int ant, div_mode;
  4751. u16 eeprom;
  4752. u8 value;
  4753. rt2800_init_bbp_early(rt2x00dev);
  4754. rt2800_bbp_read(rt2x00dev, 105, &value);
  4755. rt2x00_set_field8(&value, BBP105_MLD,
  4756. rt2x00dev->default_ant.rx_chain_num == 2);
  4757. rt2800_bbp_write(rt2x00dev, 105, value);
  4758. rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  4759. rt2800_bbp_write(rt2x00dev, 20, 0x06);
  4760. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  4761. rt2800_bbp_write(rt2x00dev, 65, 0x2C);
  4762. rt2800_bbp_write(rt2x00dev, 68, 0xDD);
  4763. rt2800_bbp_write(rt2x00dev, 69, 0x1A);
  4764. rt2800_bbp_write(rt2x00dev, 70, 0x05);
  4765. rt2800_bbp_write(rt2x00dev, 73, 0x13);
  4766. rt2800_bbp_write(rt2x00dev, 74, 0x0F);
  4767. rt2800_bbp_write(rt2x00dev, 75, 0x4F);
  4768. rt2800_bbp_write(rt2x00dev, 76, 0x28);
  4769. rt2800_bbp_write(rt2x00dev, 77, 0x59);
  4770. rt2800_bbp_write(rt2x00dev, 84, 0x9A);
  4771. rt2800_bbp_write(rt2x00dev, 86, 0x38);
  4772. rt2800_bbp_write(rt2x00dev, 88, 0x90);
  4773. rt2800_bbp_write(rt2x00dev, 91, 0x04);
  4774. rt2800_bbp_write(rt2x00dev, 92, 0x02);
  4775. rt2800_bbp_write(rt2x00dev, 95, 0x9a);
  4776. rt2800_bbp_write(rt2x00dev, 98, 0x12);
  4777. rt2800_bbp_write(rt2x00dev, 103, 0xC0);
  4778. rt2800_bbp_write(rt2x00dev, 104, 0x92);
  4779. /* FIXME BBP105 owerwrite */
  4780. rt2800_bbp_write(rt2x00dev, 105, 0x3C);
  4781. rt2800_bbp_write(rt2x00dev, 106, 0x35);
  4782. rt2800_bbp_write(rt2x00dev, 128, 0x12);
  4783. rt2800_bbp_write(rt2x00dev, 134, 0xD0);
  4784. rt2800_bbp_write(rt2x00dev, 135, 0xF6);
  4785. rt2800_bbp_write(rt2x00dev, 137, 0x0F);
  4786. /* Initialize GLRT (Generalized Likehood Radio Test) */
  4787. rt2800_init_bbp_5592_glrt(rt2x00dev);
  4788. rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  4789. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
  4790. div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
  4791. ant = (div_mode == 3) ? 1 : 0;
  4792. rt2800_bbp_read(rt2x00dev, 152, &value);
  4793. if (ant == 0) {
  4794. /* Main antenna */
  4795. rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
  4796. } else {
  4797. /* Auxiliary antenna */
  4798. rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
  4799. }
  4800. rt2800_bbp_write(rt2x00dev, 152, value);
  4801. if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
  4802. rt2800_bbp_read(rt2x00dev, 254, &value);
  4803. rt2x00_set_field8(&value, BBP254_BIT7, 1);
  4804. rt2800_bbp_write(rt2x00dev, 254, value);
  4805. }
  4806. rt2800_init_freq_calibration(rt2x00dev);
  4807. rt2800_bbp_write(rt2x00dev, 84, 0x19);
  4808. if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
  4809. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  4810. }
  4811. static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
  4812. {
  4813. unsigned int i;
  4814. u16 eeprom;
  4815. u8 reg_id;
  4816. u8 value;
  4817. if (rt2800_is_305x_soc(rt2x00dev))
  4818. rt2800_init_bbp_305x_soc(rt2x00dev);
  4819. switch (rt2x00dev->chip.rt) {
  4820. case RT2860:
  4821. case RT2872:
  4822. case RT2883:
  4823. rt2800_init_bbp_28xx(rt2x00dev);
  4824. break;
  4825. case RT3070:
  4826. case RT3071:
  4827. case RT3090:
  4828. rt2800_init_bbp_30xx(rt2x00dev);
  4829. break;
  4830. case RT3290:
  4831. rt2800_init_bbp_3290(rt2x00dev);
  4832. break;
  4833. case RT3352:
  4834. rt2800_init_bbp_3352(rt2x00dev);
  4835. break;
  4836. case RT3390:
  4837. rt2800_init_bbp_3390(rt2x00dev);
  4838. break;
  4839. case RT3572:
  4840. rt2800_init_bbp_3572(rt2x00dev);
  4841. break;
  4842. case RT3593:
  4843. rt2800_init_bbp_3593(rt2x00dev);
  4844. return;
  4845. case RT5390:
  4846. case RT5392:
  4847. rt2800_init_bbp_53xx(rt2x00dev);
  4848. break;
  4849. case RT5592:
  4850. rt2800_init_bbp_5592(rt2x00dev);
  4851. return;
  4852. }
  4853. for (i = 0; i < EEPROM_BBP_SIZE; i++) {
  4854. rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_BBP_START, i,
  4855. &eeprom);
  4856. if (eeprom != 0xffff && eeprom != 0x0000) {
  4857. reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
  4858. value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
  4859. rt2800_bbp_write(rt2x00dev, reg_id, value);
  4860. }
  4861. }
  4862. }
  4863. static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
  4864. {
  4865. u32 reg;
  4866. rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
  4867. rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
  4868. rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
  4869. }
  4870. static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
  4871. u8 filter_target)
  4872. {
  4873. unsigned int i;
  4874. u8 bbp;
  4875. u8 rfcsr;
  4876. u8 passband;
  4877. u8 stopband;
  4878. u8 overtuned = 0;
  4879. u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
  4880. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  4881. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  4882. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
  4883. rt2800_bbp_write(rt2x00dev, 4, bbp);
  4884. rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
  4885. rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
  4886. rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
  4887. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  4888. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
  4889. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  4890. /*
  4891. * Set power & frequency of passband test tone
  4892. */
  4893. rt2800_bbp_write(rt2x00dev, 24, 0);
  4894. for (i = 0; i < 100; i++) {
  4895. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  4896. msleep(1);
  4897. rt2800_bbp_read(rt2x00dev, 55, &passband);
  4898. if (passband)
  4899. break;
  4900. }
  4901. /*
  4902. * Set power & frequency of stopband test tone
  4903. */
  4904. rt2800_bbp_write(rt2x00dev, 24, 0x06);
  4905. for (i = 0; i < 100; i++) {
  4906. rt2800_bbp_write(rt2x00dev, 25, 0x90);
  4907. msleep(1);
  4908. rt2800_bbp_read(rt2x00dev, 55, &stopband);
  4909. if ((passband - stopband) <= filter_target) {
  4910. rfcsr24++;
  4911. overtuned += ((passband - stopband) == filter_target);
  4912. } else
  4913. break;
  4914. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  4915. }
  4916. rfcsr24 -= !!overtuned;
  4917. rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
  4918. return rfcsr24;
  4919. }
  4920. static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
  4921. const unsigned int rf_reg)
  4922. {
  4923. u8 rfcsr;
  4924. rt2800_rfcsr_read(rt2x00dev, rf_reg, &rfcsr);
  4925. rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
  4926. rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
  4927. msleep(1);
  4928. rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
  4929. rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
  4930. }
  4931. static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
  4932. {
  4933. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  4934. u8 filter_tgt_bw20;
  4935. u8 filter_tgt_bw40;
  4936. u8 rfcsr, bbp;
  4937. /*
  4938. * TODO: sync filter_tgt values with vendor driver
  4939. */
  4940. if (rt2x00_rt(rt2x00dev, RT3070)) {
  4941. filter_tgt_bw20 = 0x16;
  4942. filter_tgt_bw40 = 0x19;
  4943. } else {
  4944. filter_tgt_bw20 = 0x13;
  4945. filter_tgt_bw40 = 0x15;
  4946. }
  4947. drv_data->calibration_bw20 =
  4948. rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
  4949. drv_data->calibration_bw40 =
  4950. rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
  4951. /*
  4952. * Save BBP 25 & 26 values for later use in channel switching (for 3052)
  4953. */
  4954. rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
  4955. rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
  4956. /*
  4957. * Set back to initial state
  4958. */
  4959. rt2800_bbp_write(rt2x00dev, 24, 0);
  4960. rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
  4961. rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
  4962. rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
  4963. /*
  4964. * Set BBP back to BW20
  4965. */
  4966. rt2800_bbp_read(rt2x00dev, 4, &bbp);
  4967. rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
  4968. rt2800_bbp_write(rt2x00dev, 4, bbp);
  4969. }
  4970. static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
  4971. {
  4972. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  4973. u8 min_gain, rfcsr, bbp;
  4974. u16 eeprom;
  4975. rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
  4976. rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
  4977. if (rt2x00_rt(rt2x00dev, RT3070) ||
  4978. rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  4979. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
  4980. rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
  4981. if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
  4982. rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
  4983. }
  4984. min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
  4985. if (drv_data->txmixer_gain_24g >= min_gain) {
  4986. rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
  4987. drv_data->txmixer_gain_24g);
  4988. }
  4989. rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
  4990. if (rt2x00_rt(rt2x00dev, RT3090)) {
  4991. /* Turn off unused DAC1 and ADC1 to reduce power consumption */
  4992. rt2800_bbp_read(rt2x00dev, 138, &bbp);
  4993. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
  4994. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
  4995. rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
  4996. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
  4997. rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
  4998. rt2800_bbp_write(rt2x00dev, 138, bbp);
  4999. }
  5000. if (rt2x00_rt(rt2x00dev, RT3070)) {
  5001. rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
  5002. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
  5003. rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
  5004. else
  5005. rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
  5006. rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
  5007. rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
  5008. rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
  5009. rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
  5010. } else if (rt2x00_rt(rt2x00dev, RT3071) ||
  5011. rt2x00_rt(rt2x00dev, RT3090) ||
  5012. rt2x00_rt(rt2x00dev, RT3390)) {
  5013. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  5014. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  5015. rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
  5016. rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
  5017. rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
  5018. rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
  5019. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  5020. rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
  5021. rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
  5022. rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
  5023. rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
  5024. rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
  5025. rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
  5026. rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
  5027. rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
  5028. rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
  5029. }
  5030. }
  5031. static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
  5032. {
  5033. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  5034. u8 rfcsr;
  5035. u8 tx_gain;
  5036. rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
  5037. rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
  5038. rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
  5039. rt2800_rfcsr_read(rt2x00dev, 51, &rfcsr);
  5040. tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
  5041. RFCSR17_TXMIXER_GAIN);
  5042. rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
  5043. rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
  5044. rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
  5045. rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
  5046. rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
  5047. rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
  5048. rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
  5049. rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
  5050. rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
  5051. rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
  5052. rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
  5053. rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
  5054. rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
  5055. rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
  5056. rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
  5057. /* TODO: enable stream mode */
  5058. }
  5059. static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
  5060. {
  5061. u8 reg;
  5062. u16 eeprom;
  5063. /* Turn off unused DAC1 and ADC1 to reduce power consumption */
  5064. rt2800_bbp_read(rt2x00dev, 138, &reg);
  5065. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
  5066. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
  5067. rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
  5068. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
  5069. rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
  5070. rt2800_bbp_write(rt2x00dev, 138, reg);
  5071. rt2800_rfcsr_read(rt2x00dev, 38, &reg);
  5072. rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
  5073. rt2800_rfcsr_write(rt2x00dev, 38, reg);
  5074. rt2800_rfcsr_read(rt2x00dev, 39, &reg);
  5075. rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
  5076. rt2800_rfcsr_write(rt2x00dev, 39, reg);
  5077. rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  5078. rt2800_rfcsr_read(rt2x00dev, 30, &reg);
  5079. rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
  5080. rt2800_rfcsr_write(rt2x00dev, 30, reg);
  5081. }
  5082. static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
  5083. {
  5084. rt2800_rf_init_calibration(rt2x00dev, 30);
  5085. rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
  5086. rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
  5087. rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
  5088. rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
  5089. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  5090. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  5091. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  5092. rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
  5093. rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
  5094. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  5095. rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
  5096. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  5097. rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
  5098. rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
  5099. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  5100. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  5101. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  5102. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  5103. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  5104. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  5105. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  5106. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  5107. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  5108. rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
  5109. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  5110. rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
  5111. rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
  5112. rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
  5113. rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
  5114. rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
  5115. rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
  5116. rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
  5117. }
  5118. static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
  5119. {
  5120. u8 rfcsr;
  5121. u16 eeprom;
  5122. u32 reg;
  5123. /* XXX vendor driver do this only for 3070 */
  5124. rt2800_rf_init_calibration(rt2x00dev, 30);
  5125. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  5126. rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
  5127. rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
  5128. rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
  5129. rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
  5130. rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
  5131. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  5132. rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
  5133. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  5134. rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
  5135. rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
  5136. rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
  5137. rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
  5138. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  5139. rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
  5140. rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
  5141. rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
  5142. rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
  5143. rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
  5144. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
  5145. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  5146. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  5147. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  5148. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  5149. } else if (rt2x00_rt(rt2x00dev, RT3071) ||
  5150. rt2x00_rt(rt2x00dev, RT3090)) {
  5151. rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
  5152. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  5153. rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
  5154. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  5155. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  5156. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  5157. if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  5158. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
  5159. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1,
  5160. &eeprom);
  5161. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
  5162. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  5163. else
  5164. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
  5165. }
  5166. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  5167. rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
  5168. rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
  5169. rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
  5170. }
  5171. rt2800_rx_filter_calibration(rt2x00dev);
  5172. if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
  5173. rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
  5174. rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
  5175. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  5176. rt2800_led_open_drain_enable(rt2x00dev);
  5177. rt2800_normal_mode_setup_3xxx(rt2x00dev);
  5178. }
  5179. static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
  5180. {
  5181. u8 rfcsr;
  5182. rt2800_rf_init_calibration(rt2x00dev, 2);
  5183. rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
  5184. rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
  5185. rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
  5186. rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
  5187. rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
  5188. rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
  5189. rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
  5190. rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
  5191. rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
  5192. rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
  5193. rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
  5194. rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
  5195. rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
  5196. rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
  5197. rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
  5198. rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
  5199. rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
  5200. rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  5201. rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  5202. rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  5203. rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
  5204. rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
  5205. rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
  5206. rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  5207. rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
  5208. rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
  5209. rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
  5210. rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
  5211. rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
  5212. rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
  5213. rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
  5214. rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
  5215. rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
  5216. rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
  5217. rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
  5218. rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
  5219. rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
  5220. rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
  5221. rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
  5222. rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
  5223. rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
  5224. rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
  5225. rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
  5226. rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
  5227. rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
  5228. rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
  5229. rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
  5230. rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
  5231. rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
  5232. rt2800_led_open_drain_enable(rt2x00dev);
  5233. rt2800_normal_mode_setup_3xxx(rt2x00dev);
  5234. }
  5235. static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
  5236. {
  5237. rt2800_rf_init_calibration(rt2x00dev, 30);
  5238. rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
  5239. rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
  5240. rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
  5241. rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
  5242. rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
  5243. rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
  5244. rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
  5245. rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  5246. rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
  5247. rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
  5248. rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
  5249. rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
  5250. rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
  5251. rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
  5252. rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
  5253. rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
  5254. rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
  5255. rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
  5256. rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
  5257. rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
  5258. rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
  5259. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  5260. rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
  5261. rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  5262. rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
  5263. rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
  5264. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  5265. rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
  5266. rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
  5267. rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  5268. rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  5269. rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  5270. rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
  5271. rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
  5272. rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
  5273. rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
  5274. rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
  5275. rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
  5276. rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
  5277. rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
  5278. rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
  5279. rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
  5280. rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
  5281. rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
  5282. rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
  5283. rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
  5284. rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
  5285. rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
  5286. rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
  5287. rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
  5288. rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
  5289. rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
  5290. rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
  5291. rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
  5292. rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
  5293. rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
  5294. rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
  5295. rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
  5296. rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
  5297. rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
  5298. rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
  5299. rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
  5300. rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
  5301. rt2800_rx_filter_calibration(rt2x00dev);
  5302. rt2800_led_open_drain_enable(rt2x00dev);
  5303. rt2800_normal_mode_setup_3xxx(rt2x00dev);
  5304. }
  5305. static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
  5306. {
  5307. u32 reg;
  5308. rt2800_rf_init_calibration(rt2x00dev, 30);
  5309. rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
  5310. rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
  5311. rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
  5312. rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
  5313. rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
  5314. rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
  5315. rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
  5316. rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
  5317. rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
  5318. rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
  5319. rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
  5320. rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
  5321. rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
  5322. rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
  5323. rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
  5324. rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
  5325. rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
  5326. rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
  5327. rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
  5328. rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
  5329. rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
  5330. rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
  5331. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  5332. rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
  5333. rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
  5334. rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
  5335. rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
  5336. rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  5337. rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
  5338. rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
  5339. rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
  5340. rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
  5341. rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
  5342. rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
  5343. rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
  5344. rt2800_rx_filter_calibration(rt2x00dev);
  5345. if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
  5346. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  5347. rt2800_led_open_drain_enable(rt2x00dev);
  5348. rt2800_normal_mode_setup_3xxx(rt2x00dev);
  5349. }
  5350. static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
  5351. {
  5352. u8 rfcsr;
  5353. u32 reg;
  5354. rt2800_rf_init_calibration(rt2x00dev, 30);
  5355. rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
  5356. rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
  5357. rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
  5358. rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
  5359. rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
  5360. rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
  5361. rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
  5362. rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
  5363. rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
  5364. rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
  5365. rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
  5366. rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
  5367. rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
  5368. rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
  5369. rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
  5370. rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
  5371. rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
  5372. rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
  5373. rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
  5374. rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
  5375. rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
  5376. rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
  5377. rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
  5378. rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
  5379. rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
  5380. rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
  5381. rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
  5382. rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  5383. rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
  5384. rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
  5385. rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
  5386. rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
  5387. rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
  5388. rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
  5389. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  5390. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  5391. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  5392. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  5393. msleep(1);
  5394. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  5395. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
  5396. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  5397. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  5398. rt2800_rx_filter_calibration(rt2x00dev);
  5399. rt2800_led_open_drain_enable(rt2x00dev);
  5400. rt2800_normal_mode_setup_3xxx(rt2x00dev);
  5401. }
  5402. static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
  5403. {
  5404. u8 bbp;
  5405. bool txbf_enabled = false; /* FIXME */
  5406. rt2800_bbp_read(rt2x00dev, 105, &bbp);
  5407. if (rt2x00dev->default_ant.rx_chain_num == 1)
  5408. rt2x00_set_field8(&bbp, BBP105_MLD, 0);
  5409. else
  5410. rt2x00_set_field8(&bbp, BBP105_MLD, 1);
  5411. rt2800_bbp_write(rt2x00dev, 105, bbp);
  5412. rt2800_bbp4_mac_if_ctrl(rt2x00dev);
  5413. rt2800_bbp_write(rt2x00dev, 92, 0x02);
  5414. rt2800_bbp_write(rt2x00dev, 82, 0x82);
  5415. rt2800_bbp_write(rt2x00dev, 106, 0x05);
  5416. rt2800_bbp_write(rt2x00dev, 104, 0x92);
  5417. rt2800_bbp_write(rt2x00dev, 88, 0x90);
  5418. rt2800_bbp_write(rt2x00dev, 148, 0xc8);
  5419. rt2800_bbp_write(rt2x00dev, 47, 0x48);
  5420. rt2800_bbp_write(rt2x00dev, 120, 0x50);
  5421. if (txbf_enabled)
  5422. rt2800_bbp_write(rt2x00dev, 163, 0xbd);
  5423. else
  5424. rt2800_bbp_write(rt2x00dev, 163, 0x9d);
  5425. /* SNR mapping */
  5426. rt2800_bbp_write(rt2x00dev, 142, 6);
  5427. rt2800_bbp_write(rt2x00dev, 143, 160);
  5428. rt2800_bbp_write(rt2x00dev, 142, 7);
  5429. rt2800_bbp_write(rt2x00dev, 143, 161);
  5430. rt2800_bbp_write(rt2x00dev, 142, 8);
  5431. rt2800_bbp_write(rt2x00dev, 143, 162);
  5432. /* ADC/DAC control */
  5433. rt2800_bbp_write(rt2x00dev, 31, 0x08);
  5434. /* RX AGC energy lower bound in log2 */
  5435. rt2800_bbp_write(rt2x00dev, 68, 0x0b);
  5436. /* FIXME: BBP 105 owerwrite? */
  5437. rt2800_bbp_write(rt2x00dev, 105, 0x04);
  5438. }
  5439. static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
  5440. {
  5441. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  5442. u32 reg;
  5443. u8 rfcsr;
  5444. /* Disable GPIO #4 and #7 function for LAN PE control */
  5445. rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
  5446. rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
  5447. rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
  5448. rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
  5449. /* Initialize default register values */
  5450. rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
  5451. rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
  5452. rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
  5453. rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
  5454. rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
  5455. rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
  5456. rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
  5457. rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
  5458. rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
  5459. rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
  5460. rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
  5461. rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
  5462. rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  5463. rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  5464. rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
  5465. rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
  5466. rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
  5467. rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
  5468. rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
  5469. rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
  5470. rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
  5471. rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
  5472. rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
  5473. rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
  5474. rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
  5475. rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
  5476. rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
  5477. rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
  5478. rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
  5479. rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
  5480. rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
  5481. rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
  5482. /* Initiate calibration */
  5483. /* TODO: use rt2800_rf_init_calibration ? */
  5484. rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
  5485. rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
  5486. rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
  5487. rt2800_adjust_freq_offset(rt2x00dev);
  5488. rt2800_rfcsr_read(rt2x00dev, 18, &rfcsr);
  5489. rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
  5490. rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
  5491. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  5492. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
  5493. rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
  5494. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  5495. usleep_range(1000, 1500);
  5496. rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
  5497. rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
  5498. rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
  5499. /* Set initial values for RX filter calibration */
  5500. drv_data->calibration_bw20 = 0x1f;
  5501. drv_data->calibration_bw40 = 0x2f;
  5502. /* Save BBP 25 & 26 values for later use in channel switching */
  5503. rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
  5504. rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
  5505. rt2800_led_open_drain_enable(rt2x00dev);
  5506. rt2800_normal_mode_setup_3593(rt2x00dev);
  5507. rt3593_post_bbp_init(rt2x00dev);
  5508. /* TODO: enable stream mode support */
  5509. }
  5510. static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
  5511. {
  5512. rt2800_rf_init_calibration(rt2x00dev, 2);
  5513. rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
  5514. rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
  5515. rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
  5516. rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
  5517. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
  5518. rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
  5519. else
  5520. rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
  5521. rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  5522. rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
  5523. rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
  5524. rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
  5525. rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
  5526. rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
  5527. rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
  5528. rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
  5529. rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
  5530. rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
  5531. rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
  5532. rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
  5533. rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
  5534. rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
  5535. rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
  5536. if (rt2x00_is_usb(rt2x00dev) &&
  5537. rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
  5538. rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
  5539. else
  5540. rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
  5541. rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
  5542. rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
  5543. rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  5544. rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
  5545. rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  5546. rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  5547. rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
  5548. rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
  5549. rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
  5550. rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
  5551. rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  5552. rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
  5553. rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
  5554. rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
  5555. rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
  5556. rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
  5557. rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
  5558. rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
  5559. rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
  5560. rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
  5561. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
  5562. rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
  5563. else
  5564. rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
  5565. rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
  5566. rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
  5567. rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
  5568. rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
  5569. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
  5570. rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
  5571. else
  5572. rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
  5573. rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
  5574. rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
  5575. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
  5576. rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
  5577. else
  5578. rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
  5579. rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
  5580. rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
  5581. rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
  5582. rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
  5583. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
  5584. if (rt2x00_is_usb(rt2x00dev))
  5585. rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
  5586. else
  5587. rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
  5588. } else {
  5589. if (rt2x00_is_usb(rt2x00dev))
  5590. rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
  5591. else
  5592. rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
  5593. }
  5594. rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
  5595. rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
  5596. rt2800_normal_mode_setup_5xxx(rt2x00dev);
  5597. rt2800_led_open_drain_enable(rt2x00dev);
  5598. }
  5599. static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
  5600. {
  5601. rt2800_rf_init_calibration(rt2x00dev, 2);
  5602. rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
  5603. rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
  5604. rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
  5605. rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
  5606. rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  5607. rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
  5608. rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
  5609. rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
  5610. rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
  5611. rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
  5612. rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
  5613. rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
  5614. rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
  5615. rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
  5616. rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
  5617. rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
  5618. rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
  5619. rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
  5620. rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
  5621. rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
  5622. rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
  5623. rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
  5624. rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  5625. rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
  5626. rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
  5627. rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
  5628. rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
  5629. rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
  5630. rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
  5631. rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
  5632. rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
  5633. rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
  5634. rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
  5635. rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
  5636. rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
  5637. rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
  5638. rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
  5639. rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
  5640. rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
  5641. rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
  5642. rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
  5643. rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
  5644. rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
  5645. rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
  5646. rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
  5647. rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
  5648. rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
  5649. rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
  5650. rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
  5651. rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
  5652. rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
  5653. rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
  5654. rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
  5655. rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
  5656. rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
  5657. rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
  5658. rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
  5659. rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
  5660. rt2800_normal_mode_setup_5xxx(rt2x00dev);
  5661. rt2800_led_open_drain_enable(rt2x00dev);
  5662. }
  5663. static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
  5664. {
  5665. rt2800_rf_init_calibration(rt2x00dev, 30);
  5666. rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
  5667. rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
  5668. rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
  5669. rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
  5670. rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
  5671. rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
  5672. rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
  5673. rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
  5674. rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
  5675. rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
  5676. rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
  5677. rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
  5678. rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
  5679. rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
  5680. rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
  5681. rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
  5682. rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
  5683. rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
  5684. rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
  5685. rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
  5686. rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
  5687. rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
  5688. msleep(1);
  5689. rt2800_adjust_freq_offset(rt2x00dev);
  5690. /* Enable DC filter */
  5691. if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
  5692. rt2800_bbp_write(rt2x00dev, 103, 0xc0);
  5693. rt2800_normal_mode_setup_5xxx(rt2x00dev);
  5694. if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
  5695. rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
  5696. rt2800_led_open_drain_enable(rt2x00dev);
  5697. }
  5698. static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
  5699. {
  5700. if (rt2800_is_305x_soc(rt2x00dev)) {
  5701. rt2800_init_rfcsr_305x_soc(rt2x00dev);
  5702. return;
  5703. }
  5704. switch (rt2x00dev->chip.rt) {
  5705. case RT3070:
  5706. case RT3071:
  5707. case RT3090:
  5708. rt2800_init_rfcsr_30xx(rt2x00dev);
  5709. break;
  5710. case RT3290:
  5711. rt2800_init_rfcsr_3290(rt2x00dev);
  5712. break;
  5713. case RT3352:
  5714. rt2800_init_rfcsr_3352(rt2x00dev);
  5715. break;
  5716. case RT3390:
  5717. rt2800_init_rfcsr_3390(rt2x00dev);
  5718. break;
  5719. case RT3572:
  5720. rt2800_init_rfcsr_3572(rt2x00dev);
  5721. break;
  5722. case RT3593:
  5723. rt2800_init_rfcsr_3593(rt2x00dev);
  5724. break;
  5725. case RT5390:
  5726. rt2800_init_rfcsr_5390(rt2x00dev);
  5727. break;
  5728. case RT5392:
  5729. rt2800_init_rfcsr_5392(rt2x00dev);
  5730. break;
  5731. case RT5592:
  5732. rt2800_init_rfcsr_5592(rt2x00dev);
  5733. break;
  5734. }
  5735. }
  5736. int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
  5737. {
  5738. u32 reg;
  5739. u16 word;
  5740. /*
  5741. * Initialize MAC registers.
  5742. */
  5743. if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
  5744. rt2800_init_registers(rt2x00dev)))
  5745. return -EIO;
  5746. /*
  5747. * Wait BBP/RF to wake up.
  5748. */
  5749. if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
  5750. return -EIO;
  5751. /*
  5752. * Send signal during boot time to initialize firmware.
  5753. */
  5754. rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
  5755. rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
  5756. if (rt2x00_is_usb(rt2x00dev))
  5757. rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
  5758. rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
  5759. msleep(1);
  5760. /*
  5761. * Make sure BBP is up and running.
  5762. */
  5763. if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
  5764. return -EIO;
  5765. /*
  5766. * Initialize BBP/RF registers.
  5767. */
  5768. rt2800_init_bbp(rt2x00dev);
  5769. rt2800_init_rfcsr(rt2x00dev);
  5770. if (rt2x00_is_usb(rt2x00dev) &&
  5771. (rt2x00_rt(rt2x00dev, RT3070) ||
  5772. rt2x00_rt(rt2x00dev, RT3071) ||
  5773. rt2x00_rt(rt2x00dev, RT3572))) {
  5774. udelay(200);
  5775. rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
  5776. udelay(10);
  5777. }
  5778. /*
  5779. * Enable RX.
  5780. */
  5781. rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  5782. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
  5783. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
  5784. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  5785. udelay(50);
  5786. rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
  5787. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
  5788. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
  5789. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
  5790. rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
  5791. rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
  5792. rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  5793. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
  5794. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
  5795. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  5796. /*
  5797. * Initialize LED control
  5798. */
  5799. rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
  5800. rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
  5801. word & 0xff, (word >> 8) & 0xff);
  5802. rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
  5803. rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
  5804. word & 0xff, (word >> 8) & 0xff);
  5805. rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
  5806. rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
  5807. word & 0xff, (word >> 8) & 0xff);
  5808. return 0;
  5809. }
  5810. EXPORT_SYMBOL_GPL(rt2800_enable_radio);
  5811. void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
  5812. {
  5813. u32 reg;
  5814. rt2800_disable_wpdma(rt2x00dev);
  5815. /* Wait for DMA, ignore error */
  5816. rt2800_wait_wpdma_ready(rt2x00dev);
  5817. rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
  5818. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
  5819. rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
  5820. rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
  5821. }
  5822. EXPORT_SYMBOL_GPL(rt2800_disable_radio);
  5823. int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
  5824. {
  5825. u32 reg;
  5826. u16 efuse_ctrl_reg;
  5827. if (rt2x00_rt(rt2x00dev, RT3290))
  5828. efuse_ctrl_reg = EFUSE_CTRL_3290;
  5829. else
  5830. efuse_ctrl_reg = EFUSE_CTRL;
  5831. rt2800_register_read(rt2x00dev, efuse_ctrl_reg, &reg);
  5832. return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
  5833. }
  5834. EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
  5835. static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
  5836. {
  5837. u32 reg;
  5838. u16 efuse_ctrl_reg;
  5839. u16 efuse_data0_reg;
  5840. u16 efuse_data1_reg;
  5841. u16 efuse_data2_reg;
  5842. u16 efuse_data3_reg;
  5843. if (rt2x00_rt(rt2x00dev, RT3290)) {
  5844. efuse_ctrl_reg = EFUSE_CTRL_3290;
  5845. efuse_data0_reg = EFUSE_DATA0_3290;
  5846. efuse_data1_reg = EFUSE_DATA1_3290;
  5847. efuse_data2_reg = EFUSE_DATA2_3290;
  5848. efuse_data3_reg = EFUSE_DATA3_3290;
  5849. } else {
  5850. efuse_ctrl_reg = EFUSE_CTRL;
  5851. efuse_data0_reg = EFUSE_DATA0;
  5852. efuse_data1_reg = EFUSE_DATA1;
  5853. efuse_data2_reg = EFUSE_DATA2;
  5854. efuse_data3_reg = EFUSE_DATA3;
  5855. }
  5856. mutex_lock(&rt2x00dev->csr_mutex);
  5857. rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, &reg);
  5858. rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
  5859. rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
  5860. rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
  5861. rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
  5862. /* Wait until the EEPROM has been loaded */
  5863. rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
  5864. /* Apparently the data is read from end to start */
  5865. rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, &reg);
  5866. /* The returned value is in CPU order, but eeprom is le */
  5867. *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
  5868. rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, &reg);
  5869. *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
  5870. rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, &reg);
  5871. *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
  5872. rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, &reg);
  5873. *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
  5874. mutex_unlock(&rt2x00dev->csr_mutex);
  5875. }
  5876. int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
  5877. {
  5878. unsigned int i;
  5879. for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
  5880. rt2800_efuse_read(rt2x00dev, i);
  5881. return 0;
  5882. }
  5883. EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
  5884. static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
  5885. {
  5886. u16 word;
  5887. if (rt2x00_rt(rt2x00dev, RT3593))
  5888. return 0;
  5889. rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
  5890. if ((word & 0x00ff) != 0x00ff)
  5891. return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
  5892. return 0;
  5893. }
  5894. static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
  5895. {
  5896. u16 word;
  5897. if (rt2x00_rt(rt2x00dev, RT3593))
  5898. return 0;
  5899. rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
  5900. if ((word & 0x00ff) != 0x00ff)
  5901. return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
  5902. return 0;
  5903. }
  5904. static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
  5905. {
  5906. struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
  5907. u16 word;
  5908. u8 *mac;
  5909. u8 default_lna_gain;
  5910. int retval;
  5911. /*
  5912. * Read the EEPROM.
  5913. */
  5914. retval = rt2800_read_eeprom(rt2x00dev);
  5915. if (retval)
  5916. return retval;
  5917. /*
  5918. * Start validation of the data that has been read.
  5919. */
  5920. mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
  5921. if (!is_valid_ether_addr(mac)) {
  5922. eth_random_addr(mac);
  5923. rt2x00_eeprom_dbg(rt2x00dev, "MAC: %pM\n", mac);
  5924. }
  5925. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
  5926. if (word == 0xffff) {
  5927. rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
  5928. rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
  5929. rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
  5930. rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
  5931. rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
  5932. } else if (rt2x00_rt(rt2x00dev, RT2860) ||
  5933. rt2x00_rt(rt2x00dev, RT2872)) {
  5934. /*
  5935. * There is a max of 2 RX streams for RT28x0 series
  5936. */
  5937. if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
  5938. rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
  5939. rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
  5940. }
  5941. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
  5942. if (word == 0xffff) {
  5943. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
  5944. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
  5945. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
  5946. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
  5947. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
  5948. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
  5949. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
  5950. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
  5951. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
  5952. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
  5953. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
  5954. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
  5955. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
  5956. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
  5957. rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
  5958. rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
  5959. rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
  5960. }
  5961. rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
  5962. if ((word & 0x00ff) == 0x00ff) {
  5963. rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
  5964. rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  5965. rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
  5966. }
  5967. if ((word & 0xff00) == 0xff00) {
  5968. rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
  5969. LED_MODE_TXRX_ACTIVITY);
  5970. rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
  5971. rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
  5972. rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
  5973. rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
  5974. rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
  5975. rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
  5976. }
  5977. /*
  5978. * During the LNA validation we are going to use
  5979. * lna0 as correct value. Note that EEPROM_LNA
  5980. * is never validated.
  5981. */
  5982. rt2800_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
  5983. default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
  5984. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
  5985. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
  5986. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
  5987. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
  5988. rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
  5989. rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
  5990. drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
  5991. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
  5992. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
  5993. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
  5994. if (!rt2x00_rt(rt2x00dev, RT3593)) {
  5995. if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
  5996. rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
  5997. rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
  5998. default_lna_gain);
  5999. }
  6000. rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
  6001. drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
  6002. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
  6003. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
  6004. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
  6005. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
  6006. rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
  6007. rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
  6008. rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
  6009. if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
  6010. rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
  6011. if (!rt2x00_rt(rt2x00dev, RT3593)) {
  6012. if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
  6013. rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
  6014. rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
  6015. default_lna_gain);
  6016. }
  6017. rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
  6018. if (rt2x00_rt(rt2x00dev, RT3593)) {
  6019. rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2, &word);
  6020. if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
  6021. rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
  6022. rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
  6023. default_lna_gain);
  6024. if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
  6025. rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
  6026. rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
  6027. default_lna_gain);
  6028. rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
  6029. }
  6030. return 0;
  6031. }
  6032. static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
  6033. {
  6034. u16 value;
  6035. u16 eeprom;
  6036. u16 rf;
  6037. /*
  6038. * Read EEPROM word for configuration.
  6039. */
  6040. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
  6041. /*
  6042. * Identify RF chipset by EEPROM value
  6043. * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
  6044. * RT53xx: defined in "EEPROM_CHIP_ID" field
  6045. */
  6046. if (rt2x00_rt(rt2x00dev, RT3290) ||
  6047. rt2x00_rt(rt2x00dev, RT5390) ||
  6048. rt2x00_rt(rt2x00dev, RT5392))
  6049. rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &rf);
  6050. else
  6051. rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
  6052. switch (rf) {
  6053. case RF2820:
  6054. case RF2850:
  6055. case RF2720:
  6056. case RF2750:
  6057. case RF3020:
  6058. case RF2020:
  6059. case RF3021:
  6060. case RF3022:
  6061. case RF3052:
  6062. case RF3053:
  6063. case RF3070:
  6064. case RF3290:
  6065. case RF3320:
  6066. case RF3322:
  6067. case RF5360:
  6068. case RF5362:
  6069. case RF5370:
  6070. case RF5372:
  6071. case RF5390:
  6072. case RF5392:
  6073. case RF5592:
  6074. break;
  6075. default:
  6076. rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
  6077. rf);
  6078. return -ENODEV;
  6079. }
  6080. rt2x00_set_rf(rt2x00dev, rf);
  6081. /*
  6082. * Identify default antenna configuration.
  6083. */
  6084. rt2x00dev->default_ant.tx_chain_num =
  6085. rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
  6086. rt2x00dev->default_ant.rx_chain_num =
  6087. rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
  6088. rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
  6089. if (rt2x00_rt(rt2x00dev, RT3070) ||
  6090. rt2x00_rt(rt2x00dev, RT3090) ||
  6091. rt2x00_rt(rt2x00dev, RT3352) ||
  6092. rt2x00_rt(rt2x00dev, RT3390)) {
  6093. value = rt2x00_get_field16(eeprom,
  6094. EEPROM_NIC_CONF1_ANT_DIVERSITY);
  6095. switch (value) {
  6096. case 0:
  6097. case 1:
  6098. case 2:
  6099. rt2x00dev->default_ant.tx = ANTENNA_A;
  6100. rt2x00dev->default_ant.rx = ANTENNA_A;
  6101. break;
  6102. case 3:
  6103. rt2x00dev->default_ant.tx = ANTENNA_A;
  6104. rt2x00dev->default_ant.rx = ANTENNA_B;
  6105. break;
  6106. }
  6107. } else {
  6108. rt2x00dev->default_ant.tx = ANTENNA_A;
  6109. rt2x00dev->default_ant.rx = ANTENNA_A;
  6110. }
  6111. if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
  6112. rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
  6113. rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
  6114. }
  6115. /*
  6116. * Determine external LNA informations.
  6117. */
  6118. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
  6119. __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
  6120. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
  6121. __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
  6122. /*
  6123. * Detect if this device has an hardware controlled radio.
  6124. */
  6125. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
  6126. __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
  6127. /*
  6128. * Detect if this device has Bluetooth co-existence.
  6129. */
  6130. if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
  6131. __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
  6132. /*
  6133. * Read frequency offset and RF programming sequence.
  6134. */
  6135. rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
  6136. rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
  6137. /*
  6138. * Store led settings, for correct led behaviour.
  6139. */
  6140. #ifdef CONFIG_RT2X00_LIB_LEDS
  6141. rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
  6142. rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
  6143. rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
  6144. rt2x00dev->led_mcu_reg = eeprom;
  6145. #endif /* CONFIG_RT2X00_LIB_LEDS */
  6146. /*
  6147. * Check if support EIRP tx power limit feature.
  6148. */
  6149. rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
  6150. if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
  6151. EIRP_MAX_TX_POWER_LIMIT)
  6152. __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
  6153. return 0;
  6154. }
  6155. /*
  6156. * RF value list for rt28xx
  6157. * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
  6158. */
  6159. static const struct rf_channel rf_vals[] = {
  6160. { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
  6161. { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
  6162. { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
  6163. { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
  6164. { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
  6165. { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
  6166. { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
  6167. { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
  6168. { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
  6169. { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
  6170. { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
  6171. { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
  6172. { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
  6173. { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
  6174. /* 802.11 UNI / HyperLan 2 */
  6175. { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
  6176. { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
  6177. { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
  6178. { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
  6179. { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
  6180. { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
  6181. { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
  6182. { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
  6183. { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
  6184. { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
  6185. { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
  6186. { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
  6187. /* 802.11 HyperLan 2 */
  6188. { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
  6189. { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
  6190. { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
  6191. { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
  6192. { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
  6193. { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
  6194. { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
  6195. { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
  6196. { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
  6197. { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
  6198. { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
  6199. { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
  6200. { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
  6201. { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
  6202. { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
  6203. { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
  6204. /* 802.11 UNII */
  6205. { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
  6206. { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
  6207. { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
  6208. { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
  6209. { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
  6210. { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
  6211. { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
  6212. { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
  6213. { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
  6214. { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
  6215. { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
  6216. /* 802.11 Japan */
  6217. { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
  6218. { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
  6219. { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
  6220. { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
  6221. { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
  6222. { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
  6223. { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
  6224. };
  6225. /*
  6226. * RF value list for rt3xxx
  6227. * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
  6228. */
  6229. static const struct rf_channel rf_vals_3x[] = {
  6230. {1, 241, 2, 2 },
  6231. {2, 241, 2, 7 },
  6232. {3, 242, 2, 2 },
  6233. {4, 242, 2, 7 },
  6234. {5, 243, 2, 2 },
  6235. {6, 243, 2, 7 },
  6236. {7, 244, 2, 2 },
  6237. {8, 244, 2, 7 },
  6238. {9, 245, 2, 2 },
  6239. {10, 245, 2, 7 },
  6240. {11, 246, 2, 2 },
  6241. {12, 246, 2, 7 },
  6242. {13, 247, 2, 2 },
  6243. {14, 248, 2, 4 },
  6244. /* 802.11 UNI / HyperLan 2 */
  6245. {36, 0x56, 0, 4},
  6246. {38, 0x56, 0, 6},
  6247. {40, 0x56, 0, 8},
  6248. {44, 0x57, 0, 0},
  6249. {46, 0x57, 0, 2},
  6250. {48, 0x57, 0, 4},
  6251. {52, 0x57, 0, 8},
  6252. {54, 0x57, 0, 10},
  6253. {56, 0x58, 0, 0},
  6254. {60, 0x58, 0, 4},
  6255. {62, 0x58, 0, 6},
  6256. {64, 0x58, 0, 8},
  6257. /* 802.11 HyperLan 2 */
  6258. {100, 0x5b, 0, 8},
  6259. {102, 0x5b, 0, 10},
  6260. {104, 0x5c, 0, 0},
  6261. {108, 0x5c, 0, 4},
  6262. {110, 0x5c, 0, 6},
  6263. {112, 0x5c, 0, 8},
  6264. {116, 0x5d, 0, 0},
  6265. {118, 0x5d, 0, 2},
  6266. {120, 0x5d, 0, 4},
  6267. {124, 0x5d, 0, 8},
  6268. {126, 0x5d, 0, 10},
  6269. {128, 0x5e, 0, 0},
  6270. {132, 0x5e, 0, 4},
  6271. {134, 0x5e, 0, 6},
  6272. {136, 0x5e, 0, 8},
  6273. {140, 0x5f, 0, 0},
  6274. /* 802.11 UNII */
  6275. {149, 0x5f, 0, 9},
  6276. {151, 0x5f, 0, 11},
  6277. {153, 0x60, 0, 1},
  6278. {157, 0x60, 0, 5},
  6279. {159, 0x60, 0, 7},
  6280. {161, 0x60, 0, 9},
  6281. {165, 0x61, 0, 1},
  6282. {167, 0x61, 0, 3},
  6283. {169, 0x61, 0, 5},
  6284. {171, 0x61, 0, 7},
  6285. {173, 0x61, 0, 9},
  6286. };
  6287. static const struct rf_channel rf_vals_5592_xtal20[] = {
  6288. /* Channel, N, K, mod, R */
  6289. {1, 482, 4, 10, 3},
  6290. {2, 483, 4, 10, 3},
  6291. {3, 484, 4, 10, 3},
  6292. {4, 485, 4, 10, 3},
  6293. {5, 486, 4, 10, 3},
  6294. {6, 487, 4, 10, 3},
  6295. {7, 488, 4, 10, 3},
  6296. {8, 489, 4, 10, 3},
  6297. {9, 490, 4, 10, 3},
  6298. {10, 491, 4, 10, 3},
  6299. {11, 492, 4, 10, 3},
  6300. {12, 493, 4, 10, 3},
  6301. {13, 494, 4, 10, 3},
  6302. {14, 496, 8, 10, 3},
  6303. {36, 172, 8, 12, 1},
  6304. {38, 173, 0, 12, 1},
  6305. {40, 173, 4, 12, 1},
  6306. {42, 173, 8, 12, 1},
  6307. {44, 174, 0, 12, 1},
  6308. {46, 174, 4, 12, 1},
  6309. {48, 174, 8, 12, 1},
  6310. {50, 175, 0, 12, 1},
  6311. {52, 175, 4, 12, 1},
  6312. {54, 175, 8, 12, 1},
  6313. {56, 176, 0, 12, 1},
  6314. {58, 176, 4, 12, 1},
  6315. {60, 176, 8, 12, 1},
  6316. {62, 177, 0, 12, 1},
  6317. {64, 177, 4, 12, 1},
  6318. {100, 183, 4, 12, 1},
  6319. {102, 183, 8, 12, 1},
  6320. {104, 184, 0, 12, 1},
  6321. {106, 184, 4, 12, 1},
  6322. {108, 184, 8, 12, 1},
  6323. {110, 185, 0, 12, 1},
  6324. {112, 185, 4, 12, 1},
  6325. {114, 185, 8, 12, 1},
  6326. {116, 186, 0, 12, 1},
  6327. {118, 186, 4, 12, 1},
  6328. {120, 186, 8, 12, 1},
  6329. {122, 187, 0, 12, 1},
  6330. {124, 187, 4, 12, 1},
  6331. {126, 187, 8, 12, 1},
  6332. {128, 188, 0, 12, 1},
  6333. {130, 188, 4, 12, 1},
  6334. {132, 188, 8, 12, 1},
  6335. {134, 189, 0, 12, 1},
  6336. {136, 189, 4, 12, 1},
  6337. {138, 189, 8, 12, 1},
  6338. {140, 190, 0, 12, 1},
  6339. {149, 191, 6, 12, 1},
  6340. {151, 191, 10, 12, 1},
  6341. {153, 192, 2, 12, 1},
  6342. {155, 192, 6, 12, 1},
  6343. {157, 192, 10, 12, 1},
  6344. {159, 193, 2, 12, 1},
  6345. {161, 193, 6, 12, 1},
  6346. {165, 194, 2, 12, 1},
  6347. {184, 164, 0, 12, 1},
  6348. {188, 164, 4, 12, 1},
  6349. {192, 165, 8, 12, 1},
  6350. {196, 166, 0, 12, 1},
  6351. };
  6352. static const struct rf_channel rf_vals_5592_xtal40[] = {
  6353. /* Channel, N, K, mod, R */
  6354. {1, 241, 2, 10, 3},
  6355. {2, 241, 7, 10, 3},
  6356. {3, 242, 2, 10, 3},
  6357. {4, 242, 7, 10, 3},
  6358. {5, 243, 2, 10, 3},
  6359. {6, 243, 7, 10, 3},
  6360. {7, 244, 2, 10, 3},
  6361. {8, 244, 7, 10, 3},
  6362. {9, 245, 2, 10, 3},
  6363. {10, 245, 7, 10, 3},
  6364. {11, 246, 2, 10, 3},
  6365. {12, 246, 7, 10, 3},
  6366. {13, 247, 2, 10, 3},
  6367. {14, 248, 4, 10, 3},
  6368. {36, 86, 4, 12, 1},
  6369. {38, 86, 6, 12, 1},
  6370. {40, 86, 8, 12, 1},
  6371. {42, 86, 10, 12, 1},
  6372. {44, 87, 0, 12, 1},
  6373. {46, 87, 2, 12, 1},
  6374. {48, 87, 4, 12, 1},
  6375. {50, 87, 6, 12, 1},
  6376. {52, 87, 8, 12, 1},
  6377. {54, 87, 10, 12, 1},
  6378. {56, 88, 0, 12, 1},
  6379. {58, 88, 2, 12, 1},
  6380. {60, 88, 4, 12, 1},
  6381. {62, 88, 6, 12, 1},
  6382. {64, 88, 8, 12, 1},
  6383. {100, 91, 8, 12, 1},
  6384. {102, 91, 10, 12, 1},
  6385. {104, 92, 0, 12, 1},
  6386. {106, 92, 2, 12, 1},
  6387. {108, 92, 4, 12, 1},
  6388. {110, 92, 6, 12, 1},
  6389. {112, 92, 8, 12, 1},
  6390. {114, 92, 10, 12, 1},
  6391. {116, 93, 0, 12, 1},
  6392. {118, 93, 2, 12, 1},
  6393. {120, 93, 4, 12, 1},
  6394. {122, 93, 6, 12, 1},
  6395. {124, 93, 8, 12, 1},
  6396. {126, 93, 10, 12, 1},
  6397. {128, 94, 0, 12, 1},
  6398. {130, 94, 2, 12, 1},
  6399. {132, 94, 4, 12, 1},
  6400. {134, 94, 6, 12, 1},
  6401. {136, 94, 8, 12, 1},
  6402. {138, 94, 10, 12, 1},
  6403. {140, 95, 0, 12, 1},
  6404. {149, 95, 9, 12, 1},
  6405. {151, 95, 11, 12, 1},
  6406. {153, 96, 1, 12, 1},
  6407. {155, 96, 3, 12, 1},
  6408. {157, 96, 5, 12, 1},
  6409. {159, 96, 7, 12, 1},
  6410. {161, 96, 9, 12, 1},
  6411. {165, 97, 1, 12, 1},
  6412. {184, 82, 0, 12, 1},
  6413. {188, 82, 4, 12, 1},
  6414. {192, 82, 8, 12, 1},
  6415. {196, 83, 0, 12, 1},
  6416. };
  6417. static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
  6418. {
  6419. struct hw_mode_spec *spec = &rt2x00dev->spec;
  6420. struct channel_info *info;
  6421. char *default_power1;
  6422. char *default_power2;
  6423. char *default_power3;
  6424. unsigned int i;
  6425. u32 reg;
  6426. /*
  6427. * Disable powersaving as default.
  6428. */
  6429. rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  6430. /*
  6431. * Initialize all hw fields.
  6432. */
  6433. ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_HT_CCK_RATES);
  6434. ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
  6435. ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
  6436. ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
  6437. ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
  6438. ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
  6439. /*
  6440. * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
  6441. * unless we are capable of sending the buffered frames out after the
  6442. * DTIM transmission using rt2x00lib_beacondone. This will send out
  6443. * multicast and broadcast traffic immediately instead of buffering it
  6444. * infinitly and thus dropping it after some time.
  6445. */
  6446. if (!rt2x00_is_usb(rt2x00dev))
  6447. ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
  6448. SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
  6449. SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
  6450. rt2800_eeprom_addr(rt2x00dev,
  6451. EEPROM_MAC_ADDR_0));
  6452. /*
  6453. * As rt2800 has a global fallback table we cannot specify
  6454. * more then one tx rate per frame but since the hw will
  6455. * try several rates (based on the fallback table) we should
  6456. * initialize max_report_rates to the maximum number of rates
  6457. * we are going to try. Otherwise mac80211 will truncate our
  6458. * reported tx rates and the rc algortihm will end up with
  6459. * incorrect data.
  6460. */
  6461. rt2x00dev->hw->max_rates = 1;
  6462. rt2x00dev->hw->max_report_rates = 7;
  6463. rt2x00dev->hw->max_rate_tries = 1;
  6464. /*
  6465. * Initialize hw_mode information.
  6466. */
  6467. spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
  6468. switch (rt2x00dev->chip.rf) {
  6469. case RF2720:
  6470. case RF2820:
  6471. spec->num_channels = 14;
  6472. spec->channels = rf_vals;
  6473. break;
  6474. case RF2750:
  6475. case RF2850:
  6476. spec->num_channels = ARRAY_SIZE(rf_vals);
  6477. spec->channels = rf_vals;
  6478. break;
  6479. case RF2020:
  6480. case RF3020:
  6481. case RF3021:
  6482. case RF3022:
  6483. case RF3070:
  6484. case RF3290:
  6485. case RF3320:
  6486. case RF3322:
  6487. case RF5360:
  6488. case RF5362:
  6489. case RF5370:
  6490. case RF5372:
  6491. case RF5390:
  6492. case RF5392:
  6493. spec->num_channels = 14;
  6494. spec->channels = rf_vals_3x;
  6495. break;
  6496. case RF3052:
  6497. case RF3053:
  6498. spec->num_channels = ARRAY_SIZE(rf_vals_3x);
  6499. spec->channels = rf_vals_3x;
  6500. break;
  6501. case RF5592:
  6502. rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX, &reg);
  6503. if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
  6504. spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
  6505. spec->channels = rf_vals_5592_xtal40;
  6506. } else {
  6507. spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
  6508. spec->channels = rf_vals_5592_xtal20;
  6509. }
  6510. break;
  6511. }
  6512. if (WARN_ON_ONCE(!spec->channels))
  6513. return -ENODEV;
  6514. spec->supported_bands = SUPPORT_BAND_2GHZ;
  6515. if (spec->num_channels > 14)
  6516. spec->supported_bands |= SUPPORT_BAND_5GHZ;
  6517. /*
  6518. * Initialize HT information.
  6519. */
  6520. if (!rt2x00_rf(rt2x00dev, RF2020))
  6521. spec->ht.ht_supported = true;
  6522. else
  6523. spec->ht.ht_supported = false;
  6524. spec->ht.cap =
  6525. IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
  6526. IEEE80211_HT_CAP_GRN_FLD |
  6527. IEEE80211_HT_CAP_SGI_20 |
  6528. IEEE80211_HT_CAP_SGI_40;
  6529. if (rt2x00dev->default_ant.tx_chain_num >= 2)
  6530. spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
  6531. spec->ht.cap |= rt2x00dev->default_ant.rx_chain_num <<
  6532. IEEE80211_HT_CAP_RX_STBC_SHIFT;
  6533. spec->ht.ampdu_factor = 3;
  6534. spec->ht.ampdu_density = 4;
  6535. spec->ht.mcs.tx_params =
  6536. IEEE80211_HT_MCS_TX_DEFINED |
  6537. IEEE80211_HT_MCS_TX_RX_DIFF |
  6538. ((rt2x00dev->default_ant.tx_chain_num - 1) <<
  6539. IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
  6540. switch (rt2x00dev->default_ant.rx_chain_num) {
  6541. case 3:
  6542. spec->ht.mcs.rx_mask[2] = 0xff;
  6543. case 2:
  6544. spec->ht.mcs.rx_mask[1] = 0xff;
  6545. case 1:
  6546. spec->ht.mcs.rx_mask[0] = 0xff;
  6547. spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
  6548. break;
  6549. }
  6550. /*
  6551. * Create channel information array
  6552. */
  6553. info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
  6554. if (!info)
  6555. return -ENOMEM;
  6556. spec->channels_info = info;
  6557. default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
  6558. default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
  6559. if (rt2x00dev->default_ant.tx_chain_num > 2)
  6560. default_power3 = rt2800_eeprom_addr(rt2x00dev,
  6561. EEPROM_EXT_TXPOWER_BG3);
  6562. else
  6563. default_power3 = NULL;
  6564. for (i = 0; i < 14; i++) {
  6565. info[i].default_power1 = default_power1[i];
  6566. info[i].default_power2 = default_power2[i];
  6567. if (default_power3)
  6568. info[i].default_power3 = default_power3[i];
  6569. }
  6570. if (spec->num_channels > 14) {
  6571. default_power1 = rt2800_eeprom_addr(rt2x00dev,
  6572. EEPROM_TXPOWER_A1);
  6573. default_power2 = rt2800_eeprom_addr(rt2x00dev,
  6574. EEPROM_TXPOWER_A2);
  6575. if (rt2x00dev->default_ant.tx_chain_num > 2)
  6576. default_power3 =
  6577. rt2800_eeprom_addr(rt2x00dev,
  6578. EEPROM_EXT_TXPOWER_A3);
  6579. else
  6580. default_power3 = NULL;
  6581. for (i = 14; i < spec->num_channels; i++) {
  6582. info[i].default_power1 = default_power1[i - 14];
  6583. info[i].default_power2 = default_power2[i - 14];
  6584. if (default_power3)
  6585. info[i].default_power3 = default_power3[i - 14];
  6586. }
  6587. }
  6588. switch (rt2x00dev->chip.rf) {
  6589. case RF2020:
  6590. case RF3020:
  6591. case RF3021:
  6592. case RF3022:
  6593. case RF3320:
  6594. case RF3052:
  6595. case RF3053:
  6596. case RF3070:
  6597. case RF3290:
  6598. case RF5360:
  6599. case RF5362:
  6600. case RF5370:
  6601. case RF5372:
  6602. case RF5390:
  6603. case RF5392:
  6604. __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
  6605. break;
  6606. }
  6607. return 0;
  6608. }
  6609. static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
  6610. {
  6611. u32 reg;
  6612. u32 rt;
  6613. u32 rev;
  6614. if (rt2x00_rt(rt2x00dev, RT3290))
  6615. rt2800_register_read(rt2x00dev, MAC_CSR0_3290, &reg);
  6616. else
  6617. rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
  6618. rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
  6619. rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
  6620. switch (rt) {
  6621. case RT2860:
  6622. case RT2872:
  6623. case RT2883:
  6624. case RT3070:
  6625. case RT3071:
  6626. case RT3090:
  6627. case RT3290:
  6628. case RT3352:
  6629. case RT3390:
  6630. case RT3572:
  6631. case RT3593:
  6632. case RT5390:
  6633. case RT5392:
  6634. case RT5592:
  6635. break;
  6636. default:
  6637. rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
  6638. rt, rev);
  6639. return -ENODEV;
  6640. }
  6641. rt2x00_set_rt(rt2x00dev, rt, rev);
  6642. return 0;
  6643. }
  6644. int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
  6645. {
  6646. int retval;
  6647. u32 reg;
  6648. retval = rt2800_probe_rt(rt2x00dev);
  6649. if (retval)
  6650. return retval;
  6651. /*
  6652. * Allocate eeprom data.
  6653. */
  6654. retval = rt2800_validate_eeprom(rt2x00dev);
  6655. if (retval)
  6656. return retval;
  6657. retval = rt2800_init_eeprom(rt2x00dev);
  6658. if (retval)
  6659. return retval;
  6660. /*
  6661. * Enable rfkill polling by setting GPIO direction of the
  6662. * rfkill switch GPIO pin correctly.
  6663. */
  6664. rt2800_register_read(rt2x00dev, GPIO_CTRL, &reg);
  6665. rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
  6666. rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
  6667. /*
  6668. * Initialize hw specifications.
  6669. */
  6670. retval = rt2800_probe_hw_mode(rt2x00dev);
  6671. if (retval)
  6672. return retval;
  6673. /*
  6674. * Set device capabilities.
  6675. */
  6676. __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
  6677. __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
  6678. if (!rt2x00_is_usb(rt2x00dev))
  6679. __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
  6680. /*
  6681. * Set device requirements.
  6682. */
  6683. if (!rt2x00_is_soc(rt2x00dev))
  6684. __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
  6685. __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
  6686. __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
  6687. if (!rt2800_hwcrypt_disabled(rt2x00dev))
  6688. __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
  6689. __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
  6690. __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
  6691. if (rt2x00_is_usb(rt2x00dev))
  6692. __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
  6693. else {
  6694. __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
  6695. __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
  6696. }
  6697. /*
  6698. * Set the rssi offset.
  6699. */
  6700. rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
  6701. return 0;
  6702. }
  6703. EXPORT_SYMBOL_GPL(rt2800_probe_hw);
  6704. /*
  6705. * IEEE80211 stack callback functions.
  6706. */
  6707. void rt2800_get_key_seq(struct ieee80211_hw *hw,
  6708. struct ieee80211_key_conf *key,
  6709. struct ieee80211_key_seq *seq)
  6710. {
  6711. struct rt2x00_dev *rt2x00dev = hw->priv;
  6712. struct mac_iveiv_entry iveiv_entry;
  6713. u32 offset;
  6714. if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
  6715. return;
  6716. offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
  6717. rt2800_register_multiread(rt2x00dev, offset,
  6718. &iveiv_entry, sizeof(iveiv_entry));
  6719. memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
  6720. memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
  6721. }
  6722. EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
  6723. int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
  6724. {
  6725. struct rt2x00_dev *rt2x00dev = hw->priv;
  6726. u32 reg;
  6727. bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
  6728. rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
  6729. rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
  6730. rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
  6731. rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
  6732. rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
  6733. rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
  6734. rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
  6735. rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
  6736. rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
  6737. rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
  6738. rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
  6739. rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
  6740. rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
  6741. rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
  6742. rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
  6743. rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
  6744. rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
  6745. rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
  6746. rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
  6747. rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
  6748. rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
  6749. return 0;
  6750. }
  6751. EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
  6752. int rt2800_conf_tx(struct ieee80211_hw *hw,
  6753. struct ieee80211_vif *vif, u16 queue_idx,
  6754. const struct ieee80211_tx_queue_params *params)
  6755. {
  6756. struct rt2x00_dev *rt2x00dev = hw->priv;
  6757. struct data_queue *queue;
  6758. struct rt2x00_field32 field;
  6759. int retval;
  6760. u32 reg;
  6761. u32 offset;
  6762. /*
  6763. * First pass the configuration through rt2x00lib, that will
  6764. * update the queue settings and validate the input. After that
  6765. * we are free to update the registers based on the value
  6766. * in the queue parameter.
  6767. */
  6768. retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
  6769. if (retval)
  6770. return retval;
  6771. /*
  6772. * We only need to perform additional register initialization
  6773. * for WMM queues/
  6774. */
  6775. if (queue_idx >= 4)
  6776. return 0;
  6777. queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
  6778. /* Update WMM TXOP register */
  6779. offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
  6780. field.bit_offset = (queue_idx & 1) * 16;
  6781. field.bit_mask = 0xffff << field.bit_offset;
  6782. rt2800_register_read(rt2x00dev, offset, &reg);
  6783. rt2x00_set_field32(&reg, field, queue->txop);
  6784. rt2800_register_write(rt2x00dev, offset, reg);
  6785. /* Update WMM registers */
  6786. field.bit_offset = queue_idx * 4;
  6787. field.bit_mask = 0xf << field.bit_offset;
  6788. rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
  6789. rt2x00_set_field32(&reg, field, queue->aifs);
  6790. rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
  6791. rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
  6792. rt2x00_set_field32(&reg, field, queue->cw_min);
  6793. rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
  6794. rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
  6795. rt2x00_set_field32(&reg, field, queue->cw_max);
  6796. rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
  6797. /* Update EDCA registers */
  6798. offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
  6799. rt2800_register_read(rt2x00dev, offset, &reg);
  6800. rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
  6801. rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
  6802. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
  6803. rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
  6804. rt2800_register_write(rt2x00dev, offset, reg);
  6805. return 0;
  6806. }
  6807. EXPORT_SYMBOL_GPL(rt2800_conf_tx);
  6808. u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
  6809. {
  6810. struct rt2x00_dev *rt2x00dev = hw->priv;
  6811. u64 tsf;
  6812. u32 reg;
  6813. rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
  6814. tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
  6815. rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
  6816. tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
  6817. return tsf;
  6818. }
  6819. EXPORT_SYMBOL_GPL(rt2800_get_tsf);
  6820. int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
  6821. enum ieee80211_ampdu_mlme_action action,
  6822. struct ieee80211_sta *sta, u16 tid, u16 *ssn,
  6823. u8 buf_size)
  6824. {
  6825. struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
  6826. int ret = 0;
  6827. /*
  6828. * Don't allow aggregation for stations the hardware isn't aware
  6829. * of because tx status reports for frames to an unknown station
  6830. * always contain wcid=WCID_END+1 and thus we can't distinguish
  6831. * between multiple stations which leads to unwanted situations
  6832. * when the hw reorders frames due to aggregation.
  6833. */
  6834. if (sta_priv->wcid > WCID_END)
  6835. return 1;
  6836. switch (action) {
  6837. case IEEE80211_AMPDU_RX_START:
  6838. case IEEE80211_AMPDU_RX_STOP:
  6839. /*
  6840. * The hw itself takes care of setting up BlockAck mechanisms.
  6841. * So, we only have to allow mac80211 to nagotiate a BlockAck
  6842. * agreement. Once that is done, the hw will BlockAck incoming
  6843. * AMPDUs without further setup.
  6844. */
  6845. break;
  6846. case IEEE80211_AMPDU_TX_START:
  6847. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  6848. break;
  6849. case IEEE80211_AMPDU_TX_STOP_CONT:
  6850. case IEEE80211_AMPDU_TX_STOP_FLUSH:
  6851. case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
  6852. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  6853. break;
  6854. case IEEE80211_AMPDU_TX_OPERATIONAL:
  6855. break;
  6856. default:
  6857. rt2x00_warn((struct rt2x00_dev *)hw->priv,
  6858. "Unknown AMPDU action\n");
  6859. }
  6860. return ret;
  6861. }
  6862. EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
  6863. int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
  6864. struct survey_info *survey)
  6865. {
  6866. struct rt2x00_dev *rt2x00dev = hw->priv;
  6867. struct ieee80211_conf *conf = &hw->conf;
  6868. u32 idle, busy, busy_ext;
  6869. if (idx != 0)
  6870. return -ENOENT;
  6871. survey->channel = conf->chandef.chan;
  6872. rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
  6873. rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
  6874. rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
  6875. if (idle || busy) {
  6876. survey->filled = SURVEY_INFO_TIME |
  6877. SURVEY_INFO_TIME_BUSY |
  6878. SURVEY_INFO_TIME_EXT_BUSY;
  6879. survey->time = (idle + busy) / 1000;
  6880. survey->time_busy = busy / 1000;
  6881. survey->time_ext_busy = busy_ext / 1000;
  6882. }
  6883. if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
  6884. survey->filled |= SURVEY_INFO_IN_USE;
  6885. return 0;
  6886. }
  6887. EXPORT_SYMBOL_GPL(rt2800_get_survey);
  6888. MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
  6889. MODULE_VERSION(DRV_VERSION);
  6890. MODULE_DESCRIPTION("Ralink RT2800 library");
  6891. MODULE_LICENSE("GPL");