fw.c 33 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23. * USA
  24. *
  25. * The full GNU General Public License is included in this distribution
  26. * in the file called COPYING.
  27. *
  28. * Contact Information:
  29. * Intel Linux Wireless <ilw@linux.intel.com>
  30. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31. *
  32. * BSD LICENSE
  33. *
  34. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  35. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  36. * All rights reserved.
  37. *
  38. * Redistribution and use in source and binary forms, with or without
  39. * modification, are permitted provided that the following conditions
  40. * are met:
  41. *
  42. * * Redistributions of source code must retain the above copyright
  43. * notice, this list of conditions and the following disclaimer.
  44. * * Redistributions in binary form must reproduce the above copyright
  45. * notice, this list of conditions and the following disclaimer in
  46. * the documentation and/or other materials provided with the
  47. * distribution.
  48. * * Neither the name Intel Corporation nor the names of its
  49. * contributors may be used to endorse or promote products derived
  50. * from this software without specific prior written permission.
  51. *
  52. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63. *
  64. *****************************************************************************/
  65. #include <net/mac80211.h>
  66. #include "iwl-trans.h"
  67. #include "iwl-op-mode.h"
  68. #include "iwl-fw.h"
  69. #include "iwl-debug.h"
  70. #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
  71. #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
  72. #include "iwl-prph.h"
  73. #include "iwl-eeprom-parse.h"
  74. #include "mvm.h"
  75. #include "iwl-phy-db.h"
  76. #define MVM_UCODE_ALIVE_TIMEOUT HZ
  77. #define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
  78. #define UCODE_VALID_OK cpu_to_le32(0x1)
  79. struct iwl_mvm_alive_data {
  80. bool valid;
  81. u32 scd_base_addr;
  82. };
  83. static inline const struct fw_img *
  84. iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type)
  85. {
  86. if (ucode_type >= IWL_UCODE_TYPE_MAX)
  87. return NULL;
  88. return &mvm->fw->img[ucode_type];
  89. }
  90. static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
  91. {
  92. struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
  93. .valid = cpu_to_le32(valid_tx_ant),
  94. };
  95. IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
  96. return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
  97. sizeof(tx_ant_cmd), &tx_ant_cmd);
  98. }
  99. static void iwl_free_fw_paging(struct iwl_mvm *mvm)
  100. {
  101. int i;
  102. if (!mvm->fw_paging_db[0].fw_paging_block)
  103. return;
  104. for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
  105. if (!mvm->fw_paging_db[i].fw_paging_block) {
  106. IWL_DEBUG_FW(mvm,
  107. "Paging: block %d already freed, continue to next page\n",
  108. i);
  109. continue;
  110. }
  111. __free_pages(mvm->fw_paging_db[i].fw_paging_block,
  112. get_order(mvm->fw_paging_db[i].fw_paging_size));
  113. }
  114. kfree(mvm->trans->paging_download_buf);
  115. memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
  116. }
  117. static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
  118. {
  119. int sec_idx, idx;
  120. u32 offset = 0;
  121. /*
  122. * find where is the paging image start point:
  123. * if CPU2 exist and it's in paging format, then the image looks like:
  124. * CPU1 sections (2 or more)
  125. * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
  126. * CPU2 sections (not paged)
  127. * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
  128. * non paged to CPU2 paging sec
  129. * CPU2 paging CSS
  130. * CPU2 paging image (including instruction and data)
  131. */
  132. for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
  133. if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
  134. sec_idx++;
  135. break;
  136. }
  137. }
  138. if (sec_idx >= IWL_UCODE_SECTION_MAX) {
  139. IWL_ERR(mvm, "driver didn't find paging image\n");
  140. iwl_free_fw_paging(mvm);
  141. return -EINVAL;
  142. }
  143. /* copy the CSS block to the dram */
  144. IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
  145. sec_idx);
  146. memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
  147. image->sec[sec_idx].data,
  148. mvm->fw_paging_db[0].fw_paging_size);
  149. IWL_DEBUG_FW(mvm,
  150. "Paging: copied %d CSS bytes to first block\n",
  151. mvm->fw_paging_db[0].fw_paging_size);
  152. sec_idx++;
  153. /*
  154. * copy the paging blocks to the dram
  155. * loop index start from 1 since that CSS block already copied to dram
  156. * and CSS index is 0.
  157. * loop stop at num_of_paging_blk since that last block is not full.
  158. */
  159. for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
  160. memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
  161. image->sec[sec_idx].data + offset,
  162. mvm->fw_paging_db[idx].fw_paging_size);
  163. IWL_DEBUG_FW(mvm,
  164. "Paging: copied %d paging bytes to block %d\n",
  165. mvm->fw_paging_db[idx].fw_paging_size,
  166. idx);
  167. offset += mvm->fw_paging_db[idx].fw_paging_size;
  168. }
  169. /* copy the last paging block */
  170. if (mvm->num_of_pages_in_last_blk > 0) {
  171. memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
  172. image->sec[sec_idx].data + offset,
  173. FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
  174. IWL_DEBUG_FW(mvm,
  175. "Paging: copied %d pages in the last block %d\n",
  176. mvm->num_of_pages_in_last_blk, idx);
  177. }
  178. return 0;
  179. }
  180. static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
  181. const struct fw_img *image)
  182. {
  183. struct page *block;
  184. dma_addr_t phys = 0;
  185. int blk_idx = 0;
  186. int order, num_of_pages;
  187. int dma_enabled;
  188. if (mvm->fw_paging_db[0].fw_paging_block)
  189. return 0;
  190. dma_enabled = is_device_dma_capable(mvm->trans->dev);
  191. /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
  192. BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
  193. num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
  194. mvm->num_of_paging_blk = ((num_of_pages - 1) /
  195. NUM_OF_PAGE_PER_GROUP) + 1;
  196. mvm->num_of_pages_in_last_blk =
  197. num_of_pages -
  198. NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
  199. IWL_DEBUG_FW(mvm,
  200. "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
  201. mvm->num_of_paging_blk,
  202. mvm->num_of_pages_in_last_blk);
  203. /* allocate block of 4Kbytes for paging CSS */
  204. order = get_order(FW_PAGING_SIZE);
  205. block = alloc_pages(GFP_KERNEL, order);
  206. if (!block) {
  207. /* free all the previous pages since we failed */
  208. iwl_free_fw_paging(mvm);
  209. return -ENOMEM;
  210. }
  211. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  212. mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
  213. if (dma_enabled) {
  214. phys = dma_map_page(mvm->trans->dev, block, 0,
  215. PAGE_SIZE << order, DMA_BIDIRECTIONAL);
  216. if (dma_mapping_error(mvm->trans->dev, phys)) {
  217. /*
  218. * free the previous pages and the current one since
  219. * we failed to map_page.
  220. */
  221. iwl_free_fw_paging(mvm);
  222. return -ENOMEM;
  223. }
  224. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  225. } else {
  226. mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG |
  227. blk_idx << BLOCK_2_EXP_SIZE;
  228. }
  229. IWL_DEBUG_FW(mvm,
  230. "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
  231. order);
  232. /*
  233. * allocate blocks in dram.
  234. * since that CSS allocated in fw_paging_db[0] loop start from index 1
  235. */
  236. for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  237. /* allocate block of PAGING_BLOCK_SIZE (32K) */
  238. order = get_order(PAGING_BLOCK_SIZE);
  239. block = alloc_pages(GFP_KERNEL, order);
  240. if (!block) {
  241. /* free all the previous pages since we failed */
  242. iwl_free_fw_paging(mvm);
  243. return -ENOMEM;
  244. }
  245. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  246. mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
  247. if (dma_enabled) {
  248. phys = dma_map_page(mvm->trans->dev, block, 0,
  249. PAGE_SIZE << order,
  250. DMA_BIDIRECTIONAL);
  251. if (dma_mapping_error(mvm->trans->dev, phys)) {
  252. /*
  253. * free the previous pages and the current one
  254. * since we failed to map_page.
  255. */
  256. iwl_free_fw_paging(mvm);
  257. return -ENOMEM;
  258. }
  259. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  260. } else {
  261. mvm->fw_paging_db[blk_idx].fw_paging_phys =
  262. PAGING_ADDR_SIG |
  263. blk_idx << BLOCK_2_EXP_SIZE;
  264. }
  265. IWL_DEBUG_FW(mvm,
  266. "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
  267. order);
  268. }
  269. return 0;
  270. }
  271. static int iwl_save_fw_paging(struct iwl_mvm *mvm,
  272. const struct fw_img *fw)
  273. {
  274. int ret;
  275. ret = iwl_alloc_fw_paging_mem(mvm, fw);
  276. if (ret)
  277. return ret;
  278. return iwl_fill_paging_mem(mvm, fw);
  279. }
  280. /* send paging cmd to FW in case CPU2 has paging image */
  281. static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
  282. {
  283. int blk_idx;
  284. __le32 dev_phy_addr;
  285. struct iwl_fw_paging_cmd fw_paging_cmd = {
  286. .flags =
  287. cpu_to_le32(PAGING_CMD_IS_SECURED |
  288. PAGING_CMD_IS_ENABLED |
  289. (mvm->num_of_pages_in_last_blk <<
  290. PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
  291. .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
  292. .block_num = cpu_to_le32(mvm->num_of_paging_blk),
  293. };
  294. /* loop for for all paging blocks + CSS block */
  295. for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  296. dev_phy_addr =
  297. cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >>
  298. PAGE_2_EXP_SIZE);
  299. fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr;
  300. }
  301. return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
  302. IWL_ALWAYS_LONG_GROUP, 0),
  303. 0, sizeof(fw_paging_cmd), &fw_paging_cmd);
  304. }
  305. /*
  306. * Send paging item cmd to FW in case CPU2 has paging image
  307. */
  308. static int iwl_trans_get_paging_item(struct iwl_mvm *mvm)
  309. {
  310. int ret;
  311. struct iwl_fw_get_item_cmd fw_get_item_cmd = {
  312. .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING),
  313. };
  314. struct iwl_fw_get_item_resp *item_resp;
  315. struct iwl_host_cmd cmd = {
  316. .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0),
  317. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  318. .data = { &fw_get_item_cmd, },
  319. };
  320. cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd);
  321. ret = iwl_mvm_send_cmd(mvm, &cmd);
  322. if (ret) {
  323. IWL_ERR(mvm,
  324. "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n",
  325. ret);
  326. return ret;
  327. }
  328. item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data;
  329. if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) {
  330. IWL_ERR(mvm,
  331. "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n",
  332. le32_to_cpu(item_resp->item_id));
  333. ret = -EIO;
  334. goto exit;
  335. }
  336. mvm->trans->paging_download_buf = kzalloc(MAX_PAGING_IMAGE_SIZE,
  337. GFP_KERNEL);
  338. if (!mvm->trans->paging_download_buf) {
  339. ret = -ENOMEM;
  340. goto exit;
  341. }
  342. mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val);
  343. mvm->trans->paging_db = mvm->fw_paging_db;
  344. IWL_DEBUG_FW(mvm,
  345. "Paging: got paging request address (paging_req_addr 0x%08x)\n",
  346. mvm->trans->paging_req_addr);
  347. exit:
  348. iwl_free_resp(&cmd);
  349. return ret;
  350. }
  351. static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
  352. struct iwl_rx_packet *pkt, void *data)
  353. {
  354. struct iwl_mvm *mvm =
  355. container_of(notif_wait, struct iwl_mvm, notif_wait);
  356. struct iwl_mvm_alive_data *alive_data = data;
  357. struct mvm_alive_resp_ver1 *palive1;
  358. struct mvm_alive_resp_ver2 *palive2;
  359. struct mvm_alive_resp *palive;
  360. if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
  361. palive1 = (void *)pkt->data;
  362. mvm->support_umac_log = false;
  363. mvm->error_event_table =
  364. le32_to_cpu(palive1->error_event_table_ptr);
  365. mvm->log_event_table =
  366. le32_to_cpu(palive1->log_event_table_ptr);
  367. alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
  368. alive_data->valid = le16_to_cpu(palive1->status) ==
  369. IWL_ALIVE_STATUS_OK;
  370. IWL_DEBUG_FW(mvm,
  371. "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  372. le16_to_cpu(palive1->status), palive1->ver_type,
  373. palive1->ver_subtype, palive1->flags);
  374. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
  375. palive2 = (void *)pkt->data;
  376. mvm->error_event_table =
  377. le32_to_cpu(palive2->error_event_table_ptr);
  378. mvm->log_event_table =
  379. le32_to_cpu(palive2->log_event_table_ptr);
  380. alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
  381. mvm->umac_error_event_table =
  382. le32_to_cpu(palive2->error_info_addr);
  383. mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
  384. mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
  385. alive_data->valid = le16_to_cpu(palive2->status) ==
  386. IWL_ALIVE_STATUS_OK;
  387. if (mvm->umac_error_event_table)
  388. mvm->support_umac_log = true;
  389. IWL_DEBUG_FW(mvm,
  390. "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  391. le16_to_cpu(palive2->status), palive2->ver_type,
  392. palive2->ver_subtype, palive2->flags);
  393. IWL_DEBUG_FW(mvm,
  394. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  395. palive2->umac_major, palive2->umac_minor);
  396. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
  397. palive = (void *)pkt->data;
  398. mvm->error_event_table =
  399. le32_to_cpu(palive->error_event_table_ptr);
  400. mvm->log_event_table =
  401. le32_to_cpu(palive->log_event_table_ptr);
  402. alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
  403. mvm->umac_error_event_table =
  404. le32_to_cpu(palive->error_info_addr);
  405. mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
  406. mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
  407. alive_data->valid = le16_to_cpu(palive->status) ==
  408. IWL_ALIVE_STATUS_OK;
  409. if (mvm->umac_error_event_table)
  410. mvm->support_umac_log = true;
  411. IWL_DEBUG_FW(mvm,
  412. "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  413. le16_to_cpu(palive->status), palive->ver_type,
  414. palive->ver_subtype, palive->flags);
  415. IWL_DEBUG_FW(mvm,
  416. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  417. le32_to_cpu(palive->umac_major),
  418. le32_to_cpu(palive->umac_minor));
  419. }
  420. return true;
  421. }
  422. static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
  423. struct iwl_rx_packet *pkt, void *data)
  424. {
  425. struct iwl_phy_db *phy_db = data;
  426. if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
  427. WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
  428. return true;
  429. }
  430. WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC));
  431. return false;
  432. }
  433. static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
  434. enum iwl_ucode_type ucode_type)
  435. {
  436. struct iwl_notification_wait alive_wait;
  437. struct iwl_mvm_alive_data alive_data;
  438. const struct fw_img *fw;
  439. int ret, i;
  440. enum iwl_ucode_type old_type = mvm->cur_ucode;
  441. static const u16 alive_cmd[] = { MVM_ALIVE };
  442. struct iwl_sf_region st_fwrd_space;
  443. if (ucode_type == IWL_UCODE_REGULAR &&
  444. iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE))
  445. fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER);
  446. else
  447. fw = iwl_get_ucode_image(mvm, ucode_type);
  448. if (WARN_ON(!fw))
  449. return -EINVAL;
  450. mvm->cur_ucode = ucode_type;
  451. mvm->ucode_loaded = false;
  452. iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
  453. alive_cmd, ARRAY_SIZE(alive_cmd),
  454. iwl_alive_fn, &alive_data);
  455. ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
  456. if (ret) {
  457. mvm->cur_ucode = old_type;
  458. iwl_remove_notification(&mvm->notif_wait, &alive_wait);
  459. return ret;
  460. }
  461. /*
  462. * Some things may run in the background now, but we
  463. * just wait for the ALIVE notification here.
  464. */
  465. ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
  466. MVM_UCODE_ALIVE_TIMEOUT);
  467. if (ret) {
  468. if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
  469. IWL_ERR(mvm,
  470. "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
  471. iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
  472. iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
  473. mvm->cur_ucode = old_type;
  474. return ret;
  475. }
  476. if (!alive_data.valid) {
  477. IWL_ERR(mvm, "Loaded ucode is not valid!\n");
  478. mvm->cur_ucode = old_type;
  479. return -EIO;
  480. }
  481. /*
  482. * update the sdio allocation according to the pointer we get in the
  483. * alive notification.
  484. */
  485. st_fwrd_space.addr = mvm->sf_space.addr;
  486. st_fwrd_space.size = mvm->sf_space.size;
  487. ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
  488. if (ret) {
  489. IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
  490. return ret;
  491. }
  492. iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
  493. /*
  494. * configure and operate fw paging mechanism.
  495. * driver configures the paging flow only once, CPU2 paging image
  496. * included in the IWL_UCODE_INIT image.
  497. */
  498. if (fw->paging_mem_size) {
  499. /*
  500. * When dma is not enabled, the driver needs to copy / write
  501. * the downloaded / uploaded page to / from the smem.
  502. * This gets the location of the place were the pages are
  503. * stored.
  504. */
  505. if (!is_device_dma_capable(mvm->trans->dev)) {
  506. ret = iwl_trans_get_paging_item(mvm);
  507. if (ret) {
  508. IWL_ERR(mvm, "failed to get FW paging item\n");
  509. return ret;
  510. }
  511. }
  512. ret = iwl_save_fw_paging(mvm, fw);
  513. if (ret) {
  514. IWL_ERR(mvm, "failed to save the FW paging image\n");
  515. return ret;
  516. }
  517. ret = iwl_send_paging_cmd(mvm, fw);
  518. if (ret) {
  519. IWL_ERR(mvm, "failed to send the paging cmd\n");
  520. iwl_free_fw_paging(mvm);
  521. return ret;
  522. }
  523. }
  524. /*
  525. * Note: all the queues are enabled as part of the interface
  526. * initialization, but in firmware restart scenarios they
  527. * could be stopped, so wake them up. In firmware restart,
  528. * mac80211 will have the queues stopped as well until the
  529. * reconfiguration completes. During normal startup, they
  530. * will be empty.
  531. */
  532. for (i = 0; i < IWL_MAX_HW_QUEUES; i++) {
  533. if (i < mvm->first_agg_queue && i != IWL_MVM_CMD_QUEUE)
  534. mvm->queue_to_mac80211[i] = i;
  535. else
  536. mvm->queue_to_mac80211[i] = IWL_INVALID_MAC80211_QUEUE;
  537. }
  538. for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
  539. atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
  540. mvm->ucode_loaded = true;
  541. return 0;
  542. }
  543. static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
  544. {
  545. struct iwl_phy_cfg_cmd phy_cfg_cmd;
  546. enum iwl_ucode_type ucode_type = mvm->cur_ucode;
  547. /* Set parameters */
  548. phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
  549. phy_cfg_cmd.calib_control.event_trigger =
  550. mvm->fw->default_calib[ucode_type].event_trigger;
  551. phy_cfg_cmd.calib_control.flow_trigger =
  552. mvm->fw->default_calib[ucode_type].flow_trigger;
  553. IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
  554. phy_cfg_cmd.phy_cfg);
  555. return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
  556. sizeof(phy_cfg_cmd), &phy_cfg_cmd);
  557. }
  558. int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
  559. {
  560. struct iwl_notification_wait calib_wait;
  561. static const u16 init_complete[] = {
  562. INIT_COMPLETE_NOTIF,
  563. CALIB_RES_NOTIF_PHY_DB
  564. };
  565. int ret;
  566. lockdep_assert_held(&mvm->mutex);
  567. if (WARN_ON_ONCE(mvm->calibrating))
  568. return 0;
  569. iwl_init_notification_wait(&mvm->notif_wait,
  570. &calib_wait,
  571. init_complete,
  572. ARRAY_SIZE(init_complete),
  573. iwl_wait_phy_db_entry,
  574. mvm->phy_db);
  575. /* Will also start the device */
  576. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
  577. if (ret) {
  578. IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
  579. goto error;
  580. }
  581. ret = iwl_send_bt_init_conf(mvm);
  582. if (ret)
  583. goto error;
  584. /* Read the NVM only at driver load time, no need to do this twice */
  585. if (read_nvm) {
  586. /* Read nvm */
  587. ret = iwl_nvm_init(mvm, true);
  588. if (ret) {
  589. IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
  590. goto error;
  591. }
  592. }
  593. /* In case we read the NVM from external file, load it to the NIC */
  594. if (mvm->nvm_file_name)
  595. iwl_mvm_load_nvm_to_nic(mvm);
  596. ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
  597. WARN_ON(ret);
  598. /*
  599. * abort after reading the nvm in case RF Kill is on, we will complete
  600. * the init seq later when RF kill will switch to off
  601. */
  602. if (iwl_mvm_is_radio_hw_killed(mvm)) {
  603. IWL_DEBUG_RF_KILL(mvm,
  604. "jump over all phy activities due to RF kill\n");
  605. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  606. ret = 1;
  607. goto out;
  608. }
  609. mvm->calibrating = true;
  610. /* Send TX valid antennas before triggering calibrations */
  611. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  612. if (ret)
  613. goto error;
  614. /*
  615. * Send phy configurations command to init uCode
  616. * to start the 16.0 uCode init image internal calibrations.
  617. */
  618. ret = iwl_send_phy_cfg_cmd(mvm);
  619. if (ret) {
  620. IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
  621. ret);
  622. goto error;
  623. }
  624. /*
  625. * Some things may run in the background now, but we
  626. * just wait for the calibration complete notification.
  627. */
  628. ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
  629. MVM_UCODE_CALIB_TIMEOUT);
  630. if (ret && iwl_mvm_is_radio_hw_killed(mvm)) {
  631. IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
  632. ret = 1;
  633. }
  634. goto out;
  635. error:
  636. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  637. out:
  638. mvm->calibrating = false;
  639. if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
  640. /* we want to debug INIT and we have no NVM - fake */
  641. mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
  642. sizeof(struct ieee80211_channel) +
  643. sizeof(struct ieee80211_rate),
  644. GFP_KERNEL);
  645. if (!mvm->nvm_data)
  646. return -ENOMEM;
  647. mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
  648. mvm->nvm_data->bands[0].n_channels = 1;
  649. mvm->nvm_data->bands[0].n_bitrates = 1;
  650. mvm->nvm_data->bands[0].bitrates =
  651. (void *)mvm->nvm_data->channels + 1;
  652. mvm->nvm_data->bands[0].bitrates->hw_value = 10;
  653. }
  654. return ret;
  655. }
  656. static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
  657. {
  658. struct iwl_host_cmd cmd = {
  659. .id = SHARED_MEM_CFG,
  660. .flags = CMD_WANT_SKB,
  661. .data = { NULL, },
  662. .len = { 0, },
  663. };
  664. struct iwl_rx_packet *pkt;
  665. struct iwl_shared_mem_cfg *mem_cfg;
  666. u32 i;
  667. lockdep_assert_held(&mvm->mutex);
  668. if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
  669. return;
  670. pkt = cmd.resp_pkt;
  671. mem_cfg = (void *)pkt->data;
  672. mvm->shared_mem_cfg.shared_mem_addr =
  673. le32_to_cpu(mem_cfg->shared_mem_addr);
  674. mvm->shared_mem_cfg.shared_mem_size =
  675. le32_to_cpu(mem_cfg->shared_mem_size);
  676. mvm->shared_mem_cfg.sample_buff_addr =
  677. le32_to_cpu(mem_cfg->sample_buff_addr);
  678. mvm->shared_mem_cfg.sample_buff_size =
  679. le32_to_cpu(mem_cfg->sample_buff_size);
  680. mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr);
  681. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++)
  682. mvm->shared_mem_cfg.txfifo_size[i] =
  683. le32_to_cpu(mem_cfg->txfifo_size[i]);
  684. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
  685. mvm->shared_mem_cfg.rxfifo_size[i] =
  686. le32_to_cpu(mem_cfg->rxfifo_size[i]);
  687. mvm->shared_mem_cfg.page_buff_addr =
  688. le32_to_cpu(mem_cfg->page_buff_addr);
  689. mvm->shared_mem_cfg.page_buff_size =
  690. le32_to_cpu(mem_cfg->page_buff_size);
  691. IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
  692. iwl_free_resp(&cmd);
  693. }
  694. int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
  695. struct iwl_mvm_dump_desc *desc,
  696. struct iwl_fw_dbg_trigger_tlv *trigger)
  697. {
  698. unsigned int delay = 0;
  699. if (trigger)
  700. delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
  701. if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
  702. return -EBUSY;
  703. if (WARN_ON(mvm->fw_dump_desc))
  704. iwl_mvm_free_fw_dump_desc(mvm);
  705. IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
  706. le32_to_cpu(desc->trig_desc.type));
  707. mvm->fw_dump_desc = desc;
  708. mvm->fw_dump_trig = trigger;
  709. queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay);
  710. return 0;
  711. }
  712. int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
  713. const char *str, size_t len,
  714. struct iwl_fw_dbg_trigger_tlv *trigger)
  715. {
  716. struct iwl_mvm_dump_desc *desc;
  717. desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
  718. if (!desc)
  719. return -ENOMEM;
  720. desc->len = len;
  721. desc->trig_desc.type = cpu_to_le32(trig);
  722. memcpy(desc->trig_desc.data, str, len);
  723. return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
  724. }
  725. int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
  726. struct iwl_fw_dbg_trigger_tlv *trigger,
  727. const char *fmt, ...)
  728. {
  729. u16 occurrences = le16_to_cpu(trigger->occurrences);
  730. int ret, len = 0;
  731. char buf[64];
  732. if (!occurrences)
  733. return 0;
  734. if (fmt) {
  735. va_list ap;
  736. buf[sizeof(buf) - 1] = '\0';
  737. va_start(ap, fmt);
  738. vsnprintf(buf, sizeof(buf), fmt, ap);
  739. va_end(ap);
  740. /* check for truncation */
  741. if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
  742. buf[sizeof(buf) - 1] = '\0';
  743. len = strlen(buf) + 1;
  744. }
  745. ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
  746. trigger);
  747. if (ret)
  748. return ret;
  749. trigger->occurrences = cpu_to_le16(occurrences - 1);
  750. return 0;
  751. }
  752. static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
  753. {
  754. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
  755. iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
  756. else
  757. iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
  758. }
  759. int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
  760. {
  761. u8 *ptr;
  762. int ret;
  763. int i;
  764. if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
  765. "Invalid configuration %d\n", conf_id))
  766. return -EINVAL;
  767. /* EARLY START - firmware's configuration is hard coded */
  768. if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
  769. !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
  770. conf_id == FW_DBG_START_FROM_ALIVE) {
  771. iwl_mvm_restart_early_start(mvm);
  772. return 0;
  773. }
  774. if (!mvm->fw->dbg_conf_tlv[conf_id])
  775. return -EINVAL;
  776. if (mvm->fw_dbg_conf != FW_DBG_INVALID)
  777. IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
  778. mvm->fw_dbg_conf);
  779. /* Send all HCMDs for configuring the FW debug */
  780. ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
  781. for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
  782. struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
  783. ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
  784. le16_to_cpu(cmd->len), cmd->data);
  785. if (ret)
  786. return ret;
  787. ptr += sizeof(*cmd);
  788. ptr += le16_to_cpu(cmd->len);
  789. }
  790. mvm->fw_dbg_conf = conf_id;
  791. return ret;
  792. }
  793. static int iwl_mvm_config_ltr_v1(struct iwl_mvm *mvm)
  794. {
  795. struct iwl_ltr_config_cmd_v1 cmd_v1 = {
  796. .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
  797. };
  798. if (!mvm->trans->ltr_enabled)
  799. return 0;
  800. return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
  801. sizeof(cmd_v1), &cmd_v1);
  802. }
  803. static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
  804. {
  805. struct iwl_ltr_config_cmd cmd = {
  806. .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
  807. };
  808. if (!mvm->trans->ltr_enabled)
  809. return 0;
  810. if (!fw_has_api(&mvm->fw->ucode_capa, IWL_UCODE_TLV_API_HDC_PHASE_0))
  811. return iwl_mvm_config_ltr_v1(mvm);
  812. return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
  813. sizeof(cmd), &cmd);
  814. }
  815. int iwl_mvm_up(struct iwl_mvm *mvm)
  816. {
  817. int ret, i;
  818. struct ieee80211_channel *chan;
  819. struct cfg80211_chan_def chandef;
  820. lockdep_assert_held(&mvm->mutex);
  821. ret = iwl_trans_start_hw(mvm->trans);
  822. if (ret)
  823. return ret;
  824. /*
  825. * If we haven't completed the run of the init ucode during
  826. * module loading, load init ucode now
  827. * (for example, if we were in RFKILL)
  828. */
  829. ret = iwl_run_init_mvm_ucode(mvm, false);
  830. if (ret && !iwlmvm_mod_params.init_dbg) {
  831. IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
  832. /* this can't happen */
  833. if (WARN_ON(ret > 0))
  834. ret = -ERFKILL;
  835. goto error;
  836. }
  837. if (!iwlmvm_mod_params.init_dbg) {
  838. /*
  839. * Stop and start the transport without entering low power
  840. * mode. This will save the state of other components on the
  841. * device that are triggered by the INIT firwmare (MFUART).
  842. */
  843. _iwl_trans_stop_device(mvm->trans, false);
  844. ret = _iwl_trans_start_hw(mvm->trans, false);
  845. if (ret)
  846. goto error;
  847. }
  848. if (iwlmvm_mod_params.init_dbg)
  849. return 0;
  850. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
  851. if (ret) {
  852. IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
  853. goto error;
  854. }
  855. iwl_mvm_get_shared_mem_conf(mvm);
  856. ret = iwl_mvm_sf_update(mvm, NULL, false);
  857. if (ret)
  858. IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
  859. mvm->fw_dbg_conf = FW_DBG_INVALID;
  860. /* if we have a destination, assume EARLY START */
  861. if (mvm->fw->dbg_dest_tlv)
  862. mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
  863. iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
  864. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  865. if (ret)
  866. goto error;
  867. ret = iwl_send_bt_init_conf(mvm);
  868. if (ret)
  869. goto error;
  870. /* Send phy db control command and then phy db calibration*/
  871. ret = iwl_send_phy_db_data(mvm->phy_db);
  872. if (ret)
  873. goto error;
  874. ret = iwl_send_phy_cfg_cmd(mvm);
  875. if (ret)
  876. goto error;
  877. /* init the fw <-> mac80211 STA mapping */
  878. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  879. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  880. mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
  881. /* reset quota debouncing buffer - 0xff will yield invalid data */
  882. memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
  883. /* Add auxiliary station for scanning */
  884. ret = iwl_mvm_add_aux_sta(mvm);
  885. if (ret)
  886. goto error;
  887. /* Add all the PHY contexts */
  888. chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0];
  889. cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
  890. for (i = 0; i < NUM_PHY_CTX; i++) {
  891. /*
  892. * The channel used here isn't relevant as it's
  893. * going to be overwritten in the other flows.
  894. * For now use the first channel we have.
  895. */
  896. ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
  897. &chandef, 1, 1);
  898. if (ret)
  899. goto error;
  900. }
  901. /* Initialize tx backoffs to the minimal possible */
  902. iwl_mvm_tt_tx_backoff(mvm, 0);
  903. WARN_ON(iwl_mvm_config_ltr(mvm));
  904. ret = iwl_mvm_power_update_device(mvm);
  905. if (ret)
  906. goto error;
  907. /*
  908. * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
  909. * anyway, so don't init MCC.
  910. */
  911. if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
  912. ret = iwl_mvm_init_mcc(mvm);
  913. if (ret)
  914. goto error;
  915. }
  916. if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
  917. ret = iwl_mvm_config_scan(mvm);
  918. if (ret)
  919. goto error;
  920. }
  921. if (iwl_mvm_is_csum_supported(mvm) &&
  922. mvm->cfg->features & NETIF_F_RXCSUM)
  923. iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
  924. /* allow FW/transport low power modes if not during restart */
  925. if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
  926. iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
  927. IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
  928. return 0;
  929. error:
  930. iwl_trans_stop_device(mvm->trans);
  931. return ret;
  932. }
  933. int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
  934. {
  935. int ret, i;
  936. lockdep_assert_held(&mvm->mutex);
  937. ret = iwl_trans_start_hw(mvm->trans);
  938. if (ret)
  939. return ret;
  940. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
  941. if (ret) {
  942. IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
  943. goto error;
  944. }
  945. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  946. if (ret)
  947. goto error;
  948. /* Send phy db control command and then phy db calibration*/
  949. ret = iwl_send_phy_db_data(mvm->phy_db);
  950. if (ret)
  951. goto error;
  952. ret = iwl_send_phy_cfg_cmd(mvm);
  953. if (ret)
  954. goto error;
  955. /* init the fw <-> mac80211 STA mapping */
  956. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  957. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  958. /* Add auxiliary station for scanning */
  959. ret = iwl_mvm_add_aux_sta(mvm);
  960. if (ret)
  961. goto error;
  962. return 0;
  963. error:
  964. iwl_trans_stop_device(mvm->trans);
  965. return ret;
  966. }
  967. void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
  968. struct iwl_rx_cmd_buffer *rxb)
  969. {
  970. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  971. struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
  972. u32 flags = le32_to_cpu(card_state_notif->flags);
  973. IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
  974. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  975. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  976. (flags & CT_KILL_CARD_DISABLED) ?
  977. "Reached" : "Not reached");
  978. }
  979. void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
  980. struct iwl_rx_cmd_buffer *rxb)
  981. {
  982. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  983. struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
  984. IWL_DEBUG_INFO(mvm,
  985. "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
  986. le32_to_cpu(mfuart_notif->installed_ver),
  987. le32_to_cpu(mfuart_notif->external_ver),
  988. le32_to_cpu(mfuart_notif->status),
  989. le32_to_cpu(mfuart_notif->duration));
  990. }