htc_drv_init.c 26 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  17. #include "htc.h"
  18. MODULE_AUTHOR("Atheros Communications");
  19. MODULE_LICENSE("Dual BSD/GPL");
  20. MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices");
  21. static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  22. module_param_named(debug, ath9k_debug, uint, 0);
  23. MODULE_PARM_DESC(debug, "Debugging mask");
  24. int htc_modparam_nohwcrypt;
  25. module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444);
  26. MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  27. static int ath9k_htc_btcoex_enable;
  28. module_param_named(btcoex_enable, ath9k_htc_btcoex_enable, int, 0444);
  29. MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  30. static int ath9k_ps_enable;
  31. module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
  32. MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
  33. #ifdef CONFIG_MAC80211_LEDS
  34. int ath9k_htc_led_blink = 1;
  35. module_param_named(blink, ath9k_htc_led_blink, int, 0444);
  36. MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  37. static const struct ieee80211_tpt_blink ath9k_htc_tpt_blink[] = {
  38. { .throughput = 0 * 1024, .blink_time = 334 },
  39. { .throughput = 1 * 1024, .blink_time = 260 },
  40. { .throughput = 5 * 1024, .blink_time = 220 },
  41. { .throughput = 10 * 1024, .blink_time = 190 },
  42. { .throughput = 20 * 1024, .blink_time = 170 },
  43. { .throughput = 50 * 1024, .blink_time = 150 },
  44. { .throughput = 70 * 1024, .blink_time = 130 },
  45. { .throughput = 100 * 1024, .blink_time = 110 },
  46. { .throughput = 200 * 1024, .blink_time = 80 },
  47. { .throughput = 300 * 1024, .blink_time = 50 },
  48. };
  49. #endif
  50. static void ath9k_htc_op_ps_wakeup(struct ath_common *common)
  51. {
  52. ath9k_htc_ps_wakeup((struct ath9k_htc_priv *) common->priv);
  53. }
  54. static void ath9k_htc_op_ps_restore(struct ath_common *common)
  55. {
  56. ath9k_htc_ps_restore((struct ath9k_htc_priv *) common->priv);
  57. }
  58. static struct ath_ps_ops ath9k_htc_ps_ops = {
  59. .wakeup = ath9k_htc_op_ps_wakeup,
  60. .restore = ath9k_htc_op_ps_restore,
  61. };
  62. static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv)
  63. {
  64. unsigned long time_left;
  65. if (atomic_read(&priv->htc->tgt_ready) > 0) {
  66. atomic_dec(&priv->htc->tgt_ready);
  67. return 0;
  68. }
  69. /* Firmware can take up to 50ms to get ready, to be safe use 1 second */
  70. time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ);
  71. if (!time_left) {
  72. dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n");
  73. return -ETIMEDOUT;
  74. }
  75. atomic_dec(&priv->htc->tgt_ready);
  76. return 0;
  77. }
  78. static void ath9k_deinit_priv(struct ath9k_htc_priv *priv)
  79. {
  80. ath9k_hw_deinit(priv->ah);
  81. kfree(priv->ah);
  82. priv->ah = NULL;
  83. }
  84. static void ath9k_deinit_device(struct ath9k_htc_priv *priv)
  85. {
  86. struct ieee80211_hw *hw = priv->hw;
  87. wiphy_rfkill_stop_polling(hw->wiphy);
  88. ath9k_deinit_leds(priv);
  89. ath9k_htc_deinit_debug(priv);
  90. ieee80211_unregister_hw(hw);
  91. ath9k_rx_cleanup(priv);
  92. ath9k_tx_cleanup(priv);
  93. ath9k_deinit_priv(priv);
  94. }
  95. static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv,
  96. u16 service_id,
  97. void (*tx) (void *,
  98. struct sk_buff *,
  99. enum htc_endpoint_id,
  100. bool txok),
  101. enum htc_endpoint_id *ep_id)
  102. {
  103. struct htc_service_connreq req;
  104. memset(&req, 0, sizeof(struct htc_service_connreq));
  105. req.service_id = service_id;
  106. req.ep_callbacks.priv = priv;
  107. req.ep_callbacks.rx = ath9k_htc_rxep;
  108. req.ep_callbacks.tx = tx;
  109. return htc_connect_service(priv->htc, &req, ep_id);
  110. }
  111. static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid,
  112. u32 drv_info)
  113. {
  114. int ret;
  115. /* WMI CMD*/
  116. ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep);
  117. if (ret)
  118. goto err;
  119. /* Beacon */
  120. ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep,
  121. &priv->beacon_ep);
  122. if (ret)
  123. goto err;
  124. /* CAB */
  125. ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep,
  126. &priv->cab_ep);
  127. if (ret)
  128. goto err;
  129. /* UAPSD */
  130. ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep,
  131. &priv->uapsd_ep);
  132. if (ret)
  133. goto err;
  134. /* MGMT */
  135. ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep,
  136. &priv->mgmt_ep);
  137. if (ret)
  138. goto err;
  139. /* DATA BE */
  140. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep,
  141. &priv->data_be_ep);
  142. if (ret)
  143. goto err;
  144. /* DATA BK */
  145. ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep,
  146. &priv->data_bk_ep);
  147. if (ret)
  148. goto err;
  149. /* DATA VI */
  150. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep,
  151. &priv->data_vi_ep);
  152. if (ret)
  153. goto err;
  154. /* DATA VO */
  155. ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep,
  156. &priv->data_vo_ep);
  157. if (ret)
  158. goto err;
  159. /*
  160. * Setup required credits before initializing HTC.
  161. * This is a bit hacky, but, since queuing is done in
  162. * the HIF layer, shouldn't matter much.
  163. */
  164. if (IS_AR7010_DEVICE(drv_info))
  165. priv->htc->credits = 45;
  166. else
  167. priv->htc->credits = 33;
  168. ret = htc_init(priv->htc);
  169. if (ret)
  170. goto err;
  171. dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n",
  172. priv->htc->credits);
  173. return 0;
  174. err:
  175. dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n");
  176. return ret;
  177. }
  178. static void ath9k_reg_notifier(struct wiphy *wiphy,
  179. struct regulatory_request *request)
  180. {
  181. struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
  182. struct ath9k_htc_priv *priv = hw->priv;
  183. ath_reg_notifier_apply(wiphy, request,
  184. ath9k_hw_regulatory(priv->ah));
  185. }
  186. static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset)
  187. {
  188. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  189. struct ath_common *common = ath9k_hw_common(ah);
  190. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  191. __be32 val, reg = cpu_to_be32(reg_offset);
  192. int r;
  193. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  194. (u8 *) &reg, sizeof(reg),
  195. (u8 *) &val, sizeof(val),
  196. 100);
  197. if (unlikely(r)) {
  198. ath_dbg(common, WMI, "REGISTER READ FAILED: (0x%04x, %d)\n",
  199. reg_offset, r);
  200. return -EIO;
  201. }
  202. return be32_to_cpu(val);
  203. }
  204. static void ath9k_multi_regread(void *hw_priv, u32 *addr,
  205. u32 *val, u16 count)
  206. {
  207. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  208. struct ath_common *common = ath9k_hw_common(ah);
  209. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  210. __be32 tmpaddr[8];
  211. __be32 tmpval[8];
  212. int i, ret;
  213. for (i = 0; i < count; i++) {
  214. tmpaddr[i] = cpu_to_be32(addr[i]);
  215. }
  216. ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID,
  217. (u8 *)tmpaddr , sizeof(u32) * count,
  218. (u8 *)tmpval, sizeof(u32) * count,
  219. 100);
  220. if (unlikely(ret)) {
  221. ath_dbg(common, WMI,
  222. "Multiple REGISTER READ FAILED (count: %d)\n", count);
  223. }
  224. for (i = 0; i < count; i++) {
  225. val[i] = be32_to_cpu(tmpval[i]);
  226. }
  227. }
  228. static void ath9k_regwrite_multi(struct ath_common *common)
  229. {
  230. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  231. u32 rsp_status;
  232. int r;
  233. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  234. (u8 *) &priv->wmi->multi_write,
  235. sizeof(struct register_write) * priv->wmi->multi_write_idx,
  236. (u8 *) &rsp_status, sizeof(rsp_status),
  237. 100);
  238. if (unlikely(r)) {
  239. ath_dbg(common, WMI,
  240. "REGISTER WRITE FAILED, multi len: %d\n",
  241. priv->wmi->multi_write_idx);
  242. }
  243. priv->wmi->multi_write_idx = 0;
  244. }
  245. static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset)
  246. {
  247. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  248. struct ath_common *common = ath9k_hw_common(ah);
  249. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  250. const __be32 buf[2] = {
  251. cpu_to_be32(reg_offset),
  252. cpu_to_be32(val),
  253. };
  254. int r;
  255. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID,
  256. (u8 *) &buf, sizeof(buf),
  257. (u8 *) &val, sizeof(val),
  258. 100);
  259. if (unlikely(r)) {
  260. ath_dbg(common, WMI, "REGISTER WRITE FAILED:(0x%04x, %d)\n",
  261. reg_offset, r);
  262. }
  263. }
  264. static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset)
  265. {
  266. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  267. struct ath_common *common = ath9k_hw_common(ah);
  268. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  269. mutex_lock(&priv->wmi->multi_write_mutex);
  270. /* Store the register/value */
  271. priv->wmi->multi_write[priv->wmi->multi_write_idx].reg =
  272. cpu_to_be32(reg_offset);
  273. priv->wmi->multi_write[priv->wmi->multi_write_idx].val =
  274. cpu_to_be32(val);
  275. priv->wmi->multi_write_idx++;
  276. /* If the buffer is full, send it out. */
  277. if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER)
  278. ath9k_regwrite_multi(common);
  279. mutex_unlock(&priv->wmi->multi_write_mutex);
  280. }
  281. static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset)
  282. {
  283. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  284. struct ath_common *common = ath9k_hw_common(ah);
  285. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  286. if (atomic_read(&priv->wmi->mwrite_cnt))
  287. ath9k_regwrite_buffer(hw_priv, val, reg_offset);
  288. else
  289. ath9k_regwrite_single(hw_priv, val, reg_offset);
  290. }
  291. static void ath9k_enable_regwrite_buffer(void *hw_priv)
  292. {
  293. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  294. struct ath_common *common = ath9k_hw_common(ah);
  295. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  296. atomic_inc(&priv->wmi->mwrite_cnt);
  297. }
  298. static void ath9k_regwrite_flush(void *hw_priv)
  299. {
  300. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  301. struct ath_common *common = ath9k_hw_common(ah);
  302. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  303. atomic_dec(&priv->wmi->mwrite_cnt);
  304. mutex_lock(&priv->wmi->multi_write_mutex);
  305. if (priv->wmi->multi_write_idx)
  306. ath9k_regwrite_multi(common);
  307. mutex_unlock(&priv->wmi->multi_write_mutex);
  308. }
  309. static void ath9k_reg_rmw_buffer(void *hw_priv,
  310. u32 reg_offset, u32 set, u32 clr)
  311. {
  312. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  313. struct ath_common *common = ath9k_hw_common(ah);
  314. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  315. u32 rsp_status;
  316. int r;
  317. mutex_lock(&priv->wmi->multi_rmw_mutex);
  318. /* Store the register/value */
  319. priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].reg =
  320. cpu_to_be32(reg_offset);
  321. priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].set =
  322. cpu_to_be32(set);
  323. priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].clr =
  324. cpu_to_be32(clr);
  325. priv->wmi->multi_rmw_idx++;
  326. /* If the buffer is full, send it out. */
  327. if (priv->wmi->multi_rmw_idx == MAX_RMW_CMD_NUMBER) {
  328. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
  329. (u8 *) &priv->wmi->multi_rmw,
  330. sizeof(struct register_write) * priv->wmi->multi_rmw_idx,
  331. (u8 *) &rsp_status, sizeof(rsp_status),
  332. 100);
  333. if (unlikely(r)) {
  334. ath_dbg(common, WMI,
  335. "REGISTER RMW FAILED, multi len: %d\n",
  336. priv->wmi->multi_rmw_idx);
  337. }
  338. priv->wmi->multi_rmw_idx = 0;
  339. }
  340. mutex_unlock(&priv->wmi->multi_rmw_mutex);
  341. }
  342. static void ath9k_reg_rmw_flush(void *hw_priv)
  343. {
  344. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  345. struct ath_common *common = ath9k_hw_common(ah);
  346. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  347. u32 rsp_status;
  348. int r;
  349. if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags))
  350. return;
  351. atomic_dec(&priv->wmi->m_rmw_cnt);
  352. mutex_lock(&priv->wmi->multi_rmw_mutex);
  353. if (priv->wmi->multi_rmw_idx) {
  354. r = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
  355. (u8 *) &priv->wmi->multi_rmw,
  356. sizeof(struct register_rmw) * priv->wmi->multi_rmw_idx,
  357. (u8 *) &rsp_status, sizeof(rsp_status),
  358. 100);
  359. if (unlikely(r)) {
  360. ath_dbg(common, WMI,
  361. "REGISTER RMW FAILED, multi len: %d\n",
  362. priv->wmi->multi_rmw_idx);
  363. }
  364. priv->wmi->multi_rmw_idx = 0;
  365. }
  366. mutex_unlock(&priv->wmi->multi_rmw_mutex);
  367. }
  368. static void ath9k_enable_rmw_buffer(void *hw_priv)
  369. {
  370. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  371. struct ath_common *common = ath9k_hw_common(ah);
  372. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  373. if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags))
  374. return;
  375. atomic_inc(&priv->wmi->m_rmw_cnt);
  376. }
  377. static u32 ath9k_reg_rmw_single(void *hw_priv,
  378. u32 reg_offset, u32 set, u32 clr)
  379. {
  380. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  381. struct ath_common *common = ath9k_hw_common(ah);
  382. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  383. struct register_rmw buf, buf_ret;
  384. int ret;
  385. u32 val = 0;
  386. buf.reg = cpu_to_be32(reg_offset);
  387. buf.set = cpu_to_be32(set);
  388. buf.clr = cpu_to_be32(clr);
  389. ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
  390. (u8 *) &buf, sizeof(buf),
  391. (u8 *) &buf_ret, sizeof(buf_ret),
  392. 100);
  393. if (unlikely(ret)) {
  394. ath_dbg(common, WMI, "REGISTER RMW FAILED:(0x%04x, %d)\n",
  395. reg_offset, ret);
  396. }
  397. return val;
  398. }
  399. static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
  400. {
  401. struct ath_hw *ah = (struct ath_hw *) hw_priv;
  402. struct ath_common *common = ath9k_hw_common(ah);
  403. struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
  404. if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags)) {
  405. u32 val;
  406. val = REG_READ(ah, reg_offset);
  407. val &= ~clr;
  408. val |= set;
  409. REG_WRITE(ah, reg_offset, val);
  410. return 0;
  411. }
  412. if (atomic_read(&priv->wmi->m_rmw_cnt))
  413. ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr);
  414. else
  415. ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr);
  416. return 0;
  417. }
  418. static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
  419. {
  420. *csz = L1_CACHE_BYTES >> 2;
  421. }
  422. static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data)
  423. {
  424. struct ath_hw *ah = (struct ath_hw *) common->ah;
  425. (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
  426. if (!ath9k_hw_wait(ah,
  427. AR_EEPROM_STATUS_DATA,
  428. AR_EEPROM_STATUS_DATA_BUSY |
  429. AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0,
  430. AH_WAIT_TIMEOUT))
  431. return false;
  432. *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
  433. AR_EEPROM_STATUS_DATA_VAL);
  434. return true;
  435. }
  436. static const struct ath_bus_ops ath9k_usb_bus_ops = {
  437. .ath_bus_type = ATH_USB,
  438. .read_cachesize = ath_usb_read_cachesize,
  439. .eeprom_read = ath_usb_eeprom_read,
  440. };
  441. static int ath9k_init_queues(struct ath9k_htc_priv *priv)
  442. {
  443. struct ath_common *common = ath9k_hw_common(priv->ah);
  444. int i;
  445. for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++)
  446. priv->hwq_map[i] = -1;
  447. priv->beacon.beaconq = ath9k_hw_beaconq_setup(priv->ah);
  448. if (priv->beacon.beaconq == -1) {
  449. ath_err(common, "Unable to setup BEACON xmit queue\n");
  450. goto err;
  451. }
  452. priv->cabq = ath9k_htc_cabq_setup(priv);
  453. if (priv->cabq == -1) {
  454. ath_err(common, "Unable to setup CAB xmit queue\n");
  455. goto err;
  456. }
  457. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BE)) {
  458. ath_err(common, "Unable to setup xmit queue for BE traffic\n");
  459. goto err;
  460. }
  461. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_BK)) {
  462. ath_err(common, "Unable to setup xmit queue for BK traffic\n");
  463. goto err;
  464. }
  465. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VI)) {
  466. ath_err(common, "Unable to setup xmit queue for VI traffic\n");
  467. goto err;
  468. }
  469. if (!ath9k_htc_txq_setup(priv, IEEE80211_AC_VO)) {
  470. ath_err(common, "Unable to setup xmit queue for VO traffic\n");
  471. goto err;
  472. }
  473. return 0;
  474. err:
  475. return -EINVAL;
  476. }
  477. static void ath9k_init_misc(struct ath9k_htc_priv *priv)
  478. {
  479. struct ath_common *common = ath9k_hw_common(priv->ah);
  480. memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
  481. common->last_rssi = ATH_RSSI_DUMMY_MARKER;
  482. priv->ah->opmode = NL80211_IFTYPE_STATION;
  483. priv->spec_priv.ah = priv->ah;
  484. priv->spec_priv.spec_config.enabled = 0;
  485. priv->spec_priv.spec_config.short_repeat = true;
  486. priv->spec_priv.spec_config.count = 8;
  487. priv->spec_priv.spec_config.endless = false;
  488. priv->spec_priv.spec_config.period = 0x12;
  489. priv->spec_priv.spec_config.fft_period = 0x02;
  490. }
  491. static int ath9k_init_priv(struct ath9k_htc_priv *priv,
  492. u16 devid, char *product,
  493. u32 drv_info)
  494. {
  495. struct ath_hw *ah = NULL;
  496. struct ath_common *common;
  497. int i, ret = 0, csz = 0;
  498. ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
  499. if (!ah)
  500. return -ENOMEM;
  501. ah->dev = priv->dev;
  502. ah->hw = priv->hw;
  503. ah->hw_version.devid = devid;
  504. ah->hw_version.usbdev = drv_info;
  505. ah->ah_flags |= AH_USE_EEPROM;
  506. ah->reg_ops.read = ath9k_regread;
  507. ah->reg_ops.multi_read = ath9k_multi_regread;
  508. ah->reg_ops.write = ath9k_regwrite;
  509. ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
  510. ah->reg_ops.write_flush = ath9k_regwrite_flush;
  511. ah->reg_ops.enable_rmw_buffer = ath9k_enable_rmw_buffer;
  512. ah->reg_ops.rmw_flush = ath9k_reg_rmw_flush;
  513. ah->reg_ops.rmw = ath9k_reg_rmw;
  514. priv->ah = ah;
  515. common = ath9k_hw_common(ah);
  516. common->ops = &ah->reg_ops;
  517. common->ps_ops = &ath9k_htc_ps_ops;
  518. common->bus_ops = &ath9k_usb_bus_ops;
  519. common->ah = ah;
  520. common->hw = priv->hw;
  521. common->priv = priv;
  522. common->debug_mask = ath9k_debug;
  523. common->btcoex_enabled = ath9k_htc_btcoex_enable == 1;
  524. set_bit(ATH_OP_INVALID, &common->op_flags);
  525. spin_lock_init(&priv->beacon_lock);
  526. spin_lock_init(&priv->tx.tx_lock);
  527. mutex_init(&priv->mutex);
  528. mutex_init(&priv->htc_pm_lock);
  529. tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet,
  530. (unsigned long)priv);
  531. tasklet_init(&priv->tx_failed_tasklet, ath9k_tx_failed_tasklet,
  532. (unsigned long)priv);
  533. INIT_DELAYED_WORK(&priv->ani_work, ath9k_htc_ani_work);
  534. INIT_WORK(&priv->ps_work, ath9k_ps_work);
  535. INIT_WORK(&priv->fatal_work, ath9k_fatal_work);
  536. setup_timer(&priv->tx.cleanup_timer, ath9k_htc_tx_cleanup_timer,
  537. (unsigned long)priv);
  538. /*
  539. * Cache line size is used to size and align various
  540. * structures used to communicate with the hardware.
  541. */
  542. ath_read_cachesize(common, &csz);
  543. common->cachelsz = csz << 2; /* convert to bytes */
  544. ret = ath9k_hw_init(ah);
  545. if (ret) {
  546. ath_err(common,
  547. "Unable to initialize hardware; initialization status: %d\n",
  548. ret);
  549. goto err_hw;
  550. }
  551. ret = ath9k_init_queues(priv);
  552. if (ret)
  553. goto err_queues;
  554. for (i = 0; i < ATH9K_HTC_MAX_BCN_VIF; i++)
  555. priv->beacon.bslot[i] = NULL;
  556. priv->beacon.slottime = ATH9K_SLOT_TIME_9;
  557. ath9k_cmn_init_channels_rates(common);
  558. ath9k_cmn_init_crypto(ah);
  559. ath9k_init_misc(priv);
  560. ath9k_htc_init_btcoex(priv, product);
  561. return 0;
  562. err_queues:
  563. ath9k_hw_deinit(ah);
  564. err_hw:
  565. kfree(ah);
  566. priv->ah = NULL;
  567. return ret;
  568. }
  569. static const struct ieee80211_iface_limit if_limits[] = {
  570. { .max = 2, .types = BIT(NL80211_IFTYPE_STATION) |
  571. BIT(NL80211_IFTYPE_P2P_CLIENT) },
  572. { .max = 2, .types = BIT(NL80211_IFTYPE_AP) |
  573. #ifdef CONFIG_MAC80211_MESH
  574. BIT(NL80211_IFTYPE_MESH_POINT) |
  575. #endif
  576. BIT(NL80211_IFTYPE_P2P_GO) },
  577. };
  578. static const struct ieee80211_iface_combination if_comb = {
  579. .limits = if_limits,
  580. .n_limits = ARRAY_SIZE(if_limits),
  581. .max_interfaces = 2,
  582. .num_different_channels = 1,
  583. };
  584. static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv,
  585. struct ieee80211_hw *hw)
  586. {
  587. struct ath_hw *ah = priv->ah;
  588. struct ath_common *common = ath9k_hw_common(priv->ah);
  589. struct base_eep_header *pBase;
  590. ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
  591. ieee80211_hw_set(hw, MFP_CAPABLE);
  592. ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
  593. ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
  594. ieee80211_hw_set(hw, RX_INCLUDES_FCS);
  595. ieee80211_hw_set(hw, HAS_RATE_CONTROL);
  596. ieee80211_hw_set(hw, SPECTRUM_MGMT);
  597. ieee80211_hw_set(hw, SIGNAL_DBM);
  598. ieee80211_hw_set(hw, AMPDU_AGGREGATION);
  599. if (ath9k_ps_enable)
  600. ieee80211_hw_set(hw, SUPPORTS_PS);
  601. hw->wiphy->interface_modes =
  602. BIT(NL80211_IFTYPE_STATION) |
  603. BIT(NL80211_IFTYPE_ADHOC) |
  604. BIT(NL80211_IFTYPE_AP) |
  605. BIT(NL80211_IFTYPE_P2P_GO) |
  606. BIT(NL80211_IFTYPE_P2P_CLIENT) |
  607. BIT(NL80211_IFTYPE_MESH_POINT);
  608. hw->wiphy->iface_combinations = &if_comb;
  609. hw->wiphy->n_iface_combinations = 1;
  610. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  611. hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN |
  612. WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL |
  613. WIPHY_FLAG_HAS_CHANNEL_SWITCH;
  614. hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
  615. hw->queues = 4;
  616. hw->max_listen_interval = 1;
  617. hw->vif_data_size = sizeof(struct ath9k_htc_vif);
  618. hw->sta_data_size = sizeof(struct ath9k_htc_sta);
  619. /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */
  620. hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) +
  621. sizeof(struct htc_frame_hdr) + 4;
  622. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
  623. hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  624. &common->sbands[IEEE80211_BAND_2GHZ];
  625. if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
  626. hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  627. &common->sbands[IEEE80211_BAND_5GHZ];
  628. ath9k_cmn_reload_chainmask(ah);
  629. pBase = ath9k_htc_get_eeprom_base(priv);
  630. if (pBase) {
  631. hw->wiphy->available_antennas_rx = pBase->rxMask;
  632. hw->wiphy->available_antennas_tx = pBase->txMask;
  633. }
  634. SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
  635. }
  636. static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
  637. {
  638. struct ieee80211_hw *hw = priv->hw;
  639. struct wmi_fw_version cmd_rsp;
  640. int ret;
  641. memset(&cmd_rsp, 0, sizeof(cmd_rsp));
  642. WMI_CMD(WMI_GET_FW_VERSION);
  643. if (ret)
  644. return -EINVAL;
  645. priv->fw_version_major = be16_to_cpu(cmd_rsp.major);
  646. priv->fw_version_minor = be16_to_cpu(cmd_rsp.minor);
  647. snprintf(hw->wiphy->fw_version, sizeof(hw->wiphy->fw_version), "%d.%d",
  648. priv->fw_version_major,
  649. priv->fw_version_minor);
  650. dev_info(priv->dev, "ath9k_htc: FW Version: %d.%d\n",
  651. priv->fw_version_major,
  652. priv->fw_version_minor);
  653. /*
  654. * Check if the available FW matches the driver's
  655. * required version.
  656. */
  657. if (priv->fw_version_major != MAJOR_VERSION_REQ ||
  658. priv->fw_version_minor < MINOR_VERSION_REQ) {
  659. dev_err(priv->dev, "ath9k_htc: Please upgrade to FW version %d.%d\n",
  660. MAJOR_VERSION_REQ, MINOR_VERSION_REQ);
  661. return -EINVAL;
  662. }
  663. if (priv->fw_version_major == 1 && priv->fw_version_minor < 4)
  664. set_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags);
  665. dev_info(priv->dev, "FW RMW support: %s\n",
  666. test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags) ? "Off" : "On");
  667. return 0;
  668. }
  669. static int ath9k_init_device(struct ath9k_htc_priv *priv,
  670. u16 devid, char *product, u32 drv_info)
  671. {
  672. struct ieee80211_hw *hw = priv->hw;
  673. struct ath_common *common;
  674. struct ath_hw *ah;
  675. int error = 0;
  676. struct ath_regulatory *reg;
  677. char hw_name[64];
  678. /* Bring up device */
  679. error = ath9k_init_priv(priv, devid, product, drv_info);
  680. if (error != 0)
  681. goto err_init;
  682. ah = priv->ah;
  683. common = ath9k_hw_common(ah);
  684. ath9k_set_hw_capab(priv, hw);
  685. error = ath9k_init_firmware_version(priv);
  686. if (error != 0)
  687. goto err_fw;
  688. /* Initialize regulatory */
  689. error = ath_regd_init(&common->regulatory, priv->hw->wiphy,
  690. ath9k_reg_notifier);
  691. if (error)
  692. goto err_regd;
  693. reg = &common->regulatory;
  694. /* Setup TX */
  695. error = ath9k_tx_init(priv);
  696. if (error != 0)
  697. goto err_tx;
  698. /* Setup RX */
  699. error = ath9k_rx_init(priv);
  700. if (error != 0)
  701. goto err_rx;
  702. ath9k_hw_disable(priv->ah);
  703. #ifdef CONFIG_MAC80211_LEDS
  704. /* must be initialized before ieee80211_register_hw */
  705. priv->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(priv->hw,
  706. IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_htc_tpt_blink,
  707. ARRAY_SIZE(ath9k_htc_tpt_blink));
  708. #endif
  709. /* Register with mac80211 */
  710. error = ieee80211_register_hw(hw);
  711. if (error)
  712. goto err_register;
  713. /* Handle world regulatory */
  714. if (!ath_is_world_regd(reg)) {
  715. error = regulatory_hint(hw->wiphy, reg->alpha2);
  716. if (error)
  717. goto err_world;
  718. }
  719. error = ath9k_htc_init_debug(priv->ah);
  720. if (error) {
  721. ath_err(common, "Unable to create debugfs files\n");
  722. goto err_world;
  723. }
  724. ath_dbg(common, CONFIG,
  725. "WMI:%d, BCN:%d, CAB:%d, UAPSD:%d, MGMT:%d, BE:%d, BK:%d, VI:%d, VO:%d\n",
  726. priv->wmi_cmd_ep,
  727. priv->beacon_ep,
  728. priv->cab_ep,
  729. priv->uapsd_ep,
  730. priv->mgmt_ep,
  731. priv->data_be_ep,
  732. priv->data_bk_ep,
  733. priv->data_vi_ep,
  734. priv->data_vo_ep);
  735. ath9k_hw_name(priv->ah, hw_name, sizeof(hw_name));
  736. wiphy_info(hw->wiphy, "%s\n", hw_name);
  737. ath9k_init_leds(priv);
  738. ath9k_start_rfkill_poll(priv);
  739. return 0;
  740. err_world:
  741. ieee80211_unregister_hw(hw);
  742. err_register:
  743. ath9k_rx_cleanup(priv);
  744. err_rx:
  745. ath9k_tx_cleanup(priv);
  746. err_tx:
  747. /* Nothing */
  748. err_regd:
  749. /* Nothing */
  750. err_fw:
  751. ath9k_deinit_priv(priv);
  752. err_init:
  753. return error;
  754. }
  755. int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev,
  756. u16 devid, char *product, u32 drv_info)
  757. {
  758. struct ieee80211_hw *hw;
  759. struct ath9k_htc_priv *priv;
  760. int ret;
  761. hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops);
  762. if (!hw)
  763. return -ENOMEM;
  764. priv = hw->priv;
  765. priv->hw = hw;
  766. priv->htc = htc_handle;
  767. priv->dev = dev;
  768. htc_handle->drv_priv = priv;
  769. SET_IEEE80211_DEV(hw, priv->dev);
  770. ret = ath9k_htc_wait_for_target(priv);
  771. if (ret)
  772. goto err_free;
  773. priv->wmi = ath9k_init_wmi(priv);
  774. if (!priv->wmi) {
  775. ret = -EINVAL;
  776. goto err_free;
  777. }
  778. ret = ath9k_init_htc_services(priv, devid, drv_info);
  779. if (ret)
  780. goto err_init;
  781. ret = ath9k_init_device(priv, devid, product, drv_info);
  782. if (ret)
  783. goto err_init;
  784. return 0;
  785. err_init:
  786. ath9k_deinit_wmi(priv);
  787. err_free:
  788. ieee80211_free_hw(hw);
  789. return ret;
  790. }
  791. void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug)
  792. {
  793. if (htc_handle->drv_priv) {
  794. /* Check if the device has been yanked out. */
  795. if (hotunplug)
  796. htc_handle->drv_priv->ah->ah_flags |= AH_UNPLUGGED;
  797. ath9k_deinit_device(htc_handle->drv_priv);
  798. ath9k_deinit_wmi(htc_handle->drv_priv);
  799. ieee80211_free_hw(htc_handle->drv_priv->hw);
  800. }
  801. }
  802. #ifdef CONFIG_PM
  803. void ath9k_htc_suspend(struct htc_target *htc_handle)
  804. {
  805. ath9k_htc_setpower(htc_handle->drv_priv, ATH9K_PM_FULL_SLEEP);
  806. }
  807. int ath9k_htc_resume(struct htc_target *htc_handle)
  808. {
  809. struct ath9k_htc_priv *priv = htc_handle->drv_priv;
  810. int ret;
  811. ret = ath9k_htc_wait_for_target(priv);
  812. if (ret)
  813. return ret;
  814. ret = ath9k_init_htc_services(priv, priv->ah->hw_version.devid,
  815. priv->ah->hw_version.usbdev);
  816. ath9k_configure_leds(priv);
  817. return ret;
  818. }
  819. #endif
  820. static int __init ath9k_htc_init(void)
  821. {
  822. if (ath9k_hif_usb_init() < 0) {
  823. pr_err("No USB devices found, driver not installed\n");
  824. return -ENODEV;
  825. }
  826. return 0;
  827. }
  828. module_init(ath9k_htc_init);
  829. static void __exit ath9k_htc_exit(void)
  830. {
  831. ath9k_hif_usb_exit();
  832. pr_info("Driver unloaded\n");
  833. }
  834. module_exit(ath9k_htc_exit);